ScheduleDAGSDNodes.cpp revision 84fbac580941548a6ab1121ed3b0ffdc4e2bc080
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAG class, which is a base class used by 11// scheduling implementation classes. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "pre-RA-sched" 16#include "ScheduleDAGSDNodes.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/raw_ostream.h" 23using namespace llvm; 24 25ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 26 : ScheduleDAG(mf) { 27} 28 29SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 30 SUnit *SU = NewSUnit(Old->getNode()); 31 SU->OrigNode = Old->OrigNode; 32 SU->Latency = Old->Latency; 33 SU->isTwoAddress = Old->isTwoAddress; 34 SU->isCommutable = Old->isCommutable; 35 SU->hasPhysRegDefs = Old->hasPhysRegDefs; 36 Old->isCloned = true; 37 return SU; 38} 39 40/// CheckForPhysRegDependency - Check if the dependency between def and use of 41/// a specified operand is a physical register dependency. If so, returns the 42/// register and the cost of copying the register. 43static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 44 const TargetRegisterInfo *TRI, 45 const TargetInstrInfo *TII, 46 unsigned &PhysReg, int &Cost) { 47 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 48 return; 49 50 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 51 if (TargetRegisterInfo::isVirtualRegister(Reg)) 52 return; 53 54 unsigned ResNo = User->getOperand(2).getResNo(); 55 if (Def->isMachineOpcode()) { 56 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 57 if (ResNo >= II.getNumDefs() && 58 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 59 PhysReg = Reg; 60 const TargetRegisterClass *RC = 61 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo)); 62 Cost = RC->getCopyCost(); 63 } 64 } 65} 66 67void ScheduleDAGSDNodes::BuildSchedUnits() { 68 // During scheduling, the NodeId field of SDNode is used to map SDNodes 69 // to their associated SUnits by holding SUnits table indices. A value 70 // of -1 means the SDNode does not yet have an associated SUnit. 71 unsigned NumNodes = 0; 72 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 73 E = DAG->allnodes_end(); NI != E; ++NI) { 74 NI->setNodeId(-1); 75 ++NumNodes; 76 } 77 78 // Reserve entries in the vector for each of the SUnits we are creating. This 79 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 80 // invalidated. 81 // FIXME: Multiply by 2 because we may clone nodes during scheduling. 82 // This is a temporary workaround. 83 SUnits.reserve(NumNodes * 2); 84 85 // Check to see if the scheduler cares about latencies. 86 bool UnitLatencies = ForceUnitLatencies(); 87 88 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 89 E = DAG->allnodes_end(); NI != E; ++NI) { 90 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 91 continue; 92 93 // If this node has already been processed, stop now. 94 if (NI->getNodeId() != -1) continue; 95 96 SUnit *NodeSUnit = NewSUnit(NI); 97 98 // See if anything is flagged to this node, if so, add them to flagged 99 // nodes. Nodes can have at most one flag input and one flag output. Flags 100 // are required the be the last operand and result of a node. 101 102 // Scan up to find flagged preds. 103 SDNode *N = NI; 104 if (N->getNumOperands() && 105 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { 106 do { 107 N = N->getOperand(N->getNumOperands()-1).getNode(); 108 assert(N->getNodeId() == -1 && "Node already inserted!"); 109 N->setNodeId(NodeSUnit->NodeNum); 110 } while (N->getNumOperands() && 111 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag); 112 } 113 114 // Scan down to find any flagged succs. 115 N = NI; 116 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { 117 SDValue FlagVal(N, N->getNumValues()-1); 118 119 // There are either zero or one users of the Flag result. 120 bool HasFlagUse = false; 121 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 122 UI != E; ++UI) 123 if (FlagVal.isOperandOf(*UI)) { 124 HasFlagUse = true; 125 assert(N->getNodeId() == -1 && "Node already inserted!"); 126 N->setNodeId(NodeSUnit->NodeNum); 127 N = *UI; 128 break; 129 } 130 if (!HasFlagUse) break; 131 } 132 133 // If there are flag operands involved, N is now the bottom-most node 134 // of the sequence of nodes that are flagged together. 135 // Update the SUnit. 136 NodeSUnit->setNode(N); 137 assert(N->getNodeId() == -1 && "Node already inserted!"); 138 N->setNodeId(NodeSUnit->NodeNum); 139 140 // Assign the Latency field of NodeSUnit using target-provided information. 141 if (UnitLatencies) 142 NodeSUnit->Latency = 1; 143 else 144 ComputeLatency(NodeSUnit); 145 } 146} 147 148void ScheduleDAGSDNodes::AddSchedEdges() { 149 // Pass 2: add the preds, succs, etc. 150 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 151 SUnit *SU = &SUnits[su]; 152 SDNode *MainNode = SU->getNode(); 153 154 if (MainNode->isMachineOpcode()) { 155 unsigned Opc = MainNode->getMachineOpcode(); 156 const TargetInstrDesc &TID = TII->get(Opc); 157 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 158 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 159 SU->isTwoAddress = true; 160 break; 161 } 162 } 163 if (TID.isCommutable()) 164 SU->isCommutable = true; 165 } 166 167 // Find all predecessors and successors of the group. 168 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) { 169 if (N->isMachineOpcode() && 170 TII->get(N->getMachineOpcode()).getImplicitDefs() && 171 CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs()) 172 SU->hasPhysRegDefs = true; 173 174 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 175 SDNode *OpN = N->getOperand(i).getNode(); 176 if (isPassiveNode(OpN)) continue; // Not scheduled. 177 SUnit *OpSU = &SUnits[OpN->getNodeId()]; 178 assert(OpSU && "Node has no SUnit!"); 179 if (OpSU == SU) continue; // In the same group. 180 181 MVT OpVT = N->getOperand(i).getValueType(); 182 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); 183 bool isChain = OpVT == MVT::Other; 184 185 unsigned PhysReg = 0; 186 int Cost = 1; 187 // Determine if this is a physical register dependency. 188 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 189 assert((PhysReg == 0 || !isChain) && 190 "Chain dependence via physreg data?"); 191 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 192 // emits a copy from the physical register to a virtual register unless 193 // it requires a cross class copy (cost < 0). That means we are only 194 // treating "expensive to copy" register dependency as physical register 195 // dependency. This may change in the future though. 196 if (Cost >= 0) 197 PhysReg = 0; 198 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data, 199 OpSU->Latency, PhysReg)); 200 } 201 } 202 } 203} 204 205/// BuildSchedGraph - Build the SUnit graph from the selection dag that we 206/// are input. This SUnit graph is similar to the SelectionDAG, but 207/// excludes nodes that aren't interesting to scheduling, and represents 208/// flagged together nodes with a single SUnit. 209void ScheduleDAGSDNodes::BuildSchedGraph() { 210 // Populate the SUnits array. 211 BuildSchedUnits(); 212 // Compute all the scheduling dependencies between nodes. 213 AddSchedEdges(); 214} 215 216void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { 217 const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 218 219 // Compute the latency for the node. We use the sum of the latencies for 220 // all nodes flagged together into this SUnit. 221 SU->Latency = 0; 222 bool SawMachineOpcode = false; 223 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) 224 if (N->isMachineOpcode()) { 225 SawMachineOpcode = true; 226 SU->Latency += 227 InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass()); 228 } 229} 230 231/// CountResults - The results of target nodes have register or immediate 232/// operands first, then an optional chain, and optional flag operands (which do 233/// not go into the resulting MachineInstr). 234unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) { 235 unsigned N = Node->getNumValues(); 236 while (N && Node->getValueType(N - 1) == MVT::Flag) 237 --N; 238 if (N && Node->getValueType(N - 1) == MVT::Other) 239 --N; // Skip over chain result. 240 return N; 241} 242 243/// CountOperands - The inputs to target nodes have any actual inputs first, 244/// followed by special operands that describe memory references, then an 245/// optional chain operand, then an optional flag operand. Compute the number 246/// of actual operands that will go into the resulting MachineInstr. 247unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) { 248 unsigned N = ComputeMemOperandsEnd(Node); 249 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode())) 250 --N; // Ignore MEMOPERAND nodes 251 return N; 252} 253 254/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode 255/// operand 256unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) { 257 unsigned N = Node->getNumOperands(); 258 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 259 --N; 260 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 261 --N; // Ignore chain if it exists. 262 return N; 263} 264 265 266void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 267 if (!SU->getNode()) { 268 cerr << "PHYS REG COPY\n"; 269 return; 270 } 271 272 SU->getNode()->dump(DAG); 273 cerr << "\n"; 274 SmallVector<SDNode *, 4> FlaggedNodes; 275 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode()) 276 FlaggedNodes.push_back(N); 277 while (!FlaggedNodes.empty()) { 278 cerr << " "; 279 FlaggedNodes.back()->dump(DAG); 280 cerr << "\n"; 281 FlaggedNodes.pop_back(); 282 } 283} 284