SelectionDAGISel.cpp revision 2aeaf4e839438d51766996006fc22310d05ab2a7
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "llvm/CallingConv.h" 17#include "llvm/Constants.h" 18#include "llvm/DerivedTypes.h" 19#include "llvm/Function.h" 20#include "llvm/Instructions.h" 21#include "llvm/Intrinsics.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Target/MRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetFrameInfo.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetLowering.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Transforms/Utils/BasicBlockUtils.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include <map> 37#include <iostream> 38using namespace llvm; 39 40// Temporary command line code to enable use of the dag combiner as a beta 41// option. 42namespace llvm { 43 bool CombinerEnabled; 44} 45namespace { 46 cl::opt<bool, true> 47 CombineDAG("enable-dag-combiner", cl::Hidden, 48 cl::desc("Run the DAG combiner before and after Legalize"), 49 cl::location(CombinerEnabled), 50 cl::init(false)); 51} 52#ifndef NDEBUG 53static cl::opt<bool> 54ViewDAGs("view-isel-dags", cl::Hidden, 55 cl::desc("Pop up a window to show isel dags as they are selected")); 56#else 57static const bool ViewDAGs = 0; 58#endif 59 60 61namespace llvm { 62 //===--------------------------------------------------------------------===// 63 /// FunctionLoweringInfo - This contains information that is global to a 64 /// function that is used when lowering a region of the function. 65 class FunctionLoweringInfo { 66 public: 67 TargetLowering &TLI; 68 Function &Fn; 69 MachineFunction &MF; 70 SSARegMap *RegMap; 71 72 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 73 74 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 75 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 76 77 /// ValueMap - Since we emit code for the function a basic block at a time, 78 /// we must remember which virtual registers hold the values for 79 /// cross-basic-block values. 80 std::map<const Value*, unsigned> ValueMap; 81 82 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 83 /// the entry block. This allows the allocas to be efficiently referenced 84 /// anywhere in the function. 85 std::map<const AllocaInst*, int> StaticAllocaMap; 86 87 /// BlockLocalArguments - If any arguments are only used in a single basic 88 /// block, and if the target can access the arguments without side-effects, 89 /// avoid emitting CopyToReg nodes for those arguments. This map keeps 90 /// track of which arguments are local to each BB. 91 std::multimap<BasicBlock*, std::pair<Argument*, 92 unsigned> > BlockLocalArguments; 93 94 95 unsigned MakeReg(MVT::ValueType VT) { 96 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 97 } 98 99 unsigned CreateRegForValue(const Value *V) { 100 MVT::ValueType VT = TLI.getValueType(V->getType()); 101 // The common case is that we will only create one register for this 102 // value. If we have that case, create and return the virtual register. 103 unsigned NV = TLI.getNumElements(VT); 104 if (NV == 1) { 105 // If we are promoting this value, pick the next largest supported type. 106 return MakeReg(TLI.getTypeToTransformTo(VT)); 107 } 108 109 // If this value is represented with multiple target registers, make sure 110 // to create enough consequtive registers of the right (smaller) type. 111 unsigned NT = VT-1; // Find the type to use. 112 while (TLI.getNumElements((MVT::ValueType)NT) != 1) 113 --NT; 114 115 unsigned R = MakeReg((MVT::ValueType)NT); 116 for (unsigned i = 1; i != NV; ++i) 117 MakeReg((MVT::ValueType)NT); 118 return R; 119 } 120 121 unsigned InitializeRegForValue(const Value *V) { 122 unsigned &R = ValueMap[V]; 123 assert(R == 0 && "Already initialized this value register!"); 124 return R = CreateRegForValue(V); 125 } 126 }; 127} 128 129/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 130/// PHI nodes or outside of the basic block that defines it. 131static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 132 if (isa<PHINode>(I)) return true; 133 BasicBlock *BB = I->getParent(); 134 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 135 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI)) 136 return true; 137 return false; 138} 139 140FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 141 Function &fn, MachineFunction &mf) 142 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 143 144 // Initialize the mapping of values to registers. This is only set up for 145 // instruction values that are used outside of the block that defines 146 // them. 147 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 148 AI != E; ++AI) 149 InitializeRegForValue(AI); 150 151 Function::iterator BB = Fn.begin(), EB = Fn.end(); 152 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 153 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 154 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) { 155 const Type *Ty = AI->getAllocatedType(); 156 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); 157 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 158 159 // If the alignment of the value is smaller than the size of the value, 160 // and if the size of the value is particularly small (<= 8 bytes), 161 // round up to the size of the value for potentially better performance. 162 // 163 // FIXME: This could be made better with a preferred alignment hook in 164 // TargetData. It serves primarily to 8-byte align doubles for X86. 165 if (Align < TySize && TySize <= 8) Align = TySize; 166 167 if (CUI->getValue()) // Don't produce zero sized stack objects 168 TySize *= CUI->getValue(); // Get total allocated size. 169 StaticAllocaMap[AI] = 170 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 171 } 172 173 for (; BB != EB; ++BB) 174 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 175 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 176 if (!isa<AllocaInst>(I) || 177 !StaticAllocaMap.count(cast<AllocaInst>(I))) 178 InitializeRegForValue(I); 179 180 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 181 // also creates the initial PHI MachineInstrs, though none of the input 182 // operands are populated. 183 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 184 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 185 MBBMap[BB] = MBB; 186 MF.getBasicBlockList().push_back(MBB); 187 188 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 189 // appropriate. 190 PHINode *PN; 191 for (BasicBlock::iterator I = BB->begin(); 192 (PN = dyn_cast<PHINode>(I)); ++I) 193 if (!PN->use_empty()) { 194 unsigned NumElements = 195 TLI.getNumElements(TLI.getValueType(PN->getType())); 196 unsigned PHIReg = ValueMap[PN]; 197 assert(PHIReg &&"PHI node does not have an assigned virtual register!"); 198 for (unsigned i = 0; i != NumElements; ++i) 199 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i); 200 } 201 } 202} 203 204 205 206//===----------------------------------------------------------------------===// 207/// SelectionDAGLowering - This is the common target-independent lowering 208/// implementation that is parameterized by a TargetLowering object. 209/// Also, targets can overload any lowering method. 210/// 211namespace llvm { 212class SelectionDAGLowering { 213 MachineBasicBlock *CurMBB; 214 215 std::map<const Value*, SDOperand> NodeMap; 216 217 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 218 /// them up and then emit token factor nodes when possible. This allows us to 219 /// get simple disambiguation between loads without worrying about alias 220 /// analysis. 221 std::vector<SDOperand> PendingLoads; 222 223public: 224 // TLI - This is information that describes the available target features we 225 // need for lowering. This indicates when operations are unavailable, 226 // implemented with a libcall, etc. 227 TargetLowering &TLI; 228 SelectionDAG &DAG; 229 const TargetData &TD; 230 231 /// FuncInfo - Information about the function as a whole. 232 /// 233 FunctionLoweringInfo &FuncInfo; 234 235 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 236 FunctionLoweringInfo &funcinfo) 237 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 238 FuncInfo(funcinfo) { 239 } 240 241 /// getRoot - Return the current virtual root of the Selection DAG. 242 /// 243 SDOperand getRoot() { 244 if (PendingLoads.empty()) 245 return DAG.getRoot(); 246 247 if (PendingLoads.size() == 1) { 248 SDOperand Root = PendingLoads[0]; 249 DAG.setRoot(Root); 250 PendingLoads.clear(); 251 return Root; 252 } 253 254 // Otherwise, we have to make a token factor node. 255 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads); 256 PendingLoads.clear(); 257 DAG.setRoot(Root); 258 return Root; 259 } 260 261 void visit(Instruction &I) { visit(I.getOpcode(), I); } 262 263 void visit(unsigned Opcode, User &I) { 264 switch (Opcode) { 265 default: assert(0 && "Unknown instruction type encountered!"); 266 abort(); 267 // Build the switch statement using the Instruction.def file. 268#define HANDLE_INST(NUM, OPCODE, CLASS) \ 269 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 270#include "llvm/Instruction.def" 271 } 272 } 273 274 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 275 276 277 SDOperand getIntPtrConstant(uint64_t Val) { 278 return DAG.getConstant(Val, TLI.getPointerTy()); 279 } 280 281 SDOperand getValue(const Value *V) { 282 SDOperand &N = NodeMap[V]; 283 if (N.Val) return N; 284 285 MVT::ValueType VT = TLI.getValueType(V->getType()); 286 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) 287 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 288 visit(CE->getOpcode(), *CE); 289 assert(N.Val && "visit didn't populate the ValueMap!"); 290 return N; 291 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 292 return N = DAG.getGlobalAddress(GV, VT); 293 } else if (isa<ConstantPointerNull>(C)) { 294 return N = DAG.getConstant(0, TLI.getPointerTy()); 295 } else if (isa<UndefValue>(C)) { 296 return N = DAG.getNode(ISD::UNDEF, VT); 297 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 298 return N = DAG.getConstantFP(CFP->getValue(), VT); 299 } else { 300 // Canonicalize all constant ints to be unsigned. 301 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT); 302 } 303 304 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 305 std::map<const AllocaInst*, int>::iterator SI = 306 FuncInfo.StaticAllocaMap.find(AI); 307 if (SI != FuncInfo.StaticAllocaMap.end()) 308 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 309 } 310 311 std::map<const Value*, unsigned>::const_iterator VMI = 312 FuncInfo.ValueMap.find(V); 313 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 314 315 unsigned InReg = VMI->second; 316 317 // If this type is not legal, make it so now. 318 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 319 320 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 321 if (DestVT < VT) { 322 // Source must be expanded. This input value is actually coming from the 323 // register pair VMI->second and VMI->second+1. 324 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 325 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 326 } else { 327 if (DestVT > VT) { // Promotion case 328 if (MVT::isFloatingPoint(VT)) 329 N = DAG.getNode(ISD::FP_ROUND, VT, N); 330 else 331 N = DAG.getNode(ISD::TRUNCATE, VT, N); 332 } 333 } 334 335 return N; 336 } 337 338 const SDOperand &setValue(const Value *V, SDOperand NewN) { 339 SDOperand &N = NodeMap[V]; 340 assert(N.Val == 0 && "Already set a value for this node!"); 341 return N = NewN; 342 } 343 344 // Terminator instructions. 345 void visitRet(ReturnInst &I); 346 void visitBr(BranchInst &I); 347 void visitUnreachable(UnreachableInst &I) { /* noop */ } 348 349 // These all get lowered before this pass. 350 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); } 351 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 352 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 353 354 // 355 void visitBinary(User &I, unsigned Opcode, bool isShift = false); 356 void visitAdd(User &I) { 357 visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FADD : ISD::ADD); 358 } 359 void visitSub(User &I); 360 void visitMul(User &I) { 361 visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FMUL : ISD::MUL); 362 } 363 void visitDiv(User &I) { 364 unsigned Opc; 365 const Type *Ty = I.getType(); 366 if (Ty->isFloatingPoint()) 367 Opc = ISD::FDIV; 368 else if (Ty->isUnsigned()) 369 Opc = ISD::UDIV; 370 else 371 Opc = ISD::SDIV; 372 visitBinary(I, Opc); 373 } 374 void visitRem(User &I) { 375 unsigned Opc; 376 const Type *Ty = I.getType(); 377 if (Ty->isFloatingPoint()) 378 Opc = ISD::FREM; 379 else if (Ty->isUnsigned()) 380 Opc = ISD::UREM; 381 else 382 Opc = ISD::SREM; 383 visitBinary(I, Opc); 384 } 385 void visitAnd(User &I) { visitBinary(I, ISD::AND); } 386 void visitOr (User &I) { visitBinary(I, ISD::OR); } 387 void visitXor(User &I) { visitBinary(I, ISD::XOR); } 388 void visitShl(User &I) { visitBinary(I, ISD::SHL, true); } 389 void visitShr(User &I) { 390 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true); 391 } 392 393 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc); 394 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); } 395 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); } 396 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); } 397 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); } 398 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); } 399 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); } 400 401 void visitGetElementPtr(User &I); 402 void visitCast(User &I); 403 void visitSelect(User &I); 404 // 405 406 void visitMalloc(MallocInst &I); 407 void visitFree(FreeInst &I); 408 void visitAlloca(AllocaInst &I); 409 void visitLoad(LoadInst &I); 410 void visitStore(StoreInst &I); 411 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 412 void visitCall(CallInst &I); 413 414 void visitVAStart(CallInst &I); 415 void visitVAArg(VAArgInst &I); 416 void visitVAEnd(CallInst &I); 417 void visitVACopy(CallInst &I); 418 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 419 420 void visitMemIntrinsic(CallInst &I, unsigned Op); 421 422 void visitUserOp1(Instruction &I) { 423 assert(0 && "UserOp1 should not exist at instruction selection time!"); 424 abort(); 425 } 426 void visitUserOp2(Instruction &I) { 427 assert(0 && "UserOp2 should not exist at instruction selection time!"); 428 abort(); 429 } 430}; 431} // end namespace llvm 432 433void SelectionDAGLowering::visitRet(ReturnInst &I) { 434 if (I.getNumOperands() == 0) { 435 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 436 return; 437 } 438 439 SDOperand Op1 = getValue(I.getOperand(0)); 440 MVT::ValueType TmpVT; 441 442 switch (Op1.getValueType()) { 443 default: assert(0 && "Unknown value type!"); 444 case MVT::i1: 445 case MVT::i8: 446 case MVT::i16: 447 case MVT::i32: 448 // If this is a machine where 32-bits is legal or expanded, promote to 449 // 32-bits, otherwise, promote to 64-bits. 450 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 451 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 452 else 453 TmpVT = MVT::i32; 454 455 // Extend integer types to result type. 456 if (I.getOperand(0)->getType()->isSigned()) 457 Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1); 458 else 459 Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1); 460 break; 461 case MVT::f32: 462 case MVT::i64: 463 case MVT::f64: 464 break; // No extension needed! 465 } 466 467 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1)); 468} 469 470void SelectionDAGLowering::visitBr(BranchInst &I) { 471 // Update machine-CFG edges. 472 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 473 474 // Figure out which block is immediately after the current one. 475 MachineBasicBlock *NextBlock = 0; 476 MachineFunction::iterator BBI = CurMBB; 477 if (++BBI != CurMBB->getParent()->end()) 478 NextBlock = BBI; 479 480 if (I.isUnconditional()) { 481 // If this is not a fall-through branch, emit the branch. 482 if (Succ0MBB != NextBlock) 483 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 484 DAG.getBasicBlock(Succ0MBB))); 485 } else { 486 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 487 488 SDOperand Cond = getValue(I.getCondition()); 489 if (Succ1MBB == NextBlock) { 490 // If the condition is false, fall through. This means we should branch 491 // if the condition is true to Succ #0. 492 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 493 Cond, DAG.getBasicBlock(Succ0MBB))); 494 } else if (Succ0MBB == NextBlock) { 495 // If the condition is true, fall through. This means we should branch if 496 // the condition is false to Succ #1. Invert the condition first. 497 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 498 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 499 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), 500 Cond, DAG.getBasicBlock(Succ1MBB))); 501 } else { 502 std::vector<SDOperand> Ops; 503 Ops.push_back(getRoot()); 504 Ops.push_back(Cond); 505 Ops.push_back(DAG.getBasicBlock(Succ0MBB)); 506 Ops.push_back(DAG.getBasicBlock(Succ1MBB)); 507 DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops)); 508 } 509 } 510} 511 512void SelectionDAGLowering::visitSub(User &I) { 513 // -0.0 - X --> fneg 514 if (I.getType()->isFloatingPoint()) { 515 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 516 if (CFP->isExactlyValue(-0.0)) { 517 SDOperand Op2 = getValue(I.getOperand(1)); 518 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 519 return; 520 } 521 visitBinary(I, ISD::FSUB); 522 } else { 523 visitBinary(I, ISD::SUB); 524 } 525} 526 527void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) { 528 SDOperand Op1 = getValue(I.getOperand(0)); 529 SDOperand Op2 = getValue(I.getOperand(1)); 530 531 if (isShift) 532 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 533 534 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 535} 536 537void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 538 ISD::CondCode UnsignedOpcode) { 539 SDOperand Op1 = getValue(I.getOperand(0)); 540 SDOperand Op2 = getValue(I.getOperand(1)); 541 ISD::CondCode Opcode = SignedOpcode; 542 if (I.getOperand(0)->getType()->isUnsigned()) 543 Opcode = UnsignedOpcode; 544 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 545} 546 547void SelectionDAGLowering::visitSelect(User &I) { 548 SDOperand Cond = getValue(I.getOperand(0)); 549 SDOperand TrueVal = getValue(I.getOperand(1)); 550 SDOperand FalseVal = getValue(I.getOperand(2)); 551 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 552 TrueVal, FalseVal)); 553} 554 555void SelectionDAGLowering::visitCast(User &I) { 556 SDOperand N = getValue(I.getOperand(0)); 557 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType()); 558 MVT::ValueType DestTy = TLI.getValueType(I.getType()); 559 560 if (N.getValueType() == DestTy) { 561 setValue(&I, N); // noop cast. 562 } else if (DestTy == MVT::i1) { 563 // Cast to bool is a comparison against zero, not truncation to zero. 564 SDOperand Zero = isInteger(SrcTy) ? DAG.getConstant(0, N.getValueType()) : 565 DAG.getConstantFP(0.0, N.getValueType()); 566 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE)); 567 } else if (isInteger(SrcTy)) { 568 if (isInteger(DestTy)) { // Int -> Int cast 569 if (DestTy < SrcTy) // Truncating cast? 570 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N)); 571 else if (I.getOperand(0)->getType()->isSigned()) 572 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N)); 573 else 574 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N)); 575 } else { // Int -> FP cast 576 if (I.getOperand(0)->getType()->isSigned()) 577 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N)); 578 else 579 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N)); 580 } 581 } else { 582 assert(isFloatingPoint(SrcTy) && "Unknown value type!"); 583 if (isFloatingPoint(DestTy)) { // FP -> FP cast 584 if (DestTy < SrcTy) // Rounding cast? 585 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N)); 586 else 587 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N)); 588 } else { // FP -> Int cast. 589 if (I.getType()->isSigned()) 590 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N)); 591 else 592 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N)); 593 } 594 } 595} 596 597void SelectionDAGLowering::visitGetElementPtr(User &I) { 598 SDOperand N = getValue(I.getOperand(0)); 599 const Type *Ty = I.getOperand(0)->getType(); 600 const Type *UIntPtrTy = TD.getIntPtrType(); 601 602 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 603 OI != E; ++OI) { 604 Value *Idx = *OI; 605 if (const StructType *StTy = dyn_cast<StructType> (Ty)) { 606 unsigned Field = cast<ConstantUInt>(Idx)->getValue(); 607 if (Field) { 608 // N = N + Offset 609 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field]; 610 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 611 getIntPtrConstant(Offset)); 612 } 613 Ty = StTy->getElementType(Field); 614 } else { 615 Ty = cast<SequentialType>(Ty)->getElementType(); 616 if (!isa<Constant>(Idx) || !cast<Constant>(Idx)->isNullValue()) { 617 // N = N + Idx * ElementSize; 618 uint64_t ElementSize = TD.getTypeSize(Ty); 619 SDOperand IdxN = getValue(Idx), Scale = getIntPtrConstant(ElementSize); 620 621 // If the index is smaller or larger than intptr_t, truncate or extend 622 // it. 623 if (IdxN.getValueType() < Scale.getValueType()) { 624 if (Idx->getType()->isSigned()) 625 IdxN = DAG.getNode(ISD::SIGN_EXTEND, Scale.getValueType(), IdxN); 626 else 627 IdxN = DAG.getNode(ISD::ZERO_EXTEND, Scale.getValueType(), IdxN); 628 } else if (IdxN.getValueType() > Scale.getValueType()) 629 IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN); 630 631 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 632 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 633 } 634 } 635 } 636 setValue(&I, N); 637} 638 639void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 640 // If this is a fixed sized alloca in the entry block of the function, 641 // allocate it statically on the stack. 642 if (FuncInfo.StaticAllocaMap.count(&I)) 643 return; // getValue will auto-populate this. 644 645 const Type *Ty = I.getAllocatedType(); 646 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); 647 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 648 649 SDOperand AllocSize = getValue(I.getArraySize()); 650 MVT::ValueType IntPtr = TLI.getPointerTy(); 651 if (IntPtr < AllocSize.getValueType()) 652 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 653 else if (IntPtr > AllocSize.getValueType()) 654 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 655 656 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 657 getIntPtrConstant(TySize)); 658 659 // Handle alignment. If the requested alignment is less than or equal to the 660 // stack alignment, ignore it and round the size of the allocation up to the 661 // stack alignment size. If the size is greater than the stack alignment, we 662 // note this in the DYNAMIC_STACKALLOC node. 663 unsigned StackAlign = 664 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 665 if (Align <= StackAlign) { 666 Align = 0; 667 // Add SA-1 to the size. 668 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 669 getIntPtrConstant(StackAlign-1)); 670 // Mask out the low bits for alignment purposes. 671 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 672 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 673 } 674 675 std::vector<MVT::ValueType> VTs; 676 VTs.push_back(AllocSize.getValueType()); 677 VTs.push_back(MVT::Other); 678 std::vector<SDOperand> Ops; 679 Ops.push_back(getRoot()); 680 Ops.push_back(AllocSize); 681 Ops.push_back(getIntPtrConstant(Align)); 682 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 683 DAG.setRoot(setValue(&I, DSA).getValue(1)); 684 685 // Inform the Frame Information that we have just allocated a variable-sized 686 // object. 687 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 688} 689 690 691void SelectionDAGLowering::visitLoad(LoadInst &I) { 692 SDOperand Ptr = getValue(I.getOperand(0)); 693 694 SDOperand Root; 695 if (I.isVolatile()) 696 Root = getRoot(); 697 else { 698 // Do not serialize non-volatile loads against each other. 699 Root = DAG.getRoot(); 700 } 701 702 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr, 703 DAG.getSrcValue(I.getOperand(0))); 704 setValue(&I, L); 705 706 if (I.isVolatile()) 707 DAG.setRoot(L.getValue(1)); 708 else 709 PendingLoads.push_back(L.getValue(1)); 710} 711 712 713void SelectionDAGLowering::visitStore(StoreInst &I) { 714 Value *SrcV = I.getOperand(0); 715 SDOperand Src = getValue(SrcV); 716 SDOperand Ptr = getValue(I.getOperand(1)); 717 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr, 718 DAG.getSrcValue(I.getOperand(1)))); 719} 720 721void SelectionDAGLowering::visitCall(CallInst &I) { 722 const char *RenameFn = 0; 723 SDOperand Tmp; 724 if (Function *F = I.getCalledFunction()) 725 if (F->isExternal()) 726 switch (F->getIntrinsicID()) { 727 case 0: // Not an LLVM intrinsic. 728 if (F->getName() == "fabs" || F->getName() == "fabsf") { 729 if (I.getNumOperands() == 2 && // Basic sanity checks. 730 I.getOperand(1)->getType()->isFloatingPoint() && 731 I.getType() == I.getOperand(1)->getType()) { 732 Tmp = getValue(I.getOperand(1)); 733 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 734 return; 735 } 736 } 737 else if (F->getName() == "sin" || F->getName() == "sinf") { 738 if (I.getNumOperands() == 2 && // Basic sanity checks. 739 I.getOperand(1)->getType()->isFloatingPoint() && 740 I.getType() == I.getOperand(1)->getType()) { 741 Tmp = getValue(I.getOperand(1)); 742 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 743 return; 744 } 745 } 746 else if (F->getName() == "cos" || F->getName() == "cosf") { 747 if (I.getNumOperands() == 2 && // Basic sanity checks. 748 I.getOperand(1)->getType()->isFloatingPoint() && 749 I.getType() == I.getOperand(1)->getType()) { 750 Tmp = getValue(I.getOperand(1)); 751 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 752 return; 753 } 754 } 755 break; 756 case Intrinsic::vastart: visitVAStart(I); return; 757 case Intrinsic::vaend: visitVAEnd(I); return; 758 case Intrinsic::vacopy: visitVACopy(I); return; 759 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return; 760 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return; 761 762 case Intrinsic::setjmp: 763 RenameFn = "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 764 break; 765 case Intrinsic::longjmp: 766 RenameFn = "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp(); 767 break; 768 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return; 769 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return; 770 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return; 771 772 case Intrinsic::readport: 773 case Intrinsic::readio: { 774 std::vector<MVT::ValueType> VTs; 775 VTs.push_back(TLI.getValueType(I.getType())); 776 VTs.push_back(MVT::Other); 777 std::vector<SDOperand> Ops; 778 Ops.push_back(getRoot()); 779 Ops.push_back(getValue(I.getOperand(1))); 780 Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ? 781 ISD::READPORT : ISD::READIO, VTs, Ops); 782 783 setValue(&I, Tmp); 784 DAG.setRoot(Tmp.getValue(1)); 785 return; 786 } 787 case Intrinsic::writeport: 788 case Intrinsic::writeio: 789 DAG.setRoot(DAG.getNode(F->getIntrinsicID() == Intrinsic::writeport ? 790 ISD::WRITEPORT : ISD::WRITEIO, MVT::Other, 791 getRoot(), getValue(I.getOperand(1)), 792 getValue(I.getOperand(2)))); 793 return; 794 case Intrinsic::dbg_stoppoint: 795 case Intrinsic::dbg_region_start: 796 case Intrinsic::dbg_region_end: 797 case Intrinsic::dbg_func_start: 798 case Intrinsic::dbg_declare: 799 if (I.getType() != Type::VoidTy) 800 setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()))); 801 return; 802 803 case Intrinsic::isunordered: 804 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), 805 getValue(I.getOperand(2)), ISD::SETUO)); 806 return; 807 808 case Intrinsic::sqrt: 809 setValue(&I, DAG.getNode(ISD::FSQRT, 810 getValue(I.getOperand(1)).getValueType(), 811 getValue(I.getOperand(1)))); 812 return; 813 814 case Intrinsic::pcmarker: 815 Tmp = getValue(I.getOperand(1)); 816 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 817 return; 818 case Intrinsic::cttz: 819 setValue(&I, DAG.getNode(ISD::CTTZ, 820 getValue(I.getOperand(1)).getValueType(), 821 getValue(I.getOperand(1)))); 822 return; 823 case Intrinsic::ctlz: 824 setValue(&I, DAG.getNode(ISD::CTLZ, 825 getValue(I.getOperand(1)).getValueType(), 826 getValue(I.getOperand(1)))); 827 return; 828 case Intrinsic::ctpop: 829 setValue(&I, DAG.getNode(ISD::CTPOP, 830 getValue(I.getOperand(1)).getValueType(), 831 getValue(I.getOperand(1)))); 832 return; 833 default: 834 std::cerr << I; 835 assert(0 && "This intrinsic is not implemented yet!"); 836 return; 837 } 838 839 SDOperand Callee; 840 if (!RenameFn) 841 Callee = getValue(I.getOperand(0)); 842 else 843 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 844 std::vector<std::pair<SDOperand, const Type*> > Args; 845 846 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 847 Value *Arg = I.getOperand(i); 848 SDOperand ArgNode = getValue(Arg); 849 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 850 } 851 852 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 853 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 854 855 std::pair<SDOperand,SDOperand> Result = 856 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(), 857 I.isTailCall(), Callee, Args, DAG); 858 if (I.getType() != Type::VoidTy) 859 setValue(&I, Result.first); 860 DAG.setRoot(Result.second); 861} 862 863void SelectionDAGLowering::visitMalloc(MallocInst &I) { 864 SDOperand Src = getValue(I.getOperand(0)); 865 866 MVT::ValueType IntPtr = TLI.getPointerTy(); 867 868 if (IntPtr < Src.getValueType()) 869 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 870 else if (IntPtr > Src.getValueType()) 871 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 872 873 // Scale the source by the type size. 874 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType()); 875 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 876 Src, getIntPtrConstant(ElementSize)); 877 878 std::vector<std::pair<SDOperand, const Type*> > Args; 879 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType())); 880 881 std::pair<SDOperand,SDOperand> Result = 882 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, 883 DAG.getExternalSymbol("malloc", IntPtr), 884 Args, DAG); 885 setValue(&I, Result.first); // Pointers always fit in registers 886 DAG.setRoot(Result.second); 887} 888 889void SelectionDAGLowering::visitFree(FreeInst &I) { 890 std::vector<std::pair<SDOperand, const Type*> > Args; 891 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 892 TLI.getTargetData().getIntPtrType())); 893 MVT::ValueType IntPtr = TLI.getPointerTy(); 894 std::pair<SDOperand,SDOperand> Result = 895 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, 896 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 897 DAG.setRoot(Result.second); 898} 899 900// InsertAtEndOfBasicBlock - This method should be implemented by targets that 901// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 902// instructions are special in various ways, which require special support to 903// insert. The specified MachineInstr is created but not inserted into any 904// basic blocks, and the scheduler passes ownership of it to this method. 905MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 906 MachineBasicBlock *MBB) { 907 std::cerr << "If a target marks an instruction with " 908 "'usesCustomDAGSchedInserter', it must implement " 909 "TargetLowering::InsertAtEndOfBasicBlock!\n"; 910 abort(); 911 return 0; 912} 913 914SDOperand TargetLowering::LowerVAStart(SDOperand Chain, 915 SDOperand VAListP, Value *VAListV, 916 SelectionDAG &DAG) { 917 // We have no sane default behavior, just emit a useful error message and bail 918 // out. 919 std::cerr << "Variable arguments handling not implemented on this target!\n"; 920 abort(); 921 return SDOperand(); 922} 923 924SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand LP, Value *LV, 925 SelectionDAG &DAG) { 926 // Default to a noop. 927 return Chain; 928} 929 930SDOperand TargetLowering::LowerVACopy(SDOperand Chain, 931 SDOperand SrcP, Value *SrcV, 932 SDOperand DestP, Value *DestV, 933 SelectionDAG &DAG) { 934 // Default to copying the input list. 935 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, 936 SrcP, DAG.getSrcValue(SrcV)); 937 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 938 Val, DestP, DAG.getSrcValue(DestV)); 939 return Result; 940} 941 942std::pair<SDOperand,SDOperand> 943TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 944 const Type *ArgTy, SelectionDAG &DAG) { 945 // We have no sane default behavior, just emit a useful error message and bail 946 // out. 947 std::cerr << "Variable arguments handling not implemented on this target!\n"; 948 abort(); 949 return std::make_pair(SDOperand(), SDOperand()); 950} 951 952 953void SelectionDAGLowering::visitVAStart(CallInst &I) { 954 DAG.setRoot(TLI.LowerVAStart(getRoot(), getValue(I.getOperand(1)), 955 I.getOperand(1), DAG)); 956} 957 958void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 959 std::pair<SDOperand,SDOperand> Result = 960 TLI.LowerVAArg(getRoot(), getValue(I.getOperand(0)), I.getOperand(0), 961 I.getType(), DAG); 962 setValue(&I, Result.first); 963 DAG.setRoot(Result.second); 964} 965 966void SelectionDAGLowering::visitVAEnd(CallInst &I) { 967 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), 968 I.getOperand(1), DAG)); 969} 970 971void SelectionDAGLowering::visitVACopy(CallInst &I) { 972 SDOperand Result = 973 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(2)), I.getOperand(2), 974 getValue(I.getOperand(1)), I.getOperand(1), DAG); 975 DAG.setRoot(Result); 976} 977 978 979// It is always conservatively correct for llvm.returnaddress and 980// llvm.frameaddress to return 0. 981std::pair<SDOperand, SDOperand> 982TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 983 unsigned Depth, SelectionDAG &DAG) { 984 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 985} 986 987SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 988 assert(0 && "LowerOperation not implemented for this target!"); 989 abort(); 990 return SDOperand(); 991} 992 993void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 994 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue(); 995 std::pair<SDOperand,SDOperand> Result = 996 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 997 setValue(&I, Result.first); 998 DAG.setRoot(Result.second); 999} 1000 1001void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 1002 std::vector<SDOperand> Ops; 1003 Ops.push_back(getRoot()); 1004 Ops.push_back(getValue(I.getOperand(1))); 1005 Ops.push_back(getValue(I.getOperand(2))); 1006 Ops.push_back(getValue(I.getOperand(3))); 1007 Ops.push_back(getValue(I.getOperand(4))); 1008 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops)); 1009} 1010 1011//===----------------------------------------------------------------------===// 1012// SelectionDAGISel code 1013//===----------------------------------------------------------------------===// 1014 1015unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 1016 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 1017} 1018 1019void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 1020 // FIXME: we only modify the CFG to split critical edges. This 1021 // updates dom and loop info. 1022} 1023 1024 1025bool SelectionDAGISel::runOnFunction(Function &Fn) { 1026 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 1027 RegMap = MF.getSSARegMap(); 1028 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n"); 1029 1030 // First pass, split all critical edges for PHI nodes with incoming values 1031 // that are constants, this way the load of the constant into a vreg will not 1032 // be placed into MBBs that are used some other way. 1033 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 1034 PHINode *PN; 1035 for (BasicBlock::iterator BBI = BB->begin(); 1036 (PN = dyn_cast<PHINode>(BBI)); ++BBI) 1037 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) 1038 if (isa<Constant>(PN->getIncomingValue(i))) 1039 SplitCriticalEdge(PN->getIncomingBlock(i), BB); 1040 } 1041 1042 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 1043 1044 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 1045 SelectBasicBlock(I, MF, FuncInfo); 1046 1047 return true; 1048} 1049 1050 1051SDOperand SelectionDAGISel:: 1052CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { 1053 SDOperand Op = SDL.getValue(V); 1054 assert((Op.getOpcode() != ISD::CopyFromReg || 1055 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 1056 "Copy from a reg to the same reg!"); 1057 1058 // If this type is not legal, we must make sure to not create an invalid 1059 // register use. 1060 MVT::ValueType SrcVT = Op.getValueType(); 1061 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 1062 SelectionDAG &DAG = SDL.DAG; 1063 if (SrcVT == DestVT) { 1064 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 1065 } else if (SrcVT < DestVT) { 1066 // The src value is promoted to the register. 1067 if (MVT::isFloatingPoint(SrcVT)) 1068 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 1069 else 1070 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 1071 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); 1072 } else { 1073 // The src value is expanded into multiple registers. 1074 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 1075 Op, DAG.getConstant(0, MVT::i32)); 1076 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 1077 Op, DAG.getConstant(1, MVT::i32)); 1078 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo); 1079 return DAG.getCopyToReg(Op, Reg+1, Hi); 1080 } 1081} 1082 1083/// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a 1084/// single basic block, return that block. Otherwise, return a null pointer. 1085static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) { 1086 if (A->use_empty()) return 0; 1087 BasicBlock *BB = cast<Instruction>(A->use_back())->getParent(); 1088 for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; 1089 ++UI) 1090 if (isa<PHINode>(*UI) || cast<Instruction>(*UI)->getParent() != BB) 1091 return 0; // Disagreement among the users? 1092 1093 // Okay, there is a single BB user. Only permit this optimization if this is 1094 // the entry block, otherwise, we might sink argument loads into loops and 1095 // stuff. Later, when we have global instruction selection, this won't be an 1096 // issue clearly. 1097 if (BB == BB->getParent()->begin()) 1098 return BB; 1099 return 0; 1100} 1101 1102void SelectionDAGISel:: 1103LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 1104 std::vector<SDOperand> &UnorderedChains) { 1105 // If this is the entry block, emit arguments. 1106 Function &F = *BB->getParent(); 1107 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 1108 1109 if (BB == &F.front()) { 1110 SDOperand OldRoot = SDL.DAG.getRoot(); 1111 1112 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 1113 1114 // If there were side effects accessing the argument list, do not do 1115 // anything special. 1116 if (OldRoot != SDL.DAG.getRoot()) { 1117 unsigned a = 0; 1118 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 1119 AI != E; ++AI,++a) 1120 if (!AI->use_empty()) { 1121 SDL.setValue(AI, Args[a]); 1122 1123 SDOperand Copy = 1124 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 1125 UnorderedChains.push_back(Copy); 1126 } 1127 } else { 1128 // Otherwise, if any argument is only accessed in a single basic block, 1129 // emit that argument only to that basic block. 1130 unsigned a = 0; 1131 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 1132 AI != E; ++AI,++a) 1133 if (!AI->use_empty()) { 1134 if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) { 1135 FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU, 1136 std::make_pair(AI, a))); 1137 } else { 1138 SDL.setValue(AI, Args[a]); 1139 SDOperand Copy = 1140 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]); 1141 UnorderedChains.push_back(Copy); 1142 } 1143 } 1144 } 1145 1146 // Next, if the function has live ins that need to be copied into vregs, 1147 // emit the copies now, into the top of the block. 1148 MachineFunction &MF = SDL.DAG.getMachineFunction(); 1149 if (MF.livein_begin() != MF.livein_end()) { 1150 SSARegMap *RegMap = MF.getSSARegMap(); 1151 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 1152 for (MachineFunction::livein_iterator LI = MF.livein_begin(), 1153 E = MF.livein_end(); LI != E; ++LI) 1154 if (LI->second) 1155 MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, 1156 LI->first, RegMap->getRegClass(LI->second)); 1157 } 1158 1159 // Finally, if the target has anything special to do, allow it to do so. 1160 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 1161 } 1162 1163 // See if there are any block-local arguments that need to be emitted in this 1164 // block. 1165 1166 if (!FuncInfo.BlockLocalArguments.empty()) { 1167 std::multimap<BasicBlock*, std::pair<Argument*, unsigned> >::iterator BLAI = 1168 FuncInfo.BlockLocalArguments.lower_bound(BB); 1169 if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) { 1170 // Lower the arguments into this block. 1171 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 1172 1173 // Set up the value mapping for the local arguments. 1174 for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB; 1175 ++BLAI) 1176 SDL.setValue(BLAI->second.first, Args[BLAI->second.second]); 1177 1178 // Any dead arguments will just be ignored here. 1179 } 1180 } 1181} 1182 1183 1184void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 1185 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 1186 FunctionLoweringInfo &FuncInfo) { 1187 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 1188 1189 std::vector<SDOperand> UnorderedChains; 1190 1191 // Lower any arguments needed in this block. 1192 LowerArguments(LLVMBB, SDL, UnorderedChains); 1193 1194 BB = FuncInfo.MBBMap[LLVMBB]; 1195 SDL.setCurrentBasicBlock(BB); 1196 1197 // Lower all of the non-terminator instructions. 1198 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 1199 I != E; ++I) 1200 SDL.visit(*I); 1201 1202 // Ensure that all instructions which are used outside of their defining 1203 // blocks are available as virtual registers. 1204 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 1205 if (!I->use_empty() && !isa<PHINode>(I)) { 1206 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 1207 if (VMI != FuncInfo.ValueMap.end()) 1208 UnorderedChains.push_back( 1209 CopyValueToVirtualRegister(SDL, I, VMI->second)); 1210 } 1211 1212 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 1213 // ensure constants are generated when needed. Remember the virtual registers 1214 // that need to be added to the Machine PHI nodes as input. We cannot just 1215 // directly add them, because expansion might result in multiple MBB's for one 1216 // BB. As such, the start of the BB might correspond to a different MBB than 1217 // the end. 1218 // 1219 1220 // Emit constants only once even if used by multiple PHI nodes. 1221 std::map<Constant*, unsigned> ConstantsOut; 1222 1223 // Check successor nodes PHI nodes that expect a constant to be available from 1224 // this block. 1225 TerminatorInst *TI = LLVMBB->getTerminator(); 1226 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1227 BasicBlock *SuccBB = TI->getSuccessor(succ); 1228 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin(); 1229 PHINode *PN; 1230 1231 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1232 // nodes and Machine PHI nodes, but the incoming operands have not been 1233 // emitted yet. 1234 for (BasicBlock::iterator I = SuccBB->begin(); 1235 (PN = dyn_cast<PHINode>(I)); ++I) 1236 if (!PN->use_empty()) { 1237 unsigned Reg; 1238 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1239 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 1240 unsigned &RegOut = ConstantsOut[C]; 1241 if (RegOut == 0) { 1242 RegOut = FuncInfo.CreateRegForValue(C); 1243 UnorderedChains.push_back( 1244 CopyValueToVirtualRegister(SDL, C, RegOut)); 1245 } 1246 Reg = RegOut; 1247 } else { 1248 Reg = FuncInfo.ValueMap[PHIOp]; 1249 if (Reg == 0) { 1250 assert(isa<AllocaInst>(PHIOp) && 1251 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 1252 "Didn't codegen value into a register!??"); 1253 Reg = FuncInfo.CreateRegForValue(PHIOp); 1254 UnorderedChains.push_back( 1255 CopyValueToVirtualRegister(SDL, PHIOp, Reg)); 1256 } 1257 } 1258 1259 // Remember that this register needs to added to the machine PHI node as 1260 // the input for this MBB. 1261 unsigned NumElements = 1262 TLI.getNumElements(TLI.getValueType(PN->getType())); 1263 for (unsigned i = 0, e = NumElements; i != e; ++i) 1264 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 1265 } 1266 } 1267 ConstantsOut.clear(); 1268 1269 // Turn all of the unordered chains into one factored node. 1270 if (!UnorderedChains.empty()) { 1271 UnorderedChains.push_back(SDL.getRoot()); 1272 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains)); 1273 } 1274 1275 // Lower the terminator after the copies are emitted. 1276 SDL.visit(*LLVMBB->getTerminator()); 1277 1278 // Make sure the root of the DAG is up-to-date. 1279 DAG.setRoot(SDL.getRoot()); 1280} 1281 1282void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 1283 FunctionLoweringInfo &FuncInfo) { 1284 SelectionDAG DAG(TLI, MF); 1285 CurDAG = &DAG; 1286 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 1287 1288 // First step, lower LLVM code to some DAG. This DAG may use operations and 1289 // types that are not supported by the target. 1290 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 1291 1292 // Run the DAG combiner in pre-legalize mode, if we are told to do so 1293 if (CombinerEnabled) DAG.Combine(false); 1294 1295 DEBUG(std::cerr << "Lowered selection DAG:\n"); 1296 DEBUG(DAG.dump()); 1297 1298 // Second step, hack on the DAG until it only uses operations and types that 1299 // the target supports. 1300 DAG.Legalize(); 1301 1302 DEBUG(std::cerr << "Legalized selection DAG:\n"); 1303 DEBUG(DAG.dump()); 1304 1305 if (ViewDAGs) DAG.viewGraph(); 1306 1307 // Run the DAG combiner in post-legalize mode, if we are told to do so 1308 if (CombinerEnabled) DAG.Combine(true); 1309 1310 // Third, instruction select all of the operations to machine code, adding the 1311 // code to the MachineBasicBlock. 1312 InstructionSelectBasicBlock(DAG); 1313 1314 DEBUG(std::cerr << "Selected machine code:\n"); 1315 DEBUG(BB->dump()); 1316 1317 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1318 // PHI nodes in successors. 1319 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 1320 MachineInstr *PHI = PHINodesToUpdate[i].first; 1321 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 1322 "This is not a machine PHI node that we are updating!"); 1323 PHI->addRegOperand(PHINodesToUpdate[i].second); 1324 PHI->addMachineBasicBlockOperand(BB); 1325 } 1326 1327 // Finally, add the CFG edges from the last selected MBB to the successor 1328 // MBBs. 1329 TerminatorInst *TI = LLVMBB->getTerminator(); 1330 for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) { 1331 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)]; 1332 BB->addSuccessor(Succ0MBB); 1333 } 1334} 1335