SelectionDAGISel.cpp revision 9bbcd5ee5b9a34f82d7d0570256ff4b4f53fabe9
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/CodeGen/SelectionDAGISel.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/FastISel.h" 32#include "llvm/CodeGen/GCStrategy.h" 33#include "llvm/CodeGen/GCMetadata.h" 34#include "llvm/CodeGen/MachineFunction.h" 35#include "llvm/CodeGen/MachineFunctionAnalysis.h" 36#include "llvm/CodeGen/MachineFrameInfo.h" 37#include "llvm/CodeGen/MachineInstrBuilder.h" 38#include "llvm/CodeGen/MachineJumpTableInfo.h" 39#include "llvm/CodeGen/MachineModuleInfo.h" 40#include "llvm/CodeGen/MachineRegisterInfo.h" 41#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 42#include "llvm/CodeGen/SchedulerRegistry.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/CodeGen/DwarfWriter.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameInfo.h" 48#include "llvm/Target/TargetIntrinsicInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetLowering.h" 51#include "llvm/Target/TargetMachine.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/Timer.h" 58#include "llvm/Support/raw_ostream.h" 59#include "llvm/ADT/Statistic.h" 60#include <algorithm> 61using namespace llvm; 62 63STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 64 65static cl::opt<bool> 66EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 67 cl::desc("Enable verbose messages in the \"fast\" " 68 "instruction selector")); 69static cl::opt<bool> 70EnableFastISelAbort("fast-isel-abort", cl::Hidden, 71 cl::desc("Enable abort calls when \"fast\" instruction fails")); 72static cl::opt<bool> 73SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 74 cl::desc("Schedule copies of livein registers"), 75 cl::init(false)); 76 77#ifndef NDEBUG 78static cl::opt<bool> 79ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 80 cl::desc("Pop up a window to show dags before the first " 81 "dag combine pass")); 82static cl::opt<bool> 83ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 84 cl::desc("Pop up a window to show dags before legalize types")); 85static cl::opt<bool> 86ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 87 cl::desc("Pop up a window to show dags before legalize")); 88static cl::opt<bool> 89ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 90 cl::desc("Pop up a window to show dags before the second " 91 "dag combine pass")); 92static cl::opt<bool> 93ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 94 cl::desc("Pop up a window to show dags before the post legalize types" 95 " dag combine pass")); 96static cl::opt<bool> 97ViewISelDAGs("view-isel-dags", cl::Hidden, 98 cl::desc("Pop up a window to show isel dags as they are selected")); 99static cl::opt<bool> 100ViewSchedDAGs("view-sched-dags", cl::Hidden, 101 cl::desc("Pop up a window to show sched dags as they are processed")); 102static cl::opt<bool> 103ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 104 cl::desc("Pop up a window to show SUnit dags after they are processed")); 105#else 106static const bool ViewDAGCombine1 = false, 107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 108 ViewDAGCombine2 = false, 109 ViewDAGCombineLT = false, 110 ViewISelDAGs = false, ViewSchedDAGs = false, 111 ViewSUnitDAGs = false; 112#endif 113 114//===---------------------------------------------------------------------===// 115/// 116/// RegisterScheduler class - Track the registration of instruction schedulers. 117/// 118//===---------------------------------------------------------------------===// 119MachinePassRegistry RegisterScheduler::Registry; 120 121//===---------------------------------------------------------------------===// 122/// 123/// ISHeuristic command line option for instruction schedulers. 124/// 125//===---------------------------------------------------------------------===// 126static cl::opt<RegisterScheduler::FunctionPassCtor, false, 127 RegisterPassParser<RegisterScheduler> > 128ISHeuristic("pre-RA-sched", 129 cl::init(&createDefaultScheduler), 130 cl::desc("Instruction schedulers available (before register" 131 " allocation):")); 132 133static RegisterScheduler 134defaultListDAGScheduler("default", "Best scheduler for the target", 135 createDefaultScheduler); 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 142 CodeGenOpt::Level OptLevel) { 143 const TargetLowering &TLI = IS->getTargetLowering(); 144 145 if (OptLevel == CodeGenOpt::None) 146 return createFastDAGScheduler(IS, OptLevel); 147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) 148 return createTDListDAGScheduler(IS, OptLevel); 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, OptLevel); 152 } 153} 154 155// EmitInstrWithCustomInserter - This method should be implemented by targets 156// that mark instructions with the 'usesCustomInserter' flag. These 157// instructions are special in various ways, which require special support to 158// insert. The specified MachineInstr is created but not inserted into any 159// basic blocks, and this method is called to expand it into a sequence of 160// instructions, potentially also creating new basic blocks and control flow. 161// When new basic blocks are inserted and the edges from MBB to its successors 162// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 163// DenseMap. 164MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 165 MachineBasicBlock *MBB, 166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 167#ifndef NDEBUG 168 dbgs() << "If a target marks an instruction with " 169 "'usesCustomInserter', it must implement " 170 "TargetLowering::EmitInstrWithCustomInserter!"; 171#endif 172 llvm_unreachable(0); 173 return 0; 174} 175 176/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 177/// physical register has only a single copy use, then coalesced the copy 178/// if possible. 179static void EmitLiveInCopy(MachineBasicBlock *MBB, 180 MachineBasicBlock::iterator &InsertPos, 181 unsigned VirtReg, unsigned PhysReg, 182 const TargetRegisterClass *RC, 183 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 184 const MachineRegisterInfo &MRI, 185 const TargetRegisterInfo &TRI, 186 const TargetInstrInfo &TII) { 187 unsigned NumUses = 0; 188 MachineInstr *UseMI = NULL; 189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 190 UE = MRI.use_end(); UI != UE; ++UI) { 191 UseMI = &*UI; 192 if (++NumUses > 1) 193 break; 194 } 195 196 // If the number of uses is not one, or the use is not a move instruction, 197 // don't coalesce. Also, only coalesce away a virtual register to virtual 198 // register copy. 199 bool Coalesced = false; 200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 201 if (NumUses == 1 && 202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 203 TargetRegisterInfo::isVirtualRegister(DstReg)) { 204 VirtReg = DstReg; 205 Coalesced = true; 206 } 207 208 // Now find an ideal location to insert the copy. 209 MachineBasicBlock::iterator Pos = InsertPos; 210 while (Pos != MBB->begin()) { 211 MachineInstr *PrevMI = prior(Pos); 212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 213 // copyRegToReg might emit multiple instructions to do a copy. 214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 216 // This is what the BB looks like right now: 217 // r1024 = mov r0 218 // ... 219 // r1 = mov r1024 220 // 221 // We want to insert "r1025 = mov r1". Inserting this copy below the 222 // move to r1024 makes it impossible for that move to be coalesced. 223 // 224 // r1025 = mov r1 225 // r1024 = mov r0 226 // ... 227 // r1 = mov 1024 228 // r2 = mov 1025 229 break; // Woot! Found a good location. 230 --Pos; 231 } 232 233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 234 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 235 (void) Emitted; 236 237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 238 if (Coalesced) { 239 if (&*InsertPos == UseMI) ++InsertPos; 240 MBB->erase(UseMI); 241 } 242} 243 244/// EmitLiveInCopies - If this is the first basic block in the function, 245/// and if it has live ins that need to be copied into vregs, emit the 246/// copies into the block. 247static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 248 const MachineRegisterInfo &MRI, 249 const TargetRegisterInfo &TRI, 250 const TargetInstrInfo &TII) { 251 if (SchedLiveInCopies) { 252 // Emit the copies at a heuristically-determined location in the block. 253 DenseMap<MachineInstr*, unsigned> CopyRegMap; 254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 256 E = MRI.livein_end(); LI != E; ++LI) 257 if (LI->second) { 258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 260 RC, CopyRegMap, MRI, TRI, TII); 261 } 262 } else { 263 // Emit the copies into the top of the block. 264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(), 265 E = MRI.livein_end(); LI != E; ++LI) 266 if (LI->second) { 267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second); 268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 269 LI->second, LI->first, RC, RC); 270 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 271 (void) Emitted; 272 } 273 } 274} 275 276//===----------------------------------------------------------------------===// 277// SelectionDAGISel code 278//===----------------------------------------------------------------------===// 279 280SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) : 281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), 282 FuncInfo(new FunctionLoweringInfo(TLI)), 283 CurDAG(new SelectionDAG(TLI, *FuncInfo)), 284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)), 285 GFI(), 286 OptLevel(OL), 287 DAGSize(0) 288{} 289 290SelectionDAGISel::~SelectionDAGISel() { 291 delete SDB; 292 delete CurDAG; 293 delete FuncInfo; 294} 295 296unsigned SelectionDAGISel::MakeReg(EVT VT) { 297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 298} 299 300void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 301 AU.addRequired<AliasAnalysis>(); 302 AU.addPreserved<AliasAnalysis>(); 303 AU.addRequired<GCModuleInfo>(); 304 AU.addPreserved<GCModuleInfo>(); 305 AU.addRequired<DwarfWriter>(); 306 AU.addPreserved<DwarfWriter>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 311 Function &Fn = *mf.getFunction(); 312 313 // Do some sanity-checking on the command-line options. 314 assert((!EnableFastISelVerbose || EnableFastISel) && 315 "-fast-isel-verbose requires -fast-isel"); 316 assert((!EnableFastISelAbort || EnableFastISel) && 317 "-fast-isel-abort requires -fast-isel"); 318 319 // Get alias analysis for load/store combining. 320 AA = &getAnalysis<AliasAnalysis>(); 321 322 MF = &mf; 323 const TargetInstrInfo &TII = *TM.getInstrInfo(); 324 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 325 326 if (Fn.hasGC()) 327 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn); 328 else 329 GFI = 0; 330 RegInfo = &MF->getRegInfo(); 331 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 332 333 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); 334 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); 335 CurDAG->init(*MF, MMI, DW); 336 FuncInfo->set(Fn, *MF, EnableFastISel); 337 SDB->init(GFI, *AA); 338 339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator())) 341 // Mark landing pad. 342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); 343 344 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII); 345 346 // If the first basic block in the function has live ins that need to be 347 // copied into vregs, emit the copies into the top of the block before 348 // emitting the code for the block. 349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII); 350 351 // Add function live-ins to entry block live-in set. 352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), 353 E = RegInfo->livein_end(); I != E; ++I) 354 MF->begin()->addLiveIn(I->first); 355 356#ifndef NDEBUG 357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() && 358 "Not all catch info was assigned to a landing pad!"); 359#endif 360 361 FuncInfo->clear(); 362 363 return true; 364} 365 366/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is 367/// attached with this instruction. 368static void SetDebugLoc(unsigned MDDbgKind, Instruction *I, 369 SelectionDAGBuilder *SDB, 370 FastISel *FastIS, MachineFunction *MF) { 371 if (isa<DbgInfoIntrinsic>(I)) return; 372 373 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) { 374 DILocation DILoc(Dbg); 375 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo()); 376 377 SDB->setCurDebugLoc(Loc); 378 379 if (FastIS) 380 FastIS->setCurDebugLoc(Loc); 381 382 // If the function doesn't have a default debug location yet, set 383 // it. This is kind of a hack. 384 if (MF->getDefaultDebugLoc().isUnknown()) 385 MF->setDefaultDebugLoc(Loc); 386 } 387} 388 389/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown. 390static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) { 391 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc()); 392 if (FastIS) 393 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc()); 394} 395 396void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, 397 BasicBlock::iterator Begin, 398 BasicBlock::iterator End, 399 bool &HadTailCall) { 400 SDB->setCurrentBasicBlock(BB); 401 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg"); 402 403 // Lower all of the non-terminator instructions. If a call is emitted 404 // as a tail call, cease emitting nodes for this block. 405 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) { 406 SetDebugLoc(MDDbgKind, I, SDB, 0, MF); 407 408 if (!isa<TerminatorInst>(I)) { 409 SDB->visit(*I); 410 411 // Set the current debug location back to "unknown" so that it doesn't 412 // spuriously apply to subsequent instructions. 413 ResetDebugLoc(SDB, 0); 414 } 415 } 416 417 if (!SDB->HasTailCall) { 418 // Ensure that all instructions which are used outside of their defining 419 // blocks are available as virtual registers. Invoke is handled elsewhere. 420 for (BasicBlock::iterator I = Begin; I != End; ++I) 421 if (!isa<PHINode>(I) && !isa<InvokeInst>(I)) 422 SDB->CopyToExportRegsIfNeeded(I); 423 424 // Handle PHI nodes in successor blocks. 425 if (End == LLVMBB->end()) { 426 HandlePHINodesInSuccessorBlocks(LLVMBB); 427 428 // Lower the terminator after the copies are emitted. 429 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF); 430 SDB->visit(*LLVMBB->getTerminator()); 431 ResetDebugLoc(SDB, 0); 432 } 433 } 434 435 // Make sure the root of the DAG is up-to-date. 436 CurDAG->setRoot(SDB->getControlRoot()); 437 438 // Final step, emit the lowered DAG as machine code. 439 CodeGenAndEmitDAG(); 440 HadTailCall = SDB->HasTailCall; 441 SDB->clear(); 442} 443 444namespace { 445/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 446/// nodes from the worklist. 447class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener { 448 SmallVector<SDNode*, 128> &Worklist; 449public: 450 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {} 451 452 virtual void NodeDeleted(SDNode *N, SDNode *E) { 453 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 454 Worklist.end()); 455 } 456 457 virtual void NodeUpdated(SDNode *N) { 458 // Ignore updates. 459 } 460}; 461} 462 463/// TrivialTruncElim - Eliminate some trivial nops that can result from 464/// ShrinkDemandedOps: (trunc (ext n)) -> n. 465static bool TrivialTruncElim(SDValue Op, 466 TargetLowering::TargetLoweringOpt &TLO) { 467 SDValue N0 = Op.getOperand(0); 468 EVT VT = Op.getValueType(); 469 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 470 N0.getOpcode() == ISD::SIGN_EXTEND || 471 N0.getOpcode() == ISD::ANY_EXTEND) && 472 N0.getOperand(0).getValueType() == VT) { 473 return TLO.CombineTo(Op, N0.getOperand(0)); 474 } 475 return false; 476} 477 478/// ShrinkDemandedOps - A late transformation pass that shrink expressions 479/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts 480/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. 481void SelectionDAGISel::ShrinkDemandedOps() { 482 SmallVector<SDNode*, 128> Worklist; 483 484 // Add all the dag nodes to the worklist. 485 Worklist.reserve(CurDAG->allnodes_size()); 486 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 487 E = CurDAG->allnodes_end(); I != E; ++I) 488 Worklist.push_back(I); 489 490 APInt Mask; 491 APInt KnownZero; 492 APInt KnownOne; 493 494 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true); 495 while (!Worklist.empty()) { 496 SDNode *N = Worklist.pop_back_val(); 497 498 if (N->use_empty() && N != CurDAG->getRoot().getNode()) { 499 CurDAG->DeleteNode(N); 500 continue; 501 } 502 503 // Run ShrinkDemandedOp on scalar binary operations. 504 if (N->getNumValues() == 1 && 505 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) { 506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 507 APInt Demanded = APInt::getAllOnesValue(BitWidth); 508 APInt KnownZero, KnownOne; 509 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, 510 KnownZero, KnownOne, TLO) || 511 (N->getOpcode() == ISD::TRUNCATE && 512 TrivialTruncElim(SDValue(N, 0), TLO))) { 513 // Revisit the node. 514 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N), 515 Worklist.end()); 516 Worklist.push_back(N); 517 518 // Replace the old value with the new one. 519 DEBUG(errs() << "\nReplacing "; 520 TLO.Old.getNode()->dump(CurDAG); 521 errs() << "\nWith: "; 522 TLO.New.getNode()->dump(CurDAG); 523 errs() << '\n'); 524 525 Worklist.push_back(TLO.New.getNode()); 526 527 SDOPsWorkListRemover DeadNodes(Worklist); 528 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 529 530 if (TLO.Old.getNode()->use_empty()) { 531 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); 532 i != e; ++i) { 533 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); 534 if (OpNode->hasOneUse()) { 535 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 536 OpNode), Worklist.end()); 537 Worklist.push_back(OpNode); 538 } 539 } 540 541 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), 542 TLO.Old.getNode()), Worklist.end()); 543 CurDAG->DeleteNode(TLO.Old.getNode()); 544 } 545 } 546 } 547 } 548} 549 550void SelectionDAGISel::ComputeLiveOutVRegInfo() { 551 SmallPtrSet<SDNode*, 128> VisitedNodes; 552 SmallVector<SDNode*, 128> Worklist; 553 554 Worklist.push_back(CurDAG->getRoot().getNode()); 555 556 APInt Mask; 557 APInt KnownZero; 558 APInt KnownOne; 559 560 do { 561 SDNode *N = Worklist.pop_back_val(); 562 563 // If we've already seen this node, ignore it. 564 if (!VisitedNodes.insert(N)) 565 continue; 566 567 // Otherwise, add all chain operands to the worklist. 568 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 569 if (N->getOperand(i).getValueType() == MVT::Other) 570 Worklist.push_back(N->getOperand(i).getNode()); 571 572 // If this is a CopyToReg with a vreg dest, process it. 573 if (N->getOpcode() != ISD::CopyToReg) 574 continue; 575 576 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 577 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 578 continue; 579 580 // Ignore non-scalar or non-integer values. 581 SDValue Src = N->getOperand(2); 582 EVT SrcVT = Src.getValueType(); 583 if (!SrcVT.isInteger() || SrcVT.isVector()) 584 continue; 585 586 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 587 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits()); 588 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); 589 590 // Only install this information if it tells us something. 591 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { 592 DestReg -= TargetRegisterInfo::FirstVirtualRegister; 593 if (DestReg >= FuncInfo->LiveOutRegInfo.size()) 594 FuncInfo->LiveOutRegInfo.resize(DestReg+1); 595 FunctionLoweringInfo::LiveOutInfo &LOI = 596 FuncInfo->LiveOutRegInfo[DestReg]; 597 LOI.NumSignBits = NumSignBits; 598 LOI.KnownOne = KnownOne; 599 LOI.KnownZero = KnownZero; 600 } 601 } while (!Worklist.empty()); 602} 603 604void SelectionDAGISel::CodeGenAndEmitDAG() { 605 std::string GroupName; 606 if (TimePassesIsEnabled) 607 GroupName = "Instruction Selection and Scheduling"; 608 std::string BlockName; 609 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 610 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 611 ViewSUnitDAGs) 612 BlockName = MF->getFunction()->getNameStr() + ":" + 613 BB->getBasicBlock()->getNameStr(); 614 615 DEBUG(dbgs() << "Initial selection DAG:\n"); 616 DEBUG(CurDAG->dump()); 617 618 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 619 620 // Run the DAG combiner in pre-legalize mode. 621 if (TimePassesIsEnabled) { 622 NamedRegionTimer T("DAG Combining 1", GroupName); 623 CurDAG->Combine(Unrestricted, *AA, OptLevel); 624 } else { 625 CurDAG->Combine(Unrestricted, *AA, OptLevel); 626 } 627 628 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); 629 DEBUG(CurDAG->dump()); 630 631 // Second step, hack on the DAG until it only uses operations and types that 632 // the target supports. 633 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 634 BlockName); 635 636 bool Changed; 637 if (TimePassesIsEnabled) { 638 NamedRegionTimer T("Type Legalization", GroupName); 639 Changed = CurDAG->LegalizeTypes(); 640 } else { 641 Changed = CurDAG->LegalizeTypes(); 642 } 643 644 DEBUG(dbgs() << "Type-legalized selection DAG:\n"); 645 DEBUG(CurDAG->dump()); 646 647 if (Changed) { 648 if (ViewDAGCombineLT) 649 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 650 651 // Run the DAG combiner in post-type-legalize mode. 652 if (TimePassesIsEnabled) { 653 NamedRegionTimer T("DAG Combining after legalize types", GroupName); 654 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 655 } else { 656 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); 657 } 658 659 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); 660 DEBUG(CurDAG->dump()); 661 } 662 663 if (TimePassesIsEnabled) { 664 NamedRegionTimer T("Vector Legalization", GroupName); 665 Changed = CurDAG->LegalizeVectors(); 666 } else { 667 Changed = CurDAG->LegalizeVectors(); 668 } 669 670 if (Changed) { 671 if (TimePassesIsEnabled) { 672 NamedRegionTimer T("Type Legalization 2", GroupName); 673 CurDAG->LegalizeTypes(); 674 } else { 675 CurDAG->LegalizeTypes(); 676 } 677 678 if (ViewDAGCombineLT) 679 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 680 681 // Run the DAG combiner in post-type-legalize mode. 682 if (TimePassesIsEnabled) { 683 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); 684 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 685 } else { 686 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 687 } 688 689 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); 690 DEBUG(CurDAG->dump()); 691 } 692 693 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 694 695 if (TimePassesIsEnabled) { 696 NamedRegionTimer T("DAG Legalization", GroupName); 697 CurDAG->Legalize(OptLevel); 698 } else { 699 CurDAG->Legalize(OptLevel); 700 } 701 702 DEBUG(dbgs() << "Legalized selection DAG:\n"); 703 DEBUG(CurDAG->dump()); 704 705 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 706 707 // Run the DAG combiner in post-legalize mode. 708 if (TimePassesIsEnabled) { 709 NamedRegionTimer T("DAG Combining 2", GroupName); 710 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 711 } else { 712 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); 713 } 714 715 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); 716 DEBUG(CurDAG->dump()); 717 718 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 719 720 if (OptLevel != CodeGenOpt::None) { 721 ShrinkDemandedOps(); 722 ComputeLiveOutVRegInfo(); 723 } 724 725 // Third, instruction select all of the operations to machine code, adding the 726 // code to the MachineBasicBlock. 727 if (TimePassesIsEnabled) { 728 NamedRegionTimer T("Instruction Selection", GroupName); 729 DoInstructionSelection(); 730 } else { 731 DoInstructionSelection(); 732 } 733 734 DEBUG(dbgs() << "Selected selection DAG:\n"); 735 DEBUG(CurDAG->dump()); 736 737 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 738 739 // Schedule machine code. 740 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 741 if (TimePassesIsEnabled) { 742 NamedRegionTimer T("Instruction Scheduling", GroupName); 743 Scheduler->Run(CurDAG, BB, BB->end()); 744 } else { 745 Scheduler->Run(CurDAG, BB, BB->end()); 746 } 747 748 if (ViewSUnitDAGs) Scheduler->viewGraph(); 749 750 // Emit machine code to BB. This can change 'BB' to the last block being 751 // inserted into. 752 if (TimePassesIsEnabled) { 753 NamedRegionTimer T("Instruction Creation", GroupName); 754 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 755 } else { 756 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping); 757 } 758 759 // Free the scheduler state. 760 if (TimePassesIsEnabled) { 761 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); 762 delete Scheduler; 763 } else { 764 delete Scheduler; 765 } 766 767 DEBUG(dbgs() << "Selected machine code:\n"); 768 DEBUG(BB->dump()); 769} 770 771void SelectionDAGISel::DoInstructionSelection() { 772 DEBUG(errs() << "===== Instruction selection begins:\n"); 773 774 PreprocessISelDAG(); 775 776 // Select target instructions for the DAG. 777 { 778 // Number all nodes with a topological order and set DAGSize. 779 DAGSize = CurDAG->AssignTopologicalOrder(); 780 781 // Create a dummy node (which is not added to allnodes), that adds 782 // a reference to the root node, preventing it from being deleted, 783 // and tracking any changes of the root. 784 HandleSDNode Dummy(CurDAG->getRoot()); 785 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode()); 786 ++ISelPosition; 787 788 // The AllNodes list is now topological-sorted. Visit the 789 // nodes by starting at the end of the list (the root of the 790 // graph) and preceding back toward the beginning (the entry 791 // node). 792 while (ISelPosition != CurDAG->allnodes_begin()) { 793 SDNode *Node = --ISelPosition; 794 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 795 // but there are currently some corner cases that it misses. Also, this 796 // makes it theoretically possible to disable the DAGCombiner. 797 if (Node->use_empty()) 798 continue; 799 800 SDNode *ResNode = Select(Node); 801 802 // FIXME: This is pretty gross. 'Select' should be changed to not return 803 // anything at all and this code should be nuked with a tactical strike. 804 805 // If node should not be replaced, continue with the next one. 806 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 807 continue; 808 // Replace node. 809 if (ResNode) 810 ReplaceUses(Node, ResNode); 811 812 // If after the replacement this node is not used any more, 813 // remove this dead node. 814 if (Node->use_empty()) { // Don't delete EntryToken, etc. 815 ISelUpdater ISU(ISelPosition); 816 CurDAG->RemoveDeadNode(Node, &ISU); 817 } 818 } 819 820 CurDAG->setRoot(Dummy.getValue()); 821 } 822 DEBUG(errs() << "===== Instruction selection ends:\n"); 823 824 PostprocessISelDAG(); 825 826 // FIXME: This shouldn't be needed, remove it. 827 CurDAG->RemoveDeadNodes(); 828} 829 830 831void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, 832 MachineFunction &MF, 833 MachineModuleInfo *MMI, 834 DwarfWriter *DW, 835 const TargetInstrInfo &TII) { 836 // Initialize the Fast-ISel state, if needed. 837 FastISel *FastIS = 0; 838 if (EnableFastISel) 839 FastIS = TLI.createFastISel(MF, MMI, DW, 840 FuncInfo->ValueMap, 841 FuncInfo->MBBMap, 842 FuncInfo->StaticAllocaMap 843#ifndef NDEBUG 844 , FuncInfo->CatchInfoLost 845#endif 846 ); 847 848 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg"); 849 850 // Iterate over all basic blocks in the function. 851 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { 852 BasicBlock *LLVMBB = &*I; 853 BB = FuncInfo->MBBMap[LLVMBB]; 854 855 BasicBlock::iterator const Begin = LLVMBB->begin(); 856 BasicBlock::iterator const End = LLVMBB->end(); 857 BasicBlock::iterator BI = Begin; 858 859 // Lower any arguments needed in this block if this is the entry block. 860 bool SuppressFastISel = false; 861 if (LLVMBB == &Fn.getEntryBlock()) { 862 LowerArguments(LLVMBB); 863 864 // If any of the arguments has the byval attribute, forgo 865 // fast-isel in the entry block. 866 if (FastIS) { 867 unsigned j = 1; 868 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end(); 869 I != E; ++I, ++j) 870 if (Fn.paramHasAttr(j, Attribute::ByVal)) { 871 if (EnableFastISelVerbose || EnableFastISelAbort) 872 dbgs() << "FastISel skips entry block due to byval argument\n"; 873 SuppressFastISel = true; 874 break; 875 } 876 } 877 } 878 879 if (MMI && BB->isLandingPad()) { 880 // Add a label to mark the beginning of the landing pad. Deletion of the 881 // landing pad can thus be detected via the MachineModuleInfo. 882 unsigned LabelID = MMI->addLandingPad(BB); 883 884 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL); 885 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID); 886 887 // Mark exception register as live in. 888 unsigned Reg = TLI.getExceptionAddressRegister(); 889 if (Reg) BB->addLiveIn(Reg); 890 891 // Mark exception selector register as live in. 892 Reg = TLI.getExceptionSelectorRegister(); 893 if (Reg) BB->addLiveIn(Reg); 894 895 // FIXME: Hack around an exception handling flaw (PR1508): the personality 896 // function and list of typeids logically belong to the invoke (or, if you 897 // like, the basic block containing the invoke), and need to be associated 898 // with it in the dwarf exception handling tables. Currently however the 899 // information is provided by an intrinsic (eh.selector) that can be moved 900 // to unexpected places by the optimizers: if the unwind edge is critical, 901 // then breaking it can result in the intrinsics being in the successor of 902 // the landing pad, not the landing pad itself. This results 903 // in exceptions not being caught because no typeids are associated with 904 // the invoke. This may not be the only way things can go wrong, but it 905 // is the only way we try to work around for the moment. 906 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator()); 907 908 if (Br && Br->isUnconditional()) { // Critical edge? 909 BasicBlock::iterator I, E; 910 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) 911 if (isa<EHSelectorInst>(I)) 912 break; 913 914 if (I == E) 915 // No catch info found - try to extract some from the successor. 916 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo); 917 } 918 } 919 920 // Before doing SelectionDAG ISel, see if FastISel has been requested. 921 if (FastIS && !SuppressFastISel) { 922 // Emit code for any incoming arguments. This must happen before 923 // beginning FastISel on the entry block. 924 if (LLVMBB == &Fn.getEntryBlock()) { 925 CurDAG->setRoot(SDB->getControlRoot()); 926 CodeGenAndEmitDAG(); 927 SDB->clear(); 928 } 929 FastIS->startNewBlock(BB); 930 // Do FastISel on as many instructions as possible. 931 for (; BI != End; ++BI) { 932 // Just before the terminator instruction, insert instructions to 933 // feed PHI nodes in successor blocks. 934 if (isa<TerminatorInst>(BI)) 935 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) { 936 ++NumFastIselFailures; 937 ResetDebugLoc(SDB, FastIS); 938 if (EnableFastISelVerbose || EnableFastISelAbort) { 939 dbgs() << "FastISel miss: "; 940 BI->dump(); 941 } 942 assert(!EnableFastISelAbort && 943 "FastISel didn't handle a PHI in a successor"); 944 break; 945 } 946 947 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF); 948 949 // Try to select the instruction with FastISel. 950 if (FastIS->SelectInstruction(BI)) { 951 ResetDebugLoc(SDB, FastIS); 952 continue; 953 } 954 955 // Clear out the debug location so that it doesn't carry over to 956 // unrelated instructions. 957 ResetDebugLoc(SDB, FastIS); 958 959 // Then handle certain instructions as single-LLVM-Instruction blocks. 960 if (isa<CallInst>(BI)) { 961 ++NumFastIselFailures; 962 if (EnableFastISelVerbose || EnableFastISelAbort) { 963 dbgs() << "FastISel missed call: "; 964 BI->dump(); 965 } 966 967 if (!BI->getType()->isVoidTy()) { 968 unsigned &R = FuncInfo->ValueMap[BI]; 969 if (!R) 970 R = FuncInfo->CreateRegForValue(BI); 971 } 972 973 bool HadTailCall = false; 974 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall); 975 976 // If the call was emitted as a tail call, we're done with the block. 977 if (HadTailCall) { 978 BI = End; 979 break; 980 } 981 982 // If the instruction was codegen'd with multiple blocks, 983 // inform the FastISel object where to resume inserting. 984 FastIS->setCurrentBlock(BB); 985 continue; 986 } 987 988 // Otherwise, give up on FastISel for the rest of the block. 989 // For now, be a little lenient about non-branch terminators. 990 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) { 991 ++NumFastIselFailures; 992 if (EnableFastISelVerbose || EnableFastISelAbort) { 993 dbgs() << "FastISel miss: "; 994 BI->dump(); 995 } 996 if (EnableFastISelAbort) 997 // The "fast" selector couldn't handle something and bailed. 998 // For the purpose of debugging, just abort. 999 llvm_unreachable("FastISel didn't select the entire block"); 1000 } 1001 break; 1002 } 1003 } 1004 1005 // Run SelectionDAG instruction selection on the remainder of the block 1006 // not handled by FastISel. If FastISel is not run, this is the entire 1007 // block. 1008 if (BI != End) { 1009 bool HadTailCall; 1010 SelectBasicBlock(LLVMBB, BI, End, HadTailCall); 1011 } 1012 1013 FinishBasicBlock(); 1014 } 1015 1016 delete FastIS; 1017} 1018 1019void 1020SelectionDAGISel::FinishBasicBlock() { 1021 1022 DEBUG(dbgs() << "Target-post-processed machine code:\n"); 1023 DEBUG(BB->dump()); 1024 1025 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1026 << SDB->PHINodesToUpdate.size() << "\n"); 1027 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) 1028 dbgs() << "Node " << i << " : (" 1029 << SDB->PHINodesToUpdate[i].first 1030 << ", " << SDB->PHINodesToUpdate[i].second << ")\n"); 1031 1032 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1033 // PHI nodes in successors. 1034 if (SDB->SwitchCases.empty() && 1035 SDB->JTCases.empty() && 1036 SDB->BitTestCases.empty()) { 1037 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1038 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1039 assert(PHI->isPHI() && 1040 "This is not a machine PHI node that we are updating!"); 1041 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1042 false)); 1043 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1044 } 1045 SDB->PHINodesToUpdate.clear(); 1046 return; 1047 } 1048 1049 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1050 // Lower header first, if it wasn't already lowered 1051 if (!SDB->BitTestCases[i].Emitted) { 1052 // Set the current basic block to the mbb we wish to insert the code into 1053 BB = SDB->BitTestCases[i].Parent; 1054 SDB->setCurrentBasicBlock(BB); 1055 // Emit the code 1056 SDB->visitBitTestHeader(SDB->BitTestCases[i]); 1057 CurDAG->setRoot(SDB->getRoot()); 1058 CodeGenAndEmitDAG(); 1059 SDB->clear(); 1060 } 1061 1062 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1063 // Set the current basic block to the mbb we wish to insert the code into 1064 BB = SDB->BitTestCases[i].Cases[j].ThisBB; 1065 SDB->setCurrentBasicBlock(BB); 1066 // Emit the code 1067 if (j+1 != ej) 1068 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, 1069 SDB->BitTestCases[i].Reg, 1070 SDB->BitTestCases[i].Cases[j]); 1071 else 1072 SDB->visitBitTestCase(SDB->BitTestCases[i].Default, 1073 SDB->BitTestCases[i].Reg, 1074 SDB->BitTestCases[i].Cases[j]); 1075 1076 1077 CurDAG->setRoot(SDB->getRoot()); 1078 CodeGenAndEmitDAG(); 1079 SDB->clear(); 1080 } 1081 1082 // Update PHI Nodes 1083 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1084 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1085 MachineBasicBlock *PHIBB = PHI->getParent(); 1086 assert(PHI->isPHI() && 1087 "This is not a machine PHI node that we are updating!"); 1088 // This is "default" BB. We have two jumps to it. From "header" BB and 1089 // from last "case" BB. 1090 if (PHIBB == SDB->BitTestCases[i].Default) { 1091 PHI->addOperand(MachineOperand:: 1092 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1093 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1094 PHI->addOperand(MachineOperand:: 1095 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1096 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1097 back().ThisBB)); 1098 } 1099 // One of "cases" BB. 1100 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1101 j != ej; ++j) { 1102 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1103 if (cBB->isSuccessor(PHIBB)) { 1104 PHI->addOperand(MachineOperand:: 1105 CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1106 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1107 } 1108 } 1109 } 1110 } 1111 SDB->BitTestCases.clear(); 1112 1113 // If the JumpTable record is filled in, then we need to emit a jump table. 1114 // Updating the PHI nodes is tricky in this case, since we need to determine 1115 // whether the PHI is a successor of the range check MBB or the jump table MBB 1116 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1117 // Lower header first, if it wasn't already lowered 1118 if (!SDB->JTCases[i].first.Emitted) { 1119 // Set the current basic block to the mbb we wish to insert the code into 1120 BB = SDB->JTCases[i].first.HeaderBB; 1121 SDB->setCurrentBasicBlock(BB); 1122 // Emit the code 1123 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first); 1124 CurDAG->setRoot(SDB->getRoot()); 1125 CodeGenAndEmitDAG(); 1126 SDB->clear(); 1127 } 1128 1129 // Set the current basic block to the mbb we wish to insert the code into 1130 BB = SDB->JTCases[i].second.MBB; 1131 SDB->setCurrentBasicBlock(BB); 1132 // Emit the code 1133 SDB->visitJumpTable(SDB->JTCases[i].second); 1134 CurDAG->setRoot(SDB->getRoot()); 1135 CodeGenAndEmitDAG(); 1136 SDB->clear(); 1137 1138 // Update PHI Nodes 1139 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) { 1140 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first; 1141 MachineBasicBlock *PHIBB = PHI->getParent(); 1142 assert(PHI->isPHI() && 1143 "This is not a machine PHI node that we are updating!"); 1144 // "default" BB. We can go there only from header BB. 1145 if (PHIBB == SDB->JTCases[i].second.Default) { 1146 PHI->addOperand 1147 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1148 PHI->addOperand 1149 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1150 } 1151 // JT BB. Just iterate over successors here 1152 if (BB->isSuccessor(PHIBB)) { 1153 PHI->addOperand 1154 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false)); 1155 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1156 } 1157 } 1158 } 1159 SDB->JTCases.clear(); 1160 1161 // If the switch block involved a branch to one of the actual successors, we 1162 // need to update PHI nodes in that block. 1163 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) { 1164 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first; 1165 assert(PHI->isPHI() && 1166 "This is not a machine PHI node that we are updating!"); 1167 if (BB->isSuccessor(PHI->getParent())) { 1168 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second, 1169 false)); 1170 PHI->addOperand(MachineOperand::CreateMBB(BB)); 1171 } 1172 } 1173 1174 // If we generated any switch lowering information, build and codegen any 1175 // additional DAGs necessary. 1176 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1177 // Set the current basic block to the mbb we wish to insert the code into 1178 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; 1179 SDB->setCurrentBasicBlock(BB); 1180 1181 // Emit the code 1182 SDB->visitSwitchCase(SDB->SwitchCases[i]); 1183 CurDAG->setRoot(SDB->getRoot()); 1184 CodeGenAndEmitDAG(); 1185 1186 // Handle any PHI nodes in successors of this chunk, as if we were coming 1187 // from the original BB before switch expansion. Note that PHI nodes can 1188 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1189 // handle them the right number of times. 1190 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 1191 // If new BB's are created during scheduling, the edges may have been 1192 // updated. That is, the edge from ThisBB to BB may have been split and 1193 // BB's predecessor is now another block. 1194 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI = 1195 SDB->EdgeMapping.find(BB); 1196 if (EI != SDB->EdgeMapping.end()) 1197 ThisBB = EI->second; 1198 1199 // BB may have been removed from the CFG if a branch was constant folded. 1200 if (ThisBB->isSuccessor(BB)) { 1201 for (MachineBasicBlock::iterator Phi = BB->begin(); 1202 Phi != BB->end() && Phi->isPHI(); 1203 ++Phi) { 1204 // This value for this PHI node is recorded in PHINodesToUpdate. 1205 for (unsigned pn = 0; ; ++pn) { 1206 assert(pn != SDB->PHINodesToUpdate.size() && 1207 "Didn't find PHI entry!"); 1208 if (SDB->PHINodesToUpdate[pn].first == Phi) { 1209 Phi->addOperand(MachineOperand:: 1210 CreateReg(SDB->PHINodesToUpdate[pn].second, 1211 false)); 1212 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1213 break; 1214 } 1215 } 1216 } 1217 } 1218 1219 // Don't process RHS if same block as LHS. 1220 if (BB == SDB->SwitchCases[i].FalseBB) 1221 SDB->SwitchCases[i].FalseBB = 0; 1222 1223 // If we haven't handled the RHS, do so now. Otherwise, we're done. 1224 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB; 1225 SDB->SwitchCases[i].FalseBB = 0; 1226 } 1227 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0); 1228 SDB->clear(); 1229 } 1230 SDB->SwitchCases.clear(); 1231 1232 SDB->PHINodesToUpdate.clear(); 1233} 1234 1235 1236/// Create the scheduler. If a specific scheduler was specified 1237/// via the SchedulerRegistry, use it, otherwise select the 1238/// one preferred by the target. 1239/// 1240ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1241 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1242 1243 if (!Ctor) { 1244 Ctor = ISHeuristic; 1245 RegisterScheduler::setDefault(Ctor); 1246 } 1247 1248 return Ctor(this, OptLevel); 1249} 1250 1251ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 1252 return new ScheduleHazardRecognizer(); 1253} 1254 1255//===----------------------------------------------------------------------===// 1256// Helper functions used by the generated instruction selector. 1257//===----------------------------------------------------------------------===// 1258// Calls to these methods are generated by tblgen. 1259 1260/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1261/// the dag combiner simplified the 255, we still want to match. RHS is the 1262/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1263/// specified in the .td file (e.g. 255). 1264bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1265 int64_t DesiredMaskS) const { 1266 const APInt &ActualMask = RHS->getAPIntValue(); 1267 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1268 1269 // If the actual mask exactly matches, success! 1270 if (ActualMask == DesiredMask) 1271 return true; 1272 1273 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1274 if (ActualMask.intersects(~DesiredMask)) 1275 return false; 1276 1277 // Otherwise, the DAG Combiner may have proven that the value coming in is 1278 // either already zero or is not demanded. Check for known zero input bits. 1279 APInt NeededMask = DesiredMask & ~ActualMask; 1280 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1281 return true; 1282 1283 // TODO: check to see if missing bits are just not demanded. 1284 1285 // Otherwise, this pattern doesn't match. 1286 return false; 1287} 1288 1289/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1290/// the dag combiner simplified the 255, we still want to match. RHS is the 1291/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1292/// specified in the .td file (e.g. 255). 1293bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1294 int64_t DesiredMaskS) const { 1295 const APInt &ActualMask = RHS->getAPIntValue(); 1296 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1297 1298 // If the actual mask exactly matches, success! 1299 if (ActualMask == DesiredMask) 1300 return true; 1301 1302 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1303 if (ActualMask.intersects(~DesiredMask)) 1304 return false; 1305 1306 // Otherwise, the DAG Combiner may have proven that the value coming in is 1307 // either already zero or is not demanded. Check for known zero input bits. 1308 APInt NeededMask = DesiredMask & ~ActualMask; 1309 1310 APInt KnownZero, KnownOne; 1311 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 1312 1313 // If all the missing bits in the or are already known to be set, match! 1314 if ((NeededMask & KnownOne) == NeededMask) 1315 return true; 1316 1317 // TODO: check to see if missing bits are just not demanded. 1318 1319 // Otherwise, this pattern doesn't match. 1320 return false; 1321} 1322 1323 1324/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1325/// by tblgen. Others should not call it. 1326void SelectionDAGISel:: 1327SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1328 std::vector<SDValue> InOps; 1329 std::swap(InOps, Ops); 1330 1331 Ops.push_back(InOps[0]); // input chain. 1332 Ops.push_back(InOps[1]); // input asm string. 1333 1334 unsigned i = 2, e = InOps.size(); 1335 if (InOps[e-1].getValueType() == MVT::Flag) 1336 --e; // Don't process a flag operand if it is here. 1337 1338 while (i != e) { 1339 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1340 if ((Flags & 7) != 4 /*MEM*/) { 1341 // Just skip over this operand, copying the operands verbatim. 1342 Ops.insert(Ops.end(), InOps.begin()+i, 1343 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1344 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1345 } else { 1346 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1347 "Memory operand with multiple values?"); 1348 // Otherwise, this is a memory operand. Ask the target to select it. 1349 std::vector<SDValue> SelOps; 1350 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) { 1351 llvm_report_error("Could not match memory address. Inline asm" 1352 " failure!"); 1353 } 1354 1355 // Add this to the output node. 1356 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), 1357 MVT::i32)); 1358 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1359 i += 2; 1360 } 1361 } 1362 1363 // Add the flag input back if present. 1364 if (e != InOps.size()) 1365 Ops.push_back(InOps.back()); 1366} 1367 1368/// findFlagUse - Return use of EVT::Flag value produced by the specified 1369/// SDNode. 1370/// 1371static SDNode *findFlagUse(SDNode *N) { 1372 unsigned FlagResNo = N->getNumValues()-1; 1373 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1374 SDUse &Use = I.getUse(); 1375 if (Use.getResNo() == FlagResNo) 1376 return Use.getUser(); 1377 } 1378 return NULL; 1379} 1380 1381/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1382/// This function recursively traverses up the operand chain, ignoring 1383/// certain nodes. 1384static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1385 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1386 bool IgnoreChains) { 1387 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1388 // greater than all of its (recursive) operands. If we scan to a point where 1389 // 'use' is smaller than the node we're scanning for, then we know we will 1390 // never find it. 1391 // 1392 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1393 // happen because we scan down to newly selected nodes in the case of flag 1394 // uses. 1395 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1396 return false; 1397 1398 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1399 // won't fail if we scan it again. 1400 if (!Visited.insert(Use)) 1401 return false; 1402 1403 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1404 // Ignore chain uses, they are validated by HandleMergeInputChains. 1405 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1406 continue; 1407 1408 SDNode *N = Use->getOperand(i).getNode(); 1409 if (N == Def) { 1410 if (Use == ImmedUse || Use == Root) 1411 continue; // We are not looking for immediate use. 1412 assert(N != Root); 1413 return true; 1414 } 1415 1416 // Traverse up the operand chain. 1417 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1418 return true; 1419 } 1420 return false; 1421} 1422 1423/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1424/// operand node N of U during instruction selection that starts at Root. 1425bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1426 SDNode *Root) const { 1427 if (OptLevel == CodeGenOpt::None) return false; 1428 return N.hasOneUse(); 1429} 1430 1431/// IsLegalToFold - Returns true if the specific operand node N of 1432/// U can be folded during instruction selection that starts at Root. 1433bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1434 bool IgnoreChains) const { 1435 if (OptLevel == CodeGenOpt::None) return false; 1436 1437 // If Root use can somehow reach N through a path that that doesn't contain 1438 // U then folding N would create a cycle. e.g. In the following 1439 // diagram, Root can reach N through X. If N is folded into into Root, then 1440 // X is both a predecessor and a successor of U. 1441 // 1442 // [N*] // 1443 // ^ ^ // 1444 // / \ // 1445 // [U*] [X]? // 1446 // ^ ^ // 1447 // \ / // 1448 // \ / // 1449 // [Root*] // 1450 // 1451 // * indicates nodes to be folded together. 1452 // 1453 // If Root produces a flag, then it gets (even more) interesting. Since it 1454 // will be "glued" together with its flag use in the scheduler, we need to 1455 // check if it might reach N. 1456 // 1457 // [N*] // 1458 // ^ ^ // 1459 // / \ // 1460 // [U*] [X]? // 1461 // ^ ^ // 1462 // \ \ // 1463 // \ | // 1464 // [Root*] | // 1465 // ^ | // 1466 // f | // 1467 // | / // 1468 // [Y] / // 1469 // ^ / // 1470 // f / // 1471 // | / // 1472 // [FU] // 1473 // 1474 // If FU (flag use) indirectly reaches N (the load), and Root folds N 1475 // (call it Fold), then X is a predecessor of FU and a successor of 1476 // Fold. But since Fold and FU are flagged together, this will create 1477 // a cycle in the scheduling graph. 1478 1479 // If the node has flags, walk down the graph to the "lowest" node in the 1480 // flagged set. 1481 EVT VT = Root->getValueType(Root->getNumValues()-1); 1482 while (VT == MVT::Flag) { 1483 SDNode *FU = findFlagUse(Root); 1484 if (FU == NULL) 1485 break; 1486 Root = FU; 1487 VT = Root->getValueType(Root->getNumValues()-1); 1488 } 1489 1490 SmallPtrSet<SDNode*, 16> Visited; 1491 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1492} 1493 1494SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1495 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1496 SelectInlineAsmMemoryOperands(Ops); 1497 1498 std::vector<EVT> VTs; 1499 VTs.push_back(MVT::Other); 1500 VTs.push_back(MVT::Flag); 1501 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1502 VTs, &Ops[0], Ops.size()); 1503 New->setNodeId(-1); 1504 return New.getNode(); 1505} 1506 1507SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1508 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1509} 1510 1511SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) { 1512 SDValue Chain = N->getOperand(0); 1513 unsigned C = cast<LabelSDNode>(N)->getLabelID(); 1514 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32); 1515 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL, 1516 MVT::Other, Tmp, Chain); 1517} 1518 1519/// GetVBR - decode a vbr encoding whose top bit is set. 1520ALWAYS_INLINE static uint64_t 1521GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1522 assert(Val >= 128 && "Not a VBR"); 1523 Val &= 127; // Remove first vbr bit. 1524 1525 unsigned Shift = 7; 1526 uint64_t NextBits; 1527 do { 1528 NextBits = MatcherTable[Idx++]; 1529 Val |= (NextBits&127) << Shift; 1530 Shift += 7; 1531 } while (NextBits & 128); 1532 1533 return Val; 1534} 1535 1536 1537/// UpdateChainsAndFlags - When a match is complete, this method updates uses of 1538/// interior flag and chain results to use the new flag and chain results. 1539void SelectionDAGISel:: 1540UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain, 1541 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1542 SDValue InputFlag, 1543 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched, 1544 bool isMorphNodeTo) { 1545 SmallVector<SDNode*, 4> NowDeadNodes; 1546 1547 ISelUpdater ISU(ISelPosition); 1548 1549 // Now that all the normal results are replaced, we replace the chain and 1550 // flag results if present. 1551 if (!ChainNodesMatched.empty()) { 1552 assert(InputChain.getNode() != 0 && 1553 "Matched input chains but didn't produce a chain"); 1554 // Loop over all of the nodes we matched that produced a chain result. 1555 // Replace all the chain results with the final chain we ended up with. 1556 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1557 SDNode *ChainNode = ChainNodesMatched[i]; 1558 1559 // If this node was already deleted, don't look at it. 1560 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1561 continue; 1562 1563 // Don't replace the results of the root node if we're doing a 1564 // MorphNodeTo. 1565 if (ChainNode == NodeToMatch && isMorphNodeTo) 1566 continue; 1567 1568 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1569 if (ChainVal.getValueType() == MVT::Flag) 1570 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1571 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1572 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU); 1573 1574 // If the node became dead, delete it. 1575 if (ChainNode->use_empty()) 1576 NowDeadNodes.push_back(ChainNode); 1577 } 1578 } 1579 1580 // If the result produces a flag, update any flag results in the matched 1581 // pattern with the flag result. 1582 if (InputFlag.getNode() != 0) { 1583 // Handle any interior nodes explicitly marked. 1584 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) { 1585 SDNode *FRN = FlagResultNodesMatched[i]; 1586 1587 // If this node was already deleted, don't look at it. 1588 if (FRN->getOpcode() == ISD::DELETED_NODE) 1589 continue; 1590 1591 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag && 1592 "Doesn't have a flag result"); 1593 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1594 InputFlag, &ISU); 1595 1596 // If the node became dead, delete it. 1597 if (FRN->use_empty()) 1598 NowDeadNodes.push_back(FRN); 1599 } 1600 } 1601 1602 if (!NowDeadNodes.empty()) 1603 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU); 1604 1605 DEBUG(errs() << "ISEL: Match complete!\n"); 1606} 1607 1608enum ChainResult { 1609 CR_Simple, 1610 CR_InducesCycle, 1611 CR_LeadsToInteriorNode 1612}; 1613 1614/// WalkChainUsers - Walk down the users of the specified chained node that is 1615/// part of the pattern we're matching, looking at all of the users we find. 1616/// This determines whether something is an interior node, whether we have a 1617/// non-pattern node in between two pattern nodes (which prevent folding because 1618/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1619/// between pattern nodes (in which case the TF becomes part of the pattern). 1620/// 1621/// The walk we do here is guaranteed to be small because we quickly get down to 1622/// already selected nodes "below" us. 1623static ChainResult 1624WalkChainUsers(SDNode *ChainedNode, 1625 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1626 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1627 ChainResult Result = CR_Simple; 1628 1629 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1630 E = ChainedNode->use_end(); UI != E; ++UI) { 1631 // Make sure the use is of the chain, not some other value we produce. 1632 if (UI.getUse().getValueType() != MVT::Other) continue; 1633 1634 SDNode *User = *UI; 1635 1636 // If we see an already-selected machine node, then we've gone beyond the 1637 // pattern that we're selecting down into the already selected chunk of the 1638 // DAG. 1639 if (User->isMachineOpcode() || 1640 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1641 continue; 1642 1643 if (User->getOpcode() == ISD::CopyToReg || 1644 User->getOpcode() == ISD::CopyFromReg || 1645 User->getOpcode() == ISD::INLINEASM) { 1646 // If their node ID got reset to -1 then they've already been selected. 1647 // Treat them like a MachineOpcode. 1648 if (User->getNodeId() == -1) 1649 continue; 1650 } 1651 1652 // If we have a TokenFactor, we handle it specially. 1653 if (User->getOpcode() != ISD::TokenFactor) { 1654 // If the node isn't a token factor and isn't part of our pattern, then it 1655 // must be a random chained node in between two nodes we're selecting. 1656 // This happens when we have something like: 1657 // x = load ptr 1658 // call 1659 // y = x+4 1660 // store y -> ptr 1661 // Because we structurally match the load/store as a read/modify/write, 1662 // but the call is chained between them. We cannot fold in this case 1663 // because it would induce a cycle in the graph. 1664 if (!std::count(ChainedNodesInPattern.begin(), 1665 ChainedNodesInPattern.end(), User)) 1666 return CR_InducesCycle; 1667 1668 // Otherwise we found a node that is part of our pattern. For example in: 1669 // x = load ptr 1670 // y = x+4 1671 // store y -> ptr 1672 // This would happen when we're scanning down from the load and see the 1673 // store as a user. Record that there is a use of ChainedNode that is 1674 // part of the pattern and keep scanning uses. 1675 Result = CR_LeadsToInteriorNode; 1676 InteriorChainedNodes.push_back(User); 1677 continue; 1678 } 1679 1680 // If we found a TokenFactor, there are two cases to consider: first if the 1681 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1682 // uses of the TF are in our pattern) we just want to ignore it. Second, 1683 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1684 // [Load chain] 1685 // ^ 1686 // | 1687 // [Load] 1688 // ^ ^ 1689 // | \ DAG's like cheese 1690 // / \ do you? 1691 // / | 1692 // [TokenFactor] [Op] 1693 // ^ ^ 1694 // | | 1695 // \ / 1696 // \ / 1697 // [Store] 1698 // 1699 // In this case, the TokenFactor becomes part of our match and we rewrite it 1700 // as a new TokenFactor. 1701 // 1702 // To distinguish these two cases, do a recursive walk down the uses. 1703 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1704 case CR_Simple: 1705 // If the uses of the TokenFactor are just already-selected nodes, ignore 1706 // it, it is "below" our pattern. 1707 continue; 1708 case CR_InducesCycle: 1709 // If the uses of the TokenFactor lead to nodes that are not part of our 1710 // pattern that are not selected, folding would turn this into a cycle, 1711 // bail out now. 1712 return CR_InducesCycle; 1713 case CR_LeadsToInteriorNode: 1714 break; // Otherwise, keep processing. 1715 } 1716 1717 // Okay, we know we're in the interesting interior case. The TokenFactor 1718 // is now going to be considered part of the pattern so that we rewrite its 1719 // uses (it may have uses that are not part of the pattern) with the 1720 // ultimate chain result of the generated code. We will also add its chain 1721 // inputs as inputs to the ultimate TokenFactor we create. 1722 Result = CR_LeadsToInteriorNode; 1723 ChainedNodesInPattern.push_back(User); 1724 InteriorChainedNodes.push_back(User); 1725 continue; 1726 } 1727 1728 return Result; 1729} 1730 1731/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1732/// operation for when the pattern matched at least one node with a chains. The 1733/// input vector contains a list of all of the chained nodes that we match. We 1734/// must determine if this is a valid thing to cover (i.e. matching it won't 1735/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1736/// be used as the input node chain for the generated nodes. 1737static SDValue 1738HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1739 SelectionDAG *CurDAG) { 1740 // Walk all of the chained nodes we've matched, recursively scanning down the 1741 // users of the chain result. This adds any TokenFactor nodes that are caught 1742 // in between chained nodes to the chained and interior nodes list. 1743 SmallVector<SDNode*, 3> InteriorChainedNodes; 1744 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1745 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1746 InteriorChainedNodes) == CR_InducesCycle) 1747 return SDValue(); // Would induce a cycle. 1748 } 1749 1750 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1751 // that we are interested in. Form our input TokenFactor node. 1752 SmallVector<SDValue, 3> InputChains; 1753 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1754 // Add the input chain of this node to the InputChains list (which will be 1755 // the operands of the generated TokenFactor) if it's not an interior node. 1756 SDNode *N = ChainNodesMatched[i]; 1757 if (N->getOpcode() != ISD::TokenFactor) { 1758 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1759 continue; 1760 1761 // Otherwise, add the input chain. 1762 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1763 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1764 InputChains.push_back(InChain); 1765 continue; 1766 } 1767 1768 // If we have a token factor, we want to add all inputs of the token factor 1769 // that are not part of the pattern we're matching. 1770 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1771 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1772 N->getOperand(op).getNode())) 1773 InputChains.push_back(N->getOperand(op)); 1774 } 1775 } 1776 1777 SDValue Res; 1778 if (InputChains.size() == 1) 1779 return InputChains[0]; 1780 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1781 MVT::Other, &InputChains[0], InputChains.size()); 1782} 1783 1784/// MorphNode - Handle morphing a node in place for the selector. 1785SDNode *SelectionDAGISel:: 1786MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1787 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1788 // It is possible we're using MorphNodeTo to replace a node with no 1789 // normal results with one that has a normal result (or we could be 1790 // adding a chain) and the input could have flags and chains as well. 1791 // In this case we need to shifting the operands down. 1792 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1793 // than the old isel though. We should sink this into MorphNodeTo. 1794 int OldFlagResultNo = -1, OldChainResultNo = -1; 1795 1796 unsigned NTMNumResults = Node->getNumValues(); 1797 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) { 1798 OldFlagResultNo = NTMNumResults-1; 1799 if (NTMNumResults != 1 && 1800 Node->getValueType(NTMNumResults-2) == MVT::Other) 1801 OldChainResultNo = NTMNumResults-2; 1802 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1803 OldChainResultNo = NTMNumResults-1; 1804 1805 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1806 // that this deletes operands of the old node that become dead. 1807 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1808 1809 // MorphNodeTo can operate in two ways: if an existing node with the 1810 // specified operands exists, it can just return it. Otherwise, it 1811 // updates the node in place to have the requested operands. 1812 if (Res == Node) { 1813 // If we updated the node in place, reset the node ID. To the isel, 1814 // this should be just like a newly allocated machine node. 1815 Res->setNodeId(-1); 1816 } 1817 1818 unsigned ResNumResults = Res->getNumValues(); 1819 // Move the flag if needed. 1820 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 && 1821 (unsigned)OldFlagResultNo != ResNumResults-1) 1822 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo), 1823 SDValue(Res, ResNumResults-1)); 1824 1825 if ((EmitNodeInfo & OPFL_FlagOutput) != 0) 1826 --ResNumResults; 1827 1828 // Move the chain reference if needed. 1829 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1830 (unsigned)OldChainResultNo != ResNumResults-1) 1831 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1832 SDValue(Res, ResNumResults-1)); 1833 1834 // Otherwise, no replacement happened because the node already exists. Replace 1835 // Uses of the old node with the new one. 1836 if (Res != Node) 1837 CurDAG->ReplaceAllUsesWith(Node, Res); 1838 1839 return Res; 1840} 1841 1842/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1843ALWAYS_INLINE static bool 1844CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1845 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) { 1846 // Accept if it is exactly the same as a previously recorded node. 1847 unsigned RecNo = MatcherTable[MatcherIndex++]; 1848 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1849 return N == RecordedNodes[RecNo]; 1850} 1851 1852/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1853ALWAYS_INLINE static bool 1854CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1855 SelectionDAGISel &SDISel) { 1856 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1857} 1858 1859/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1860ALWAYS_INLINE static bool 1861CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1862 SelectionDAGISel &SDISel, SDNode *N) { 1863 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1864} 1865 1866ALWAYS_INLINE static bool 1867CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1868 SDNode *N) { 1869 return N->getOpcode() == MatcherTable[MatcherIndex++]; 1870} 1871 1872ALWAYS_INLINE static bool 1873CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1874 SDValue N, const TargetLowering &TLI) { 1875 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1876 if (N.getValueType() == VT) return true; 1877 1878 // Handle the case when VT is iPTR. 1879 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1880} 1881 1882ALWAYS_INLINE static bool 1883CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1884 SDValue N, const TargetLowering &TLI, 1885 unsigned ChildNo) { 1886 if (ChildNo >= N.getNumOperands()) 1887 return false; // Match fails if out of range child #. 1888 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1889} 1890 1891 1892ALWAYS_INLINE static bool 1893CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1894 SDValue N) { 1895 return cast<CondCodeSDNode>(N)->get() == 1896 (ISD::CondCode)MatcherTable[MatcherIndex++]; 1897} 1898 1899ALWAYS_INLINE static bool 1900CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1901 SDValue N, const TargetLowering &TLI) { 1902 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1903 if (cast<VTSDNode>(N)->getVT() == VT) 1904 return true; 1905 1906 // Handle the case when VT is iPTR. 1907 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 1908} 1909 1910ALWAYS_INLINE static bool 1911CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1912 SDValue N) { 1913 int64_t Val = MatcherTable[MatcherIndex++]; 1914 if (Val & 128) 1915 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1916 1917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 1918 return C != 0 && C->getSExtValue() == Val; 1919} 1920 1921ALWAYS_INLINE static bool 1922CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1923 SDValue N, SelectionDAGISel &SDISel) { 1924 int64_t Val = MatcherTable[MatcherIndex++]; 1925 if (Val & 128) 1926 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1927 1928 if (N->getOpcode() != ISD::AND) return false; 1929 1930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1931 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 1932} 1933 1934ALWAYS_INLINE static bool 1935CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1936 SDValue N, SelectionDAGISel &SDISel) { 1937 int64_t Val = MatcherTable[MatcherIndex++]; 1938 if (Val & 128) 1939 Val = GetVBR(Val, MatcherTable, MatcherIndex); 1940 1941 if (N->getOpcode() != ISD::OR) return false; 1942 1943 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 1944 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 1945} 1946 1947/// IsPredicateKnownToFail - If we know how and can do so without pushing a 1948/// scope, evaluate the current node. If the current predicate is known to 1949/// fail, set Result=true and return anything. If the current predicate is 1950/// known to pass, set Result=false and return the MatcherIndex to continue 1951/// with. If the current predicate is unknown, set Result=false and return the 1952/// MatcherIndex to continue with. 1953static unsigned IsPredicateKnownToFail(const unsigned char *Table, 1954 unsigned Index, SDValue N, 1955 bool &Result, SelectionDAGISel &SDISel, 1956 SmallVectorImpl<SDValue> &RecordedNodes){ 1957 switch (Table[Index++]) { 1958 default: 1959 Result = false; 1960 return Index-1; // Could not evaluate this predicate. 1961 case SelectionDAGISel::OPC_CheckSame: 1962 Result = !::CheckSame(Table, Index, N, RecordedNodes); 1963 return Index; 1964 case SelectionDAGISel::OPC_CheckPatternPredicate: 1965 Result = !::CheckPatternPredicate(Table, Index, SDISel); 1966 return Index; 1967 case SelectionDAGISel::OPC_CheckPredicate: 1968 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 1969 return Index; 1970 case SelectionDAGISel::OPC_CheckOpcode: 1971 Result = !::CheckOpcode(Table, Index, N.getNode()); 1972 return Index; 1973 case SelectionDAGISel::OPC_CheckType: 1974 Result = !::CheckType(Table, Index, N, SDISel.TLI); 1975 return Index; 1976 case SelectionDAGISel::OPC_CheckChild0Type: 1977 case SelectionDAGISel::OPC_CheckChild1Type: 1978 case SelectionDAGISel::OPC_CheckChild2Type: 1979 case SelectionDAGISel::OPC_CheckChild3Type: 1980 case SelectionDAGISel::OPC_CheckChild4Type: 1981 case SelectionDAGISel::OPC_CheckChild5Type: 1982 case SelectionDAGISel::OPC_CheckChild6Type: 1983 case SelectionDAGISel::OPC_CheckChild7Type: 1984 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 1985 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 1986 return Index; 1987 case SelectionDAGISel::OPC_CheckCondCode: 1988 Result = !::CheckCondCode(Table, Index, N); 1989 return Index; 1990 case SelectionDAGISel::OPC_CheckValueType: 1991 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 1992 return Index; 1993 case SelectionDAGISel::OPC_CheckInteger: 1994 Result = !::CheckInteger(Table, Index, N); 1995 return Index; 1996 case SelectionDAGISel::OPC_CheckAndImm: 1997 Result = !::CheckAndImm(Table, Index, N, SDISel); 1998 return Index; 1999 case SelectionDAGISel::OPC_CheckOrImm: 2000 Result = !::CheckOrImm(Table, Index, N, SDISel); 2001 return Index; 2002 } 2003} 2004 2005 2006struct MatchScope { 2007 /// FailIndex - If this match fails, this is the index to continue with. 2008 unsigned FailIndex; 2009 2010 /// NodeStack - The node stack when the scope was formed. 2011 SmallVector<SDValue, 4> NodeStack; 2012 2013 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2014 unsigned NumRecordedNodes; 2015 2016 /// NumMatchedMemRefs - The number of matched memref entries. 2017 unsigned NumMatchedMemRefs; 2018 2019 /// InputChain/InputFlag - The current chain/flag 2020 SDValue InputChain, InputFlag; 2021 2022 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2023 bool HasChainNodesMatched, HasFlagResultNodesMatched; 2024}; 2025 2026SDNode *SelectionDAGISel:: 2027SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2028 unsigned TableSize) { 2029 // FIXME: Should these even be selected? Handle these cases in the caller? 2030 switch (NodeToMatch->getOpcode()) { 2031 default: 2032 break; 2033 case ISD::EntryToken: // These nodes remain the same. 2034 case ISD::BasicBlock: 2035 case ISD::Register: 2036 case ISD::HANDLENODE: 2037 case ISD::TargetConstant: 2038 case ISD::TargetConstantFP: 2039 case ISD::TargetConstantPool: 2040 case ISD::TargetFrameIndex: 2041 case ISD::TargetExternalSymbol: 2042 case ISD::TargetBlockAddress: 2043 case ISD::TargetJumpTable: 2044 case ISD::TargetGlobalTLSAddress: 2045 case ISD::TargetGlobalAddress: 2046 case ISD::TokenFactor: 2047 case ISD::CopyFromReg: 2048 case ISD::CopyToReg: 2049 NodeToMatch->setNodeId(-1); // Mark selected. 2050 return 0; 2051 case ISD::AssertSext: 2052 case ISD::AssertZext: 2053 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2054 NodeToMatch->getOperand(0)); 2055 return 0; 2056 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2057 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch); 2058 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2059 } 2060 2061 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2062 2063 // Set up the node stack with NodeToMatch as the only node on the stack. 2064 SmallVector<SDValue, 8> NodeStack; 2065 SDValue N = SDValue(NodeToMatch, 0); 2066 NodeStack.push_back(N); 2067 2068 // MatchScopes - Scopes used when matching, if a match failure happens, this 2069 // indicates where to continue checking. 2070 SmallVector<MatchScope, 8> MatchScopes; 2071 2072 // RecordedNodes - This is the set of nodes that have been recorded by the 2073 // state machine. 2074 SmallVector<SDValue, 8> RecordedNodes; 2075 2076 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2077 // pattern. 2078 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2079 2080 // These are the current input chain and flag for use when generating nodes. 2081 // Various Emit operations change these. For example, emitting a copytoreg 2082 // uses and updates these. 2083 SDValue InputChain, InputFlag; 2084 2085 // ChainNodesMatched - If a pattern matches nodes that have input/output 2086 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2087 // which ones they are. The result is captured into this list so that we can 2088 // update the chain results when the pattern is complete. 2089 SmallVector<SDNode*, 3> ChainNodesMatched; 2090 SmallVector<SDNode*, 3> FlagResultNodesMatched; 2091 2092 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2093 NodeToMatch->dump(CurDAG); 2094 errs() << '\n'); 2095 2096 // Determine where to start the interpreter. Normally we start at opcode #0, 2097 // but if the state machine starts with an OPC_SwitchOpcode, then we 2098 // accelerate the first lookup (which is guaranteed to be hot) with the 2099 // OpcodeOffset table. 2100 unsigned MatcherIndex = 0; 2101 2102 if (!OpcodeOffset.empty()) { 2103 // Already computed the OpcodeOffset table, just index into it. 2104 if (N.getOpcode() < OpcodeOffset.size()) 2105 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2106 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2107 2108 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2109 // Otherwise, the table isn't computed, but the state machine does start 2110 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2111 // is the first time we're selecting an instruction. 2112 unsigned Idx = 1; 2113 while (1) { 2114 // Get the size of this case. 2115 unsigned CaseSize = MatcherTable[Idx++]; 2116 if (CaseSize & 128) 2117 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2118 if (CaseSize == 0) break; 2119 2120 // Get the opcode, add the index to the table. 2121 unsigned Opc = MatcherTable[Idx++]; 2122 if (Opc >= OpcodeOffset.size()) 2123 OpcodeOffset.resize((Opc+1)*2); 2124 OpcodeOffset[Opc] = Idx; 2125 Idx += CaseSize; 2126 } 2127 2128 // Okay, do the lookup for the first opcode. 2129 if (N.getOpcode() < OpcodeOffset.size()) 2130 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2131 } 2132 2133 while (1) { 2134 assert(MatcherIndex < TableSize && "Invalid index"); 2135 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2136 switch (Opcode) { 2137 case OPC_Scope: { 2138 // Okay, the semantics of this operation are that we should push a scope 2139 // then evaluate the first child. However, pushing a scope only to have 2140 // the first check fail (which then pops it) is inefficient. If we can 2141 // determine immediately that the first check (or first several) will 2142 // immediately fail, don't even bother pushing a scope for them. 2143 unsigned FailIndex; 2144 2145 while (1) { 2146 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2147 if (NumToSkip & 128) 2148 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2149 // Found the end of the scope with no match. 2150 if (NumToSkip == 0) { 2151 FailIndex = 0; 2152 break; 2153 } 2154 2155 FailIndex = MatcherIndex+NumToSkip; 2156 2157 // If we can't evaluate this predicate without pushing a scope (e.g. if 2158 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2159 // push the scope and evaluate the full predicate chain. 2160 bool Result; 2161 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2162 Result, *this, RecordedNodes); 2163 if (!Result) 2164 break; 2165 2166 DEBUG(errs() << " Skipped scope entry at index " << MatcherIndex 2167 << " continuing at " << FailIndex << "\n"); 2168 2169 2170 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2171 // move to the next case. 2172 MatcherIndex = FailIndex; 2173 } 2174 2175 // If the whole scope failed to match, bail. 2176 if (FailIndex == 0) break; 2177 2178 // Push a MatchScope which indicates where to go if the first child fails 2179 // to match. 2180 MatchScope NewEntry; 2181 NewEntry.FailIndex = FailIndex; 2182 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2183 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2184 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2185 NewEntry.InputChain = InputChain; 2186 NewEntry.InputFlag = InputFlag; 2187 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2188 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty(); 2189 MatchScopes.push_back(NewEntry); 2190 continue; 2191 } 2192 case OPC_RecordNode: 2193 // Remember this node, it may end up being an operand in the pattern. 2194 RecordedNodes.push_back(N); 2195 continue; 2196 2197 case OPC_RecordChild0: case OPC_RecordChild1: 2198 case OPC_RecordChild2: case OPC_RecordChild3: 2199 case OPC_RecordChild4: case OPC_RecordChild5: 2200 case OPC_RecordChild6: case OPC_RecordChild7: { 2201 unsigned ChildNo = Opcode-OPC_RecordChild0; 2202 if (ChildNo >= N.getNumOperands()) 2203 break; // Match fails if out of range child #. 2204 2205 RecordedNodes.push_back(N->getOperand(ChildNo)); 2206 continue; 2207 } 2208 case OPC_RecordMemRef: 2209 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2210 continue; 2211 2212 case OPC_CaptureFlagInput: 2213 // If the current node has an input flag, capture it in InputFlag. 2214 if (N->getNumOperands() != 0 && 2215 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) 2216 InputFlag = N->getOperand(N->getNumOperands()-1); 2217 continue; 2218 2219 case OPC_MoveChild: { 2220 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2221 if (ChildNo >= N.getNumOperands()) 2222 break; // Match fails if out of range child #. 2223 N = N.getOperand(ChildNo); 2224 NodeStack.push_back(N); 2225 continue; 2226 } 2227 2228 case OPC_MoveParent: 2229 // Pop the current node off the NodeStack. 2230 NodeStack.pop_back(); 2231 assert(!NodeStack.empty() && "Node stack imbalance!"); 2232 N = NodeStack.back(); 2233 continue; 2234 2235 case OPC_CheckSame: 2236 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2237 continue; 2238 case OPC_CheckPatternPredicate: 2239 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2240 continue; 2241 case OPC_CheckPredicate: 2242 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2243 N.getNode())) 2244 break; 2245 continue; 2246 case OPC_CheckComplexPat: { 2247 unsigned CPNum = MatcherTable[MatcherIndex++]; 2248 unsigned RecNo = MatcherTable[MatcherIndex++]; 2249 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2250 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum, 2251 RecordedNodes)) 2252 break; 2253 continue; 2254 } 2255 case OPC_CheckOpcode: 2256 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2257 continue; 2258 2259 case OPC_CheckType: 2260 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2261 continue; 2262 2263 case OPC_SwitchOpcode: { 2264 unsigned CurNodeOpcode = N.getOpcode(); 2265 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2266 unsigned CaseSize; 2267 while (1) { 2268 // Get the size of this case. 2269 CaseSize = MatcherTable[MatcherIndex++]; 2270 if (CaseSize & 128) 2271 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2272 if (CaseSize == 0) break; 2273 2274 // If the opcode matches, then we will execute this case. 2275 if (CurNodeOpcode == MatcherTable[MatcherIndex++]) 2276 break; 2277 2278 // Otherwise, skip over this case. 2279 MatcherIndex += CaseSize; 2280 } 2281 2282 // If no cases matched, bail out. 2283 if (CaseSize == 0) break; 2284 2285 // Otherwise, execute the case we found. 2286 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2287 << " to " << MatcherIndex << "\n"); 2288 continue; 2289 } 2290 2291 case OPC_SwitchType: { 2292 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; 2293 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2294 unsigned CaseSize; 2295 while (1) { 2296 // Get the size of this case. 2297 CaseSize = MatcherTable[MatcherIndex++]; 2298 if (CaseSize & 128) 2299 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2300 if (CaseSize == 0) break; 2301 2302 MVT::SimpleValueType CaseVT = 2303 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2304 if (CaseVT == MVT::iPTR) 2305 CaseVT = TLI.getPointerTy().SimpleTy; 2306 2307 // If the VT matches, then we will execute this case. 2308 if (CurNodeVT == CaseVT) 2309 break; 2310 2311 // Otherwise, skip over this case. 2312 MatcherIndex += CaseSize; 2313 } 2314 2315 // If no cases matched, bail out. 2316 if (CaseSize == 0) break; 2317 2318 // Otherwise, execute the case we found. 2319 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2320 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2321 continue; 2322 } 2323 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2324 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2325 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2326 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2327 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2328 Opcode-OPC_CheckChild0Type)) 2329 break; 2330 continue; 2331 case OPC_CheckCondCode: 2332 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2333 continue; 2334 case OPC_CheckValueType: 2335 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2336 continue; 2337 case OPC_CheckInteger: 2338 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2339 continue; 2340 case OPC_CheckAndImm: 2341 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2342 continue; 2343 case OPC_CheckOrImm: 2344 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2345 continue; 2346 2347 case OPC_CheckFoldableChainNode: { 2348 assert(NodeStack.size() != 1 && "No parent node"); 2349 // Verify that all intermediate nodes between the root and this one have 2350 // a single use. 2351 bool HasMultipleUses = false; 2352 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2353 if (!NodeStack[i].hasOneUse()) { 2354 HasMultipleUses = true; 2355 break; 2356 } 2357 if (HasMultipleUses) break; 2358 2359 // Check to see that the target thinks this is profitable to fold and that 2360 // we can fold it without inducing cycles in the graph. 2361 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2362 NodeToMatch) || 2363 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2364 NodeToMatch, true/*We validate our own chains*/)) 2365 break; 2366 2367 continue; 2368 } 2369 case OPC_EmitInteger: { 2370 MVT::SimpleValueType VT = 2371 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2372 int64_t Val = MatcherTable[MatcherIndex++]; 2373 if (Val & 128) 2374 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2375 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT)); 2376 continue; 2377 } 2378 case OPC_EmitRegister: { 2379 MVT::SimpleValueType VT = 2380 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2381 unsigned RegNo = MatcherTable[MatcherIndex++]; 2382 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT)); 2383 continue; 2384 } 2385 2386 case OPC_EmitConvertToTarget: { 2387 // Convert from IMM/FPIMM to target version. 2388 unsigned RecNo = MatcherTable[MatcherIndex++]; 2389 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2390 SDValue Imm = RecordedNodes[RecNo]; 2391 2392 if (Imm->getOpcode() == ISD::Constant) { 2393 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2394 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2395 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2396 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2397 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2398 } 2399 2400 RecordedNodes.push_back(Imm); 2401 continue; 2402 } 2403 2404 case OPC_EmitMergeInputChains: { 2405 assert(InputChain.getNode() == 0 && 2406 "EmitMergeInputChains should be the first chain producing node"); 2407 // This node gets a list of nodes we matched in the input that have 2408 // chains. We want to token factor all of the input chains to these nodes 2409 // together. However, if any of the input chains is actually one of the 2410 // nodes matched in this pattern, then we have an intra-match reference. 2411 // Ignore these because the newly token factored chain should not refer to 2412 // the old nodes. 2413 unsigned NumChains = MatcherTable[MatcherIndex++]; 2414 assert(NumChains != 0 && "Can't TF zero chains"); 2415 2416 assert(ChainNodesMatched.empty() && 2417 "Should only have one EmitMergeInputChains per match"); 2418 2419 // Read all of the chained nodes. 2420 for (unsigned i = 0; i != NumChains; ++i) { 2421 unsigned RecNo = MatcherTable[MatcherIndex++]; 2422 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2423 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2424 2425 // FIXME: What if other value results of the node have uses not matched 2426 // by this pattern? 2427 if (ChainNodesMatched.back() != NodeToMatch && 2428 !RecordedNodes[RecNo].hasOneUse()) { 2429 ChainNodesMatched.clear(); 2430 break; 2431 } 2432 } 2433 2434 // If the inner loop broke out, the match fails. 2435 if (ChainNodesMatched.empty()) 2436 break; 2437 2438 // Merge the input chains if they are not intra-pattern references. 2439 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2440 2441 if (InputChain.getNode() == 0) 2442 break; // Failed to merge. 2443 2444 continue; 2445 } 2446 2447 case OPC_EmitCopyToReg: { 2448 unsigned RecNo = MatcherTable[MatcherIndex++]; 2449 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2450 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2451 2452 if (InputChain.getNode() == 0) 2453 InputChain = CurDAG->getEntryNode(); 2454 2455 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2456 DestPhysReg, RecordedNodes[RecNo], 2457 InputFlag); 2458 2459 InputFlag = InputChain.getValue(1); 2460 continue; 2461 } 2462 2463 case OPC_EmitNodeXForm: { 2464 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2465 unsigned RecNo = MatcherTable[MatcherIndex++]; 2466 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2467 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo)); 2468 continue; 2469 } 2470 2471 case OPC_EmitNode: 2472 case OPC_MorphNodeTo: { 2473 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2474 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2475 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2476 // Get the result VT list. 2477 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2478 SmallVector<EVT, 4> VTs; 2479 for (unsigned i = 0; i != NumVTs; ++i) { 2480 MVT::SimpleValueType VT = 2481 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2482 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2483 VTs.push_back(VT); 2484 } 2485 2486 if (EmitNodeInfo & OPFL_Chain) 2487 VTs.push_back(MVT::Other); 2488 if (EmitNodeInfo & OPFL_FlagOutput) 2489 VTs.push_back(MVT::Flag); 2490 2491 // This is hot code, so optimize the two most common cases of 1 and 2 2492 // results. 2493 SDVTList VTList; 2494 if (VTs.size() == 1) 2495 VTList = CurDAG->getVTList(VTs[0]); 2496 else if (VTs.size() == 2) 2497 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2498 else 2499 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2500 2501 // Get the operand list. 2502 unsigned NumOps = MatcherTable[MatcherIndex++]; 2503 SmallVector<SDValue, 8> Ops; 2504 for (unsigned i = 0; i != NumOps; ++i) { 2505 unsigned RecNo = MatcherTable[MatcherIndex++]; 2506 if (RecNo & 128) 2507 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2508 2509 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2510 Ops.push_back(RecordedNodes[RecNo]); 2511 } 2512 2513 // If there are variadic operands to add, handle them now. 2514 if (EmitNodeInfo & OPFL_VariadicInfo) { 2515 // Determine the start index to copy from. 2516 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2517 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2518 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2519 "Invalid variadic node"); 2520 // Copy all of the variadic operands, not including a potential flag 2521 // input. 2522 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2523 i != e; ++i) { 2524 SDValue V = NodeToMatch->getOperand(i); 2525 if (V.getValueType() == MVT::Flag) break; 2526 Ops.push_back(V); 2527 } 2528 } 2529 2530 // If this has chain/flag inputs, add them. 2531 if (EmitNodeInfo & OPFL_Chain) 2532 Ops.push_back(InputChain); 2533 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0) 2534 Ops.push_back(InputFlag); 2535 2536 // Create the node. 2537 SDNode *Res = 0; 2538 if (Opcode != OPC_MorphNodeTo) { 2539 // If this is a normal EmitNode command, just create the new node and 2540 // add the results to the RecordedNodes list. 2541 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2542 VTList, Ops.data(), Ops.size()); 2543 2544 // Add all the non-flag/non-chain results to the RecordedNodes list. 2545 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2546 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break; 2547 RecordedNodes.push_back(SDValue(Res, i)); 2548 } 2549 2550 } else { 2551 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2552 EmitNodeInfo); 2553 } 2554 2555 // If the node had chain/flag results, update our notion of the current 2556 // chain and flag. 2557 if (EmitNodeInfo & OPFL_FlagOutput) { 2558 InputFlag = SDValue(Res, VTs.size()-1); 2559 if (EmitNodeInfo & OPFL_Chain) 2560 InputChain = SDValue(Res, VTs.size()-2); 2561 } else if (EmitNodeInfo & OPFL_Chain) 2562 InputChain = SDValue(Res, VTs.size()-1); 2563 2564 // If the OPFL_MemRefs flag is set on this node, slap all of the 2565 // accumulated memrefs onto it. 2566 // 2567 // FIXME: This is vastly incorrect for patterns with multiple outputs 2568 // instructions that access memory and for ComplexPatterns that match 2569 // loads. 2570 if (EmitNodeInfo & OPFL_MemRefs) { 2571 MachineSDNode::mmo_iterator MemRefs = 2572 MF->allocateMemRefsArray(MatchedMemRefs.size()); 2573 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs); 2574 cast<MachineSDNode>(Res) 2575 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size()); 2576 } 2577 2578 DEBUG(errs() << " " 2579 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2580 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2581 2582 // If this was a MorphNodeTo then we're completely done! 2583 if (Opcode == OPC_MorphNodeTo) { 2584 // Update chain and flag uses. 2585 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2586 InputFlag, FlagResultNodesMatched, true); 2587 return Res; 2588 } 2589 2590 continue; 2591 } 2592 2593 case OPC_MarkFlagResults: { 2594 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2595 2596 // Read and remember all the flag-result nodes. 2597 for (unsigned i = 0; i != NumNodes; ++i) { 2598 unsigned RecNo = MatcherTable[MatcherIndex++]; 2599 if (RecNo & 128) 2600 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2601 2602 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2603 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode()); 2604 } 2605 continue; 2606 } 2607 2608 case OPC_CompleteMatch: { 2609 // The match has been completed, and any new nodes (if any) have been 2610 // created. Patch up references to the matched dag to use the newly 2611 // created nodes. 2612 unsigned NumResults = MatcherTable[MatcherIndex++]; 2613 2614 for (unsigned i = 0; i != NumResults; ++i) { 2615 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2616 if (ResSlot & 128) 2617 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2618 2619 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2620 SDValue Res = RecordedNodes[ResSlot]; 2621 2622 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program 2623 // after (parallel) on input patterns are removed. This would also 2624 // allow us to stop encoding #results in OPC_CompleteMatch's table 2625 // entry. 2626 if (NodeToMatch->getNumValues() <= i || 2627 NodeToMatch->getValueType(i) == MVT::Other || 2628 NodeToMatch->getValueType(i) == MVT::Flag) 2629 break; 2630 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2631 NodeToMatch->getValueType(i) == MVT::iPTR || 2632 Res.getValueType() == MVT::iPTR || 2633 NodeToMatch->getValueType(i).getSizeInBits() == 2634 Res.getValueType().getSizeInBits()) && 2635 "invalid replacement"); 2636 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2637 } 2638 2639 // If the root node defines a flag, add it to the flag nodes to update 2640 // list. 2641 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag) 2642 FlagResultNodesMatched.push_back(NodeToMatch); 2643 2644 // Update chain and flag uses. 2645 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched, 2646 InputFlag, FlagResultNodesMatched, false); 2647 2648 assert(NodeToMatch->use_empty() && 2649 "Didn't replace all uses of the node?"); 2650 2651 // FIXME: We just return here, which interacts correctly with SelectRoot 2652 // above. We should fix this to not return an SDNode* anymore. 2653 return 0; 2654 } 2655 } 2656 2657 // If the code reached this point, then the match failed. See if there is 2658 // another child to try in the current 'Scope', otherwise pop it until we 2659 // find a case to check. 2660 while (1) { 2661 if (MatchScopes.empty()) { 2662 CannotYetSelect(NodeToMatch); 2663 return 0; 2664 } 2665 2666 // Restore the interpreter state back to the point where the scope was 2667 // formed. 2668 MatchScope &LastScope = MatchScopes.back(); 2669 RecordedNodes.resize(LastScope.NumRecordedNodes); 2670 NodeStack.clear(); 2671 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2672 N = NodeStack.back(); 2673 2674 DEBUG(errs() << " Match failed at index " << MatcherIndex 2675 << " continuing at " << LastScope.FailIndex << "\n"); 2676 2677 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2678 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2679 MatcherIndex = LastScope.FailIndex; 2680 2681 InputChain = LastScope.InputChain; 2682 InputFlag = LastScope.InputFlag; 2683 if (!LastScope.HasChainNodesMatched) 2684 ChainNodesMatched.clear(); 2685 if (!LastScope.HasFlagResultNodesMatched) 2686 FlagResultNodesMatched.clear(); 2687 2688 // Check to see what the offset is at the new MatcherIndex. If it is zero 2689 // we have reached the end of this scope, otherwise we have another child 2690 // in the current scope to try. 2691 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2692 if (NumToSkip & 128) 2693 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2694 2695 // If we have another child in this scope to match, update FailIndex and 2696 // try it. 2697 if (NumToSkip != 0) { 2698 LastScope.FailIndex = MatcherIndex+NumToSkip; 2699 break; 2700 } 2701 2702 // End of this scope, pop it and try the next child in the containing 2703 // scope. 2704 MatchScopes.pop_back(); 2705 } 2706 } 2707} 2708 2709 2710 2711void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2712 std::string msg; 2713 raw_string_ostream Msg(msg); 2714 Msg << "Cannot yet select: "; 2715 2716 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2717 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2718 N->getOpcode() != ISD::INTRINSIC_VOID) { 2719 N->printrFull(Msg, CurDAG); 2720 } else { 2721 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2722 unsigned iid = 2723 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2724 if (iid < Intrinsic::num_intrinsics) 2725 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2726 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2727 Msg << "target intrinsic %" << TII->getName(iid); 2728 else 2729 Msg << "unknown intrinsic #" << iid; 2730 } 2731 llvm_report_error(Msg.str()); 2732} 2733 2734char SelectionDAGISel::ID = 0; 2735