SelectionDAGISel.cpp revision 9f87788040786b1bc6530763e4cf7e105bfb2924
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/Analysis/AliasAnalysis.h" 16#include "llvm/CodeGen/SelectionDAGISel.h" 17#include "llvm/CodeGen/ScheduleDAG.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Constants.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/GlobalVariable.h" 23#include "llvm/InlineAsm.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/MachineDebugInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/SchedulerRegistry.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/CodeGen/SSARegMap.h" 35#include "llvm/Target/MRegisterInfo.h" 36#include "llvm/Target/TargetAsmInfo.h" 37#include "llvm/Target/TargetData.h" 38#include "llvm/Target/TargetFrameInfo.h" 39#include "llvm/Target/TargetInstrInfo.h" 40#include "llvm/Target/TargetLowering.h" 41#include "llvm/Target/TargetMachine.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/Transforms/Utils/BasicBlockUtils.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/Compiler.h" 47#include <algorithm> 48using namespace llvm; 49 50#ifndef NDEBUG 51static cl::opt<bool> 52ViewISelDAGs("view-isel-dags", cl::Hidden, 53 cl::desc("Pop up a window to show isel dags as they are selected")); 54static cl::opt<bool> 55ViewSchedDAGs("view-sched-dags", cl::Hidden, 56 cl::desc("Pop up a window to show sched dags as they are processed")); 57#else 58static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0; 59#endif 60 61 62//===---------------------------------------------------------------------===// 63/// 64/// RegisterScheduler class - Track the registration of instruction schedulers. 65/// 66//===---------------------------------------------------------------------===// 67MachinePassRegistry RegisterScheduler::Registry; 68 69//===---------------------------------------------------------------------===// 70/// 71/// ISHeuristic command line option for instruction schedulers. 72/// 73//===---------------------------------------------------------------------===// 74namespace { 75 cl::opt<RegisterScheduler::FunctionPassCtor, false, 76 RegisterPassParser<RegisterScheduler> > 77 ISHeuristic("sched", 78 cl::init(&createDefaultScheduler), 79 cl::desc("Instruction schedulers available:")); 80 81 static RegisterScheduler 82 defaultListDAGScheduler("default", " Best scheduler for the target", 83 createDefaultScheduler); 84} // namespace 85 86namespace { 87 /// RegsForValue - This struct represents the physical registers that a 88 /// particular value is assigned and the type information about the value. 89 /// This is needed because values can be promoted into larger registers and 90 /// expanded into multiple smaller registers than the value. 91 struct VISIBILITY_HIDDEN RegsForValue { 92 /// Regs - This list hold the register (for legal and promoted values) 93 /// or register set (for expanded values) that the value should be assigned 94 /// to. 95 std::vector<unsigned> Regs; 96 97 /// RegVT - The value type of each register. 98 /// 99 MVT::ValueType RegVT; 100 101 /// ValueVT - The value type of the LLVM value, which may be promoted from 102 /// RegVT or made from merging the two expanded parts. 103 MVT::ValueType ValueVT; 104 105 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {} 106 107 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) 108 : RegVT(regvt), ValueVT(valuevt) { 109 Regs.push_back(Reg); 110 } 111 RegsForValue(const std::vector<unsigned> ®s, 112 MVT::ValueType regvt, MVT::ValueType valuevt) 113 : Regs(regs), RegVT(regvt), ValueVT(valuevt) { 114 } 115 116 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 117 /// this value and returns the result as a ValueVT value. This uses 118 /// Chain/Flag as the input and updates them for the output Chain/Flag. 119 SDOperand getCopyFromRegs(SelectionDAG &DAG, 120 SDOperand &Chain, SDOperand &Flag) const; 121 122 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 123 /// specified value into the registers specified by this object. This uses 124 /// Chain/Flag as the input and updates them for the output Chain/Flag. 125 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 126 SDOperand &Chain, SDOperand &Flag, 127 MVT::ValueType PtrVT) const; 128 129 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 130 /// operand list. This adds the code marker and includes the number of 131 /// values added into it. 132 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 133 std::vector<SDOperand> &Ops) const; 134 }; 135} 136 137namespace llvm { 138 //===--------------------------------------------------------------------===// 139 /// createDefaultScheduler - This creates an instruction scheduler appropriate 140 /// for the target. 141 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 142 SelectionDAG *DAG, 143 MachineBasicBlock *BB) { 144 TargetLowering &TLI = IS->getTargetLowering(); 145 146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { 147 return createTDListDAGScheduler(IS, DAG, BB); 148 } else { 149 assert(TLI.getSchedulingPreference() == 150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); 151 return createBURRListDAGScheduler(IS, DAG, BB); 152 } 153 } 154 155 156 //===--------------------------------------------------------------------===// 157 /// FunctionLoweringInfo - This contains information that is global to a 158 /// function that is used when lowering a region of the function. 159 class FunctionLoweringInfo { 160 public: 161 TargetLowering &TLI; 162 Function &Fn; 163 MachineFunction &MF; 164 SSARegMap *RegMap; 165 166 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); 167 168 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 169 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 170 171 /// ValueMap - Since we emit code for the function a basic block at a time, 172 /// we must remember which virtual registers hold the values for 173 /// cross-basic-block values. 174 std::map<const Value*, unsigned> ValueMap; 175 176 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 177 /// the entry block. This allows the allocas to be efficiently referenced 178 /// anywhere in the function. 179 std::map<const AllocaInst*, int> StaticAllocaMap; 180 181 unsigned MakeReg(MVT::ValueType VT) { 182 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 183 } 184 185 /// isExportedInst - Return true if the specified value is an instruction 186 /// exported from its block. 187 bool isExportedInst(const Value *V) { 188 return ValueMap.count(V); 189 } 190 191 unsigned CreateRegForValue(const Value *V); 192 193 unsigned InitializeRegForValue(const Value *V) { 194 unsigned &R = ValueMap[V]; 195 assert(R == 0 && "Already initialized this value register!"); 196 return R = CreateRegForValue(V); 197 } 198 }; 199} 200 201/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 202/// PHI nodes or outside of the basic block that defines it, or used by a 203/// switch instruction, which may expand to multiple basic blocks. 204static bool isUsedOutsideOfDefiningBlock(Instruction *I) { 205 if (isa<PHINode>(I)) return true; 206 BasicBlock *BB = I->getParent(); 207 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) 208 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) || 209 // FIXME: Remove switchinst special case. 210 isa<SwitchInst>(*UI)) 211 return true; 212 return false; 213} 214 215/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 216/// entry block, return true. This includes arguments used by switches, since 217/// the switch may expand into multiple basic blocks. 218static bool isOnlyUsedInEntryBlock(Argument *A) { 219 BasicBlock *Entry = A->getParent()->begin(); 220 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) 221 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI)) 222 return false; // Use not in entry block. 223 return true; 224} 225 226FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, 227 Function &fn, MachineFunction &mf) 228 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { 229 230 // Create a vreg for each argument register that is not dead and is used 231 // outside of the entry block for the function. 232 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); 233 AI != E; ++AI) 234 if (!isOnlyUsedInEntryBlock(AI)) 235 InitializeRegForValue(AI); 236 237 // Initialize the mapping of values to registers. This is only set up for 238 // instruction values that are used outside of the block that defines 239 // them. 240 Function::iterator BB = Fn.begin(), EB = Fn.end(); 241 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 242 if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) 243 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) { 244 const Type *Ty = AI->getAllocatedType(); 245 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 246 unsigned Align = 247 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 248 AI->getAlignment()); 249 250 // If the alignment of the value is smaller than the size of the 251 // value, and if the size of the value is particularly small 252 // (<= 8 bytes), round up to the size of the value for potentially 253 // better performance. 254 // 255 // FIXME: This could be made better with a preferred alignment hook in 256 // TargetData. It serves primarily to 8-byte align doubles for X86. 257 if (Align < TySize && TySize <= 8) Align = TySize; 258 TySize *= CUI->getZExtValue(); // Get total allocated size. 259 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 260 StaticAllocaMap[AI] = 261 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 262 } 263 264 for (; BB != EB; ++BB) 265 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) 266 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I)) 267 if (!isa<AllocaInst>(I) || 268 !StaticAllocaMap.count(cast<AllocaInst>(I))) 269 InitializeRegForValue(I); 270 271 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 272 // also creates the initial PHI MachineInstrs, though none of the input 273 // operands are populated. 274 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { 275 MachineBasicBlock *MBB = new MachineBasicBlock(BB); 276 MBBMap[BB] = MBB; 277 MF.getBasicBlockList().push_back(MBB); 278 279 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 280 // appropriate. 281 PHINode *PN; 282 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ 283 if (PN->use_empty()) continue; 284 285 MVT::ValueType VT = TLI.getValueType(PN->getType()); 286 unsigned NumElements; 287 if (VT != MVT::Vector) 288 NumElements = TLI.getNumElements(VT); 289 else { 290 MVT::ValueType VT1,VT2; 291 NumElements = 292 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 293 VT1, VT2); 294 } 295 unsigned PHIReg = ValueMap[PN]; 296 assert(PHIReg && "PHI node does not have an assigned virtual register!"); 297 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); 298 for (unsigned i = 0; i != NumElements; ++i) 299 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); 300 } 301 } 302} 303 304/// CreateRegForValue - Allocate the appropriate number of virtual registers of 305/// the correctly promoted or expanded types. Assign these registers 306/// consecutive vreg numbers and return the first assigned number. 307unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { 308 MVT::ValueType VT = TLI.getValueType(V->getType()); 309 310 // The number of multiples of registers that we need, to, e.g., split up 311 // a <2 x int64> -> 4 x i32 registers. 312 unsigned NumVectorRegs = 1; 313 314 // If this is a packed type, figure out what type it will decompose into 315 // and how many of the elements it will use. 316 if (VT == MVT::Vector) { 317 const PackedType *PTy = cast<PackedType>(V->getType()); 318 unsigned NumElts = PTy->getNumElements(); 319 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); 320 321 // Divide the input until we get to a supported size. This will always 322 // end with a scalar if the target doesn't support vectors. 323 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { 324 NumElts >>= 1; 325 NumVectorRegs <<= 1; 326 } 327 if (NumElts == 1) 328 VT = EltTy; 329 else 330 VT = getVectorType(EltTy, NumElts); 331 } 332 333 // The common case is that we will only create one register for this 334 // value. If we have that case, create and return the virtual register. 335 unsigned NV = TLI.getNumElements(VT); 336 if (NV == 1) { 337 // If we are promoting this value, pick the next largest supported type. 338 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); 339 unsigned Reg = MakeReg(PromotedType); 340 // If this is a vector of supported or promoted types (e.g. 4 x i16), 341 // create all of the registers. 342 for (unsigned i = 1; i != NumVectorRegs; ++i) 343 MakeReg(PromotedType); 344 return Reg; 345 } 346 347 // If this value is represented with multiple target registers, make sure 348 // to create enough consecutive registers of the right (smaller) type. 349 VT = TLI.getTypeToExpandTo(VT); 350 unsigned R = MakeReg(VT); 351 for (unsigned i = 1; i != NV*NumVectorRegs; ++i) 352 MakeReg(VT); 353 return R; 354} 355 356//===----------------------------------------------------------------------===// 357/// SelectionDAGLowering - This is the common target-independent lowering 358/// implementation that is parameterized by a TargetLowering object. 359/// Also, targets can overload any lowering method. 360/// 361namespace llvm { 362class SelectionDAGLowering { 363 MachineBasicBlock *CurMBB; 364 365 std::map<const Value*, SDOperand> NodeMap; 366 367 /// PendingLoads - Loads are not emitted to the program immediately. We bunch 368 /// them up and then emit token factor nodes when possible. This allows us to 369 /// get simple disambiguation between loads without worrying about alias 370 /// analysis. 371 std::vector<SDOperand> PendingLoads; 372 373 /// Case - A pair of values to record the Value for a switch case, and the 374 /// case's target basic block. 375 typedef std::pair<Constant*, MachineBasicBlock*> Case; 376 typedef std::vector<Case>::iterator CaseItr; 377 typedef std::pair<CaseItr, CaseItr> CaseRange; 378 379 /// CaseRec - A struct with ctor used in lowering switches to a binary tree 380 /// of conditional branches. 381 struct CaseRec { 382 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) : 383 CaseBB(bb), LT(lt), GE(ge), Range(r) {} 384 385 /// CaseBB - The MBB in which to emit the compare and branch 386 MachineBasicBlock *CaseBB; 387 /// LT, GE - If nonzero, we know the current case value must be less-than or 388 /// greater-than-or-equal-to these Constants. 389 Constant *LT; 390 Constant *GE; 391 /// Range - A pair of iterators representing the range of case values to be 392 /// processed at this point in the binary search tree. 393 CaseRange Range; 394 }; 395 396 /// The comparison function for sorting Case values. 397 struct CaseCmp { 398 bool operator () (const Case& C1, const Case& C2) { 399 if (const ConstantInt* I1 = dyn_cast<const ConstantInt>(C1.first)) 400 if (I1->getType()->isUnsigned()) 401 return I1->getZExtValue() < 402 cast<const ConstantInt>(C2.first)->getZExtValue(); 403 404 return cast<const ConstantInt>(C1.first)->getSExtValue() < 405 cast<const ConstantInt>(C2.first)->getSExtValue(); 406 } 407 }; 408 409public: 410 // TLI - This is information that describes the available target features we 411 // need for lowering. This indicates when operations are unavailable, 412 // implemented with a libcall, etc. 413 TargetLowering &TLI; 414 SelectionDAG &DAG; 415 const TargetData *TD; 416 417 /// SwitchCases - Vector of CaseBlock structures used to communicate 418 /// SwitchInst code generation information. 419 std::vector<SelectionDAGISel::CaseBlock> SwitchCases; 420 SelectionDAGISel::JumpTable JT; 421 422 /// FuncInfo - Information about the function as a whole. 423 /// 424 FunctionLoweringInfo &FuncInfo; 425 426 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, 427 FunctionLoweringInfo &funcinfo) 428 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), 429 JT(0,0,0,0), FuncInfo(funcinfo) { 430 } 431 432 /// getRoot - Return the current virtual root of the Selection DAG. 433 /// 434 SDOperand getRoot() { 435 if (PendingLoads.empty()) 436 return DAG.getRoot(); 437 438 if (PendingLoads.size() == 1) { 439 SDOperand Root = PendingLoads[0]; 440 DAG.setRoot(Root); 441 PendingLoads.clear(); 442 return Root; 443 } 444 445 // Otherwise, we have to make a token factor node. 446 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 447 &PendingLoads[0], PendingLoads.size()); 448 PendingLoads.clear(); 449 DAG.setRoot(Root); 450 return Root; 451 } 452 453 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg); 454 455 void visit(Instruction &I) { visit(I.getOpcode(), I); } 456 457 void visit(unsigned Opcode, User &I) { 458 // Note: this doesn't use InstVisitor, because it has to work with 459 // ConstantExpr's in addition to instructions. 460 switch (Opcode) { 461 default: assert(0 && "Unknown instruction type encountered!"); 462 abort(); 463 // Build the switch statement using the Instruction.def file. 464#define HANDLE_INST(NUM, OPCODE, CLASS) \ 465 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); 466#include "llvm/Instruction.def" 467 } 468 } 469 470 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } 471 472 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, 473 const Value *SV, SDOperand Root, 474 bool isVolatile); 475 476 SDOperand getIntPtrConstant(uint64_t Val) { 477 return DAG.getConstant(Val, TLI.getPointerTy()); 478 } 479 480 SDOperand getValue(const Value *V); 481 482 const SDOperand &setValue(const Value *V, SDOperand NewN) { 483 SDOperand &N = NodeMap[V]; 484 assert(N.Val == 0 && "Already set a value for this node!"); 485 return N = NewN; 486 } 487 488 RegsForValue GetRegistersForValue(const std::string &ConstrCode, 489 MVT::ValueType VT, 490 bool OutReg, bool InReg, 491 std::set<unsigned> &OutputRegs, 492 std::set<unsigned> &InputRegs); 493 494 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, 495 MachineBasicBlock *FBB, MachineBasicBlock *CurBB, 496 unsigned Opc); 497 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB); 498 void ExportFromCurrentBlock(Value *V); 499 500 // Terminator instructions. 501 void visitRet(ReturnInst &I); 502 void visitBr(BranchInst &I); 503 void visitSwitch(SwitchInst &I); 504 void visitUnreachable(UnreachableInst &I) { /* noop */ } 505 506 // Helper for visitSwitch 507 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB); 508 void visitJumpTable(SelectionDAGISel::JumpTable &JT); 509 510 // These all get lowered before this pass. 511 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); } 512 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); } 513 514 void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp); 515 void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp); 516 void visitShift(User &I, unsigned Opcode); 517 void visitAdd(User &I) { 518 if (I.getType()->isFloatingPoint()) 519 visitFPBinary(I, ISD::FADD, ISD::VADD); 520 else 521 visitIntBinary(I, ISD::ADD, ISD::VADD); 522 } 523 void visitSub(User &I); 524 void visitMul(User &I) { 525 if (I.getType()->isFloatingPoint()) 526 visitFPBinary(I, ISD::FMUL, ISD::VMUL); 527 else 528 visitIntBinary(I, ISD::MUL, ISD::VMUL); 529 } 530 void visitURem(User &I) { visitIntBinary(I, ISD::UREM, 0); } 531 void visitSRem(User &I) { visitIntBinary(I, ISD::SREM, 0); } 532 void visitFRem(User &I) { visitFPBinary (I, ISD::FREM, 0); } 533 void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); } 534 void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); } 535 void visitFDiv(User &I) { visitFPBinary (I, ISD::FDIV, ISD::VSDIV); } 536 void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); } 537 void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); } 538 void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); } 539 void visitShl(User &I) { visitShift(I, ISD::SHL); } 540 void visitLShr(User &I) { visitShift(I, ISD::SRL); } 541 void visitAShr(User &I) { visitShift(I, ISD::SRA); } 542 void visitICmp(User &I); 543 void visitFCmp(User &I); 544 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc, 545 ISD::CondCode FPOpc); 546 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ, 547 ISD::SETOEQ); } 548 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE, 549 ISD::SETUNE); } 550 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE, 551 ISD::SETOLE); } 552 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE, 553 ISD::SETOGE); } 554 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT, 555 ISD::SETOLT); } 556 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT, 557 ISD::SETOGT); } 558 // Visit the conversion instructions 559 void visitTrunc(User &I); 560 void visitZExt(User &I); 561 void visitSExt(User &I); 562 void visitFPTrunc(User &I); 563 void visitFPExt(User &I); 564 void visitFPToUI(User &I); 565 void visitFPToSI(User &I); 566 void visitUIToFP(User &I); 567 void visitSIToFP(User &I); 568 void visitPtrToInt(User &I); 569 void visitIntToPtr(User &I); 570 void visitBitCast(User &I); 571 572 void visitExtractElement(User &I); 573 void visitInsertElement(User &I); 574 void visitShuffleVector(User &I); 575 576 void visitGetElementPtr(User &I); 577 void visitSelect(User &I); 578 579 void visitMalloc(MallocInst &I); 580 void visitFree(FreeInst &I); 581 void visitAlloca(AllocaInst &I); 582 void visitLoad(LoadInst &I); 583 void visitStore(StoreInst &I); 584 void visitPHI(PHINode &I) { } // PHI nodes are handled specially. 585 void visitCall(CallInst &I); 586 void visitInlineAsm(CallInst &I); 587 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic); 588 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic); 589 590 void visitVAStart(CallInst &I); 591 void visitVAArg(VAArgInst &I); 592 void visitVAEnd(CallInst &I); 593 void visitVACopy(CallInst &I); 594 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress); 595 596 void visitMemIntrinsic(CallInst &I, unsigned Op); 597 598 void visitUserOp1(Instruction &I) { 599 assert(0 && "UserOp1 should not exist at instruction selection time!"); 600 abort(); 601 } 602 void visitUserOp2(Instruction &I) { 603 assert(0 && "UserOp2 should not exist at instruction selection time!"); 604 abort(); 605 } 606}; 607} // end namespace llvm 608 609SDOperand SelectionDAGLowering::getValue(const Value *V) { 610 SDOperand &N = NodeMap[V]; 611 if (N.Val) return N; 612 613 const Type *VTy = V->getType(); 614 MVT::ValueType VT = TLI.getValueType(VTy); 615 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { 616 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 617 visit(CE->getOpcode(), *CE); 618 assert(N.Val && "visit didn't populate the ValueMap!"); 619 return N; 620 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) { 621 return N = DAG.getGlobalAddress(GV, VT); 622 } else if (isa<ConstantPointerNull>(C)) { 623 return N = DAG.getConstant(0, TLI.getPointerTy()); 624 } else if (isa<UndefValue>(C)) { 625 if (!isa<PackedType>(VTy)) 626 return N = DAG.getNode(ISD::UNDEF, VT); 627 628 // Create a VBUILD_VECTOR of undef nodes. 629 const PackedType *PTy = cast<PackedType>(VTy); 630 unsigned NumElements = PTy->getNumElements(); 631 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 632 633 SmallVector<SDOperand, 8> Ops; 634 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT)); 635 636 // Create a VConstant node with generic Vector type. 637 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 638 Ops.push_back(DAG.getValueType(PVT)); 639 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 640 &Ops[0], Ops.size()); 641 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 642 return N = DAG.getConstantFP(CFP->getValue(), VT); 643 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) { 644 unsigned NumElements = PTy->getNumElements(); 645 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 646 647 // Now that we know the number and type of the elements, push a 648 // Constant or ConstantFP node onto the ops list for each element of 649 // the packed constant. 650 SmallVector<SDOperand, 8> Ops; 651 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) { 652 for (unsigned i = 0; i != NumElements; ++i) 653 Ops.push_back(getValue(CP->getOperand(i))); 654 } else { 655 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!"); 656 SDOperand Op; 657 if (MVT::isFloatingPoint(PVT)) 658 Op = DAG.getConstantFP(0, PVT); 659 else 660 Op = DAG.getConstant(0, PVT); 661 Ops.assign(NumElements, Op); 662 } 663 664 // Create a VBUILD_VECTOR node with generic Vector type. 665 Ops.push_back(DAG.getConstant(NumElements, MVT::i32)); 666 Ops.push_back(DAG.getValueType(PVT)); 667 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size()); 668 } else { 669 // Canonicalize all constant ints to be unsigned. 670 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getZExtValue(),VT); 671 } 672 } 673 674 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 675 std::map<const AllocaInst*, int>::iterator SI = 676 FuncInfo.StaticAllocaMap.find(AI); 677 if (SI != FuncInfo.StaticAllocaMap.end()) 678 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 679 } 680 681 std::map<const Value*, unsigned>::const_iterator VMI = 682 FuncInfo.ValueMap.find(V); 683 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); 684 685 unsigned InReg = VMI->second; 686 687 // If this type is not legal, make it so now. 688 if (VT != MVT::Vector) { 689 if (TLI.getTypeAction(VT) == TargetLowering::Expand) { 690 // Source must be expanded. This input value is actually coming from the 691 // register pair VMI->second and VMI->second+1. 692 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT); 693 unsigned NumVals = TLI.getNumElements(VT); 694 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 695 if (NumVals == 1) 696 N = DAG.getNode(ISD::BIT_CONVERT, VT, N); 697 else { 698 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 699 N = DAG.getNode(ISD::BUILD_PAIR, VT, N, 700 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); 701 } 702 } else { 703 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); 704 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); 705 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case 706 N = MVT::isFloatingPoint(VT) 707 ? DAG.getNode(ISD::FP_ROUND, VT, N) 708 : DAG.getNode(ISD::TRUNCATE, VT, N); 709 } 710 } else { 711 // Otherwise, if this is a vector, make it available as a generic vector 712 // here. 713 MVT::ValueType PTyElementVT, PTyLegalElementVT; 714 const PackedType *PTy = cast<PackedType>(VTy); 715 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT, 716 PTyLegalElementVT); 717 718 // Build a VBUILD_VECTOR with the input registers. 719 SmallVector<SDOperand, 8> Ops; 720 if (PTyElementVT == PTyLegalElementVT) { 721 // If the value types are legal, just VBUILD the CopyFromReg nodes. 722 for (unsigned i = 0; i != NE; ++i) 723 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 724 PTyElementVT)); 725 } else if (PTyElementVT < PTyLegalElementVT) { 726 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate. 727 for (unsigned i = 0; i != NE; ++i) { 728 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 729 PTyElementVT); 730 if (MVT::isFloatingPoint(PTyElementVT)) 731 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); 732 else 733 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op); 734 Ops.push_back(Op); 735 } 736 } else { 737 // If the register was expanded, use BUILD_PAIR. 738 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); 739 for (unsigned i = 0; i != NE/2; ++i) { 740 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 741 PTyElementVT); 742 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 743 PTyElementVT); 744 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); 745 } 746 } 747 748 Ops.push_back(DAG.getConstant(NE, MVT::i32)); 749 Ops.push_back(DAG.getValueType(PTyLegalElementVT)); 750 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 751 752 // Finally, use a VBIT_CONVERT to make this available as the appropriate 753 // vector type. 754 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 755 DAG.getConstant(PTy->getNumElements(), 756 MVT::i32), 757 DAG.getValueType(TLI.getValueType(PTy->getElementType()))); 758 } 759 760 return N; 761} 762 763 764void SelectionDAGLowering::visitRet(ReturnInst &I) { 765 if (I.getNumOperands() == 0) { 766 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); 767 return; 768 } 769 SmallVector<SDOperand, 8> NewValues; 770 NewValues.push_back(getRoot()); 771 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 772 SDOperand RetOp = getValue(I.getOperand(i)); 773 bool isSigned = I.getOperand(i)->getType()->isSigned(); 774 775 // If this is an integer return value, we need to promote it ourselves to 776 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather 777 // than sign/zero. 778 // FIXME: C calling convention requires the return type to be promoted to 779 // at least 32-bit. But this is not necessary for non-C calling conventions. 780 if (MVT::isInteger(RetOp.getValueType()) && 781 RetOp.getValueType() < MVT::i64) { 782 MVT::ValueType TmpVT; 783 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) 784 TmpVT = TLI.getTypeToTransformTo(MVT::i32); 785 else 786 TmpVT = MVT::i32; 787 788 if (isSigned) 789 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp); 790 else 791 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp); 792 } 793 NewValues.push_back(RetOp); 794 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32)); 795 } 796 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, 797 &NewValues[0], NewValues.size())); 798} 799 800/// ExportFromCurrentBlock - If this condition isn't known to be exported from 801/// the current basic block, add it to ValueMap now so that we'll get a 802/// CopyTo/FromReg. 803void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { 804 // No need to export constants. 805 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 806 807 // Already exported? 808 if (FuncInfo.isExportedInst(V)) return; 809 810 unsigned Reg = FuncInfo.InitializeRegForValue(V); 811 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg)); 812} 813 814bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, 815 const BasicBlock *FromBB) { 816 // The operands of the setcc have to be in this block. We don't know 817 // how to export them from some other block. 818 if (Instruction *VI = dyn_cast<Instruction>(V)) { 819 // Can export from current BB. 820 if (VI->getParent() == FromBB) 821 return true; 822 823 // Is already exported, noop. 824 return FuncInfo.isExportedInst(V); 825 } 826 827 // If this is an argument, we can export it if the BB is the entry block or 828 // if it is already exported. 829 if (isa<Argument>(V)) { 830 if (FromBB == &FromBB->getParent()->getEntryBlock()) 831 return true; 832 833 // Otherwise, can only export this if it is already exported. 834 return FuncInfo.isExportedInst(V); 835 } 836 837 // Otherwise, constants can always be exported. 838 return true; 839} 840 841static bool InBlock(const Value *V, const BasicBlock *BB) { 842 if (const Instruction *I = dyn_cast<Instruction>(V)) 843 return I->getParent() == BB; 844 return true; 845} 846 847/// FindMergedConditions - If Cond is an expression like 848void SelectionDAGLowering::FindMergedConditions(Value *Cond, 849 MachineBasicBlock *TBB, 850 MachineBasicBlock *FBB, 851 MachineBasicBlock *CurBB, 852 unsigned Opc) { 853 // If this node is not part of the or/and tree, emit it as a branch. 854 BinaryOperator *BOp = dyn_cast<BinaryOperator>(Cond); 855 856 if (!BOp || (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 857 BOp->getParent() != CurBB->getBasicBlock() || 858 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 859 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 860 const BasicBlock *BB = CurBB->getBasicBlock(); 861 862 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond)) 863 if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 || 864 II->getIntrinsicID() == Intrinsic::isunordered_f64) && 865 // The operands of the setcc have to be in this block. We don't know 866 // how to export them from some other block. If this is the first 867 // block of the sequence, no exporting is needed. 868 (CurBB == CurMBB || 869 (isExportableFromCurrentBlock(II->getOperand(1), BB) && 870 isExportableFromCurrentBlock(II->getOperand(2), BB)))) { 871 SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1), 872 II->getOperand(2), TBB, FBB, CurBB); 873 SwitchCases.push_back(CB); 874 return; 875 } 876 877 878 // If the leaf of the tree is a setcond inst, merge the condition into the 879 // caseblock. 880 if (BOp && isa<SetCondInst>(BOp) && 881 // The operands of the setcc have to be in this block. We don't know 882 // how to export them from some other block. If this is the first block 883 // of the sequence, no exporting is needed. 884 (CurBB == CurMBB || 885 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 886 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) { 887 ISD::CondCode SignCond, UnsCond, FPCond, Condition; 888 switch (BOp->getOpcode()) { 889 default: assert(0 && "Unknown setcc opcode!"); 890 case Instruction::SetEQ: 891 SignCond = ISD::SETEQ; 892 UnsCond = ISD::SETEQ; 893 FPCond = ISD::SETOEQ; 894 break; 895 case Instruction::SetNE: 896 SignCond = ISD::SETNE; 897 UnsCond = ISD::SETNE; 898 FPCond = ISD::SETUNE; 899 break; 900 case Instruction::SetLE: 901 SignCond = ISD::SETLE; 902 UnsCond = ISD::SETULE; 903 FPCond = ISD::SETOLE; 904 break; 905 case Instruction::SetGE: 906 SignCond = ISD::SETGE; 907 UnsCond = ISD::SETUGE; 908 FPCond = ISD::SETOGE; 909 break; 910 case Instruction::SetLT: 911 SignCond = ISD::SETLT; 912 UnsCond = ISD::SETULT; 913 FPCond = ISD::SETOLT; 914 break; 915 case Instruction::SetGT: 916 SignCond = ISD::SETGT; 917 UnsCond = ISD::SETUGT; 918 FPCond = ISD::SETOGT; 919 break; 920 } 921 922 const Type *OpType = BOp->getOperand(0)->getType(); 923 if (const PackedType *PTy = dyn_cast<PackedType>(OpType)) 924 OpType = PTy->getElementType(); 925 926 if (!FiniteOnlyFPMath() && OpType->isFloatingPoint()) 927 Condition = FPCond; 928 else if (OpType->isUnsigned()) 929 Condition = UnsCond; 930 else 931 Condition = SignCond; 932 933 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0), 934 BOp->getOperand(1), TBB, FBB, CurBB); 935 SwitchCases.push_back(CB); 936 return; 937 } 938 939 // Create a CaseBlock record representing this branch. 940 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantBool::getTrue(), 941 TBB, FBB, CurBB); 942 SwitchCases.push_back(CB); 943 return; 944 } 945 946 947 // Create TmpBB after CurBB. 948 MachineFunction::iterator BBI = CurBB; 949 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); 950 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); 951 952 if (Opc == Instruction::Or) { 953 // Codegen X | Y as: 954 // jmp_if_X TBB 955 // jmp TmpBB 956 // TmpBB: 957 // jmp_if_Y TBB 958 // jmp FBB 959 // 960 961 // Emit the LHS condition. 962 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); 963 964 // Emit the RHS condition into TmpBB. 965 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 966 } else { 967 assert(Opc == Instruction::And && "Unknown merge op!"); 968 // Codegen X & Y as: 969 // jmp_if_X TmpBB 970 // jmp FBB 971 // TmpBB: 972 // jmp_if_Y TBB 973 // jmp FBB 974 // 975 // This requires creation of TmpBB after CurBB. 976 977 // Emit the LHS condition. 978 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); 979 980 // Emit the RHS condition into TmpBB. 981 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); 982 } 983} 984 985/// If the set of cases should be emitted as a series of branches, return true. 986/// If we should emit this as a bunch of and/or'd together conditions, return 987/// false. 988static bool 989ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) { 990 if (Cases.size() != 2) return true; 991 992 // If this is two comparisons of the same values or'd or and'd together, they 993 // will get folded into a single comparison, so don't emit two blocks. 994 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 995 Cases[0].CmpRHS == Cases[1].CmpRHS) || 996 (Cases[0].CmpRHS == Cases[1].CmpLHS && 997 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 998 return false; 999 } 1000 1001 return true; 1002} 1003 1004void SelectionDAGLowering::visitBr(BranchInst &I) { 1005 // Update machine-CFG edges. 1006 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1007 1008 // Figure out which block is immediately after the current one. 1009 MachineBasicBlock *NextBlock = 0; 1010 MachineFunction::iterator BBI = CurMBB; 1011 if (++BBI != CurMBB->getParent()->end()) 1012 NextBlock = BBI; 1013 1014 if (I.isUnconditional()) { 1015 // If this is not a fall-through branch, emit the branch. 1016 if (Succ0MBB != NextBlock) 1017 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1018 DAG.getBasicBlock(Succ0MBB))); 1019 1020 // Update machine-CFG edges. 1021 CurMBB->addSuccessor(Succ0MBB); 1022 1023 return; 1024 } 1025 1026 // If this condition is one of the special cases we handle, do special stuff 1027 // now. 1028 Value *CondVal = I.getCondition(); 1029 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1030 1031 // If this is a series of conditions that are or'd or and'd together, emit 1032 // this as a sequence of branches instead of setcc's with and/or operations. 1033 // For example, instead of something like: 1034 // cmp A, B 1035 // C = seteq 1036 // cmp D, E 1037 // F = setle 1038 // or C, F 1039 // jnz foo 1040 // Emit: 1041 // cmp A, B 1042 // je foo 1043 // cmp D, E 1044 // jle foo 1045 // 1046 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1047 if (BOp->hasOneUse() && 1048 (BOp->getOpcode() == Instruction::And || 1049 BOp->getOpcode() == Instruction::Or)) { 1050 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); 1051 // If the compares in later blocks need to use values not currently 1052 // exported from this block, export them now. This block should always 1053 // be the first entry. 1054 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); 1055 1056 // Allow some cases to be rejected. 1057 if (ShouldEmitAsBranches(SwitchCases)) { 1058 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1059 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1060 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1061 } 1062 1063 // Emit the branch for this block. 1064 visitSwitchCase(SwitchCases[0]); 1065 SwitchCases.erase(SwitchCases.begin()); 1066 return; 1067 } 1068 1069 // Okay, we decided not to do this, remove any inserted MBB's and clear 1070 // SwitchCases. 1071 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1072 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); 1073 1074 SwitchCases.clear(); 1075 } 1076 } 1077 1078 // Create a CaseBlock record representing this branch. 1079 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantBool::getTrue(), 1080 Succ0MBB, Succ1MBB, CurMBB); 1081 // Use visitSwitchCase to actually insert the fast branch sequence for this 1082 // cond branch. 1083 visitSwitchCase(CB); 1084} 1085 1086/// visitSwitchCase - Emits the necessary code to represent a single node in 1087/// the binary search tree resulting from lowering a switch instruction. 1088void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { 1089 SDOperand Cond; 1090 SDOperand CondLHS = getValue(CB.CmpLHS); 1091 1092 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to 1093 // handle common cases produced by branch lowering. 1094 if (CB.CmpRHS == ConstantBool::getTrue() && CB.CC == ISD::SETEQ) 1095 Cond = CondLHS; 1096 else if (CB.CmpRHS == ConstantBool::getFalse() && CB.CC == ISD::SETEQ) { 1097 SDOperand True = DAG.getConstant(1, CondLHS.getValueType()); 1098 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); 1099 } else 1100 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1101 1102 // Set NextBlock to be the MBB immediately after the current one, if any. 1103 // This is used to avoid emitting unnecessary branches to the next block. 1104 MachineBasicBlock *NextBlock = 0; 1105 MachineFunction::iterator BBI = CurMBB; 1106 if (++BBI != CurMBB->getParent()->end()) 1107 NextBlock = BBI; 1108 1109 // If the lhs block is the next block, invert the condition so that we can 1110 // fall through to the lhs instead of the rhs block. 1111 if (CB.TrueBB == NextBlock) { 1112 std::swap(CB.TrueBB, CB.FalseBB); 1113 SDOperand True = DAG.getConstant(1, Cond.getValueType()); 1114 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); 1115 } 1116 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, 1117 DAG.getBasicBlock(CB.TrueBB)); 1118 if (CB.FalseBB == NextBlock) 1119 DAG.setRoot(BrCond); 1120 else 1121 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, 1122 DAG.getBasicBlock(CB.FalseBB))); 1123 // Update successor info 1124 CurMBB->addSuccessor(CB.TrueBB); 1125 CurMBB->addSuccessor(CB.FalseBB); 1126} 1127 1128void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { 1129 // Emit the code for the jump table 1130 MVT::ValueType PTy = TLI.getPointerTy(); 1131 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy); 1132 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); 1133 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), 1134 Table, Index)); 1135 return; 1136} 1137 1138void SelectionDAGLowering::visitSwitch(SwitchInst &I) { 1139 // Figure out which block is immediately after the current one. 1140 MachineBasicBlock *NextBlock = 0; 1141 MachineFunction::iterator BBI = CurMBB; 1142 1143 if (++BBI != CurMBB->getParent()->end()) 1144 NextBlock = BBI; 1145 1146 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()]; 1147 1148 // If there is only the default destination, branch to it if it is not the 1149 // next basic block. Otherwise, just fall through. 1150 if (I.getNumOperands() == 2) { 1151 // Update machine-CFG edges. 1152 1153 // If this is not a fall-through branch, emit the branch. 1154 if (Default != NextBlock) 1155 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(), 1156 DAG.getBasicBlock(Default))); 1157 1158 CurMBB->addSuccessor(Default); 1159 return; 1160 } 1161 1162 // If there are any non-default case statements, create a vector of Cases 1163 // representing each one, and sort the vector so that we can efficiently 1164 // create a binary search tree from them. 1165 std::vector<Case> Cases; 1166 1167 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) { 1168 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)]; 1169 Cases.push_back(Case(I.getSuccessorValue(i), SMBB)); 1170 } 1171 1172 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1173 1174 // Get the Value to be switched on and default basic blocks, which will be 1175 // inserted into CaseBlock records, representing basic blocks in the binary 1176 // search tree. 1177 Value *SV = I.getOperand(0); 1178 1179 // Get the MachineFunction which holds the current MBB. This is used during 1180 // emission of jump tables, and when inserting any additional MBBs necessary 1181 // to represent the switch. 1182 MachineFunction *CurMF = CurMBB->getParent(); 1183 const BasicBlock *LLVMBB = CurMBB->getBasicBlock(); 1184 1185 // If the switch has few cases (two or less) emit a series of specific 1186 // tests. 1187 if (Cases.size() < 3) { 1188 // TODO: If any two of the cases has the same destination, and if one value 1189 // is the same as the other, but has one bit unset that the other has set, 1190 // use bit manipulation to do two compares at once. For example: 1191 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1192 1193 // Rearrange the case blocks so that the last one falls through if possible. 1194 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) { 1195 // The last case block won't fall through into 'NextBlock' if we emit the 1196 // branches in this order. See if rearranging a case value would help. 1197 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) { 1198 if (Cases[i].second == NextBlock) { 1199 std::swap(Cases[i], Cases.back()); 1200 break; 1201 } 1202 } 1203 } 1204 1205 // Create a CaseBlock record representing a conditional branch to 1206 // the Case's target mbb if the value being switched on SV is equal 1207 // to C. 1208 MachineBasicBlock *CurBlock = CurMBB; 1209 for (unsigned i = 0, e = Cases.size(); i != e; ++i) { 1210 MachineBasicBlock *FallThrough; 1211 if (i != e-1) { 1212 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock()); 1213 CurMF->getBasicBlockList().insert(BBI, FallThrough); 1214 } else { 1215 // If the last case doesn't match, go to the default block. 1216 FallThrough = Default; 1217 } 1218 1219 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first, 1220 Cases[i].second, FallThrough, CurBlock); 1221 1222 // If emitting the first comparison, just call visitSwitchCase to emit the 1223 // code into the current block. Otherwise, push the CaseBlock onto the 1224 // vector to be later processed by SDISel, and insert the node's MBB 1225 // before the next MBB. 1226 if (CurBlock == CurMBB) 1227 visitSwitchCase(CB); 1228 else 1229 SwitchCases.push_back(CB); 1230 1231 CurBlock = FallThrough; 1232 } 1233 return; 1234 } 1235 1236 // If the switch has more than 5 blocks, and at least 31.25% dense, and the 1237 // target supports indirect branches, then emit a jump table rather than 1238 // lowering the switch to a binary tree of conditional branches. 1239 if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || 1240 TLI.isOperationLegal(ISD::BRIND, MVT::Other)) && 1241 Cases.size() > 5) { 1242 uint64_t First =cast<ConstantIntegral>(Cases.front().first)->getZExtValue(); 1243 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getZExtValue(); 1244 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL); 1245 1246 if (Density >= 0.3125) { 1247 // Create a new basic block to hold the code for loading the address 1248 // of the jump table, and jumping to it. Update successor information; 1249 // we will either branch to the default case for the switch, or the jump 1250 // table. 1251 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); 1252 CurMF->getBasicBlockList().insert(BBI, JumpTableBB); 1253 CurMBB->addSuccessor(Default); 1254 CurMBB->addSuccessor(JumpTableBB); 1255 1256 // Subtract the lowest switch case value from the value being switched on 1257 // and conditional branch to default mbb if the result is greater than the 1258 // difference between smallest and largest cases. 1259 SDOperand SwitchOp = getValue(SV); 1260 MVT::ValueType VT = SwitchOp.getValueType(); 1261 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, 1262 DAG.getConstant(First, VT)); 1263 1264 // The SDNode we just created, which holds the value being switched on 1265 // minus the the smallest case value, needs to be copied to a virtual 1266 // register so it can be used as an index into the jump table in a 1267 // subsequent basic block. This value may be smaller or larger than the 1268 // target's pointer type, and therefore require extension or truncating. 1269 if (VT > TLI.getPointerTy()) 1270 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); 1271 else 1272 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); 1273 1274 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1275 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp); 1276 1277 // Emit the range check for the jump table, and branch to the default 1278 // block for the switch statement if the value being switched on exceeds 1279 // the largest case in the switch. 1280 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB, 1281 DAG.getConstant(Last-First,VT), ISD::SETUGT); 1282 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, 1283 DAG.getBasicBlock(Default))); 1284 1285 // Build a vector of destination BBs, corresponding to each target 1286 // of the jump table. If the value of the jump table slot corresponds to 1287 // a case statement, push the case's BB onto the vector, otherwise, push 1288 // the default BB. 1289 std::vector<MachineBasicBlock*> DestBBs; 1290 uint64_t TEI = First; 1291 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) 1292 if (cast<ConstantIntegral>(ii->first)->getZExtValue() == TEI) { 1293 DestBBs.push_back(ii->second); 1294 ++ii; 1295 } else { 1296 DestBBs.push_back(Default); 1297 } 1298 1299 // Update successor info. Add one edge to each unique successor. 1300 // Vector bool would be better, but vector<bool> is really slow. 1301 std::vector<unsigned char> SuccsHandled; 1302 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs()); 1303 1304 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1305 E = DestBBs.end(); I != E; ++I) { 1306 if (!SuccsHandled[(*I)->getNumber()]) { 1307 SuccsHandled[(*I)->getNumber()] = true; 1308 JumpTableBB->addSuccessor(*I); 1309 } 1310 } 1311 1312 // Create a jump table index for this jump table, or return an existing 1313 // one. 1314 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); 1315 1316 // Set the jump table information so that we can codegen it as a second 1317 // MachineBasicBlock 1318 JT.Reg = JumpTableReg; 1319 JT.JTI = JTI; 1320 JT.MBB = JumpTableBB; 1321 JT.Default = Default; 1322 return; 1323 } 1324 } 1325 1326 // Push the initial CaseRec onto the worklist 1327 std::vector<CaseRec> CaseVec; 1328 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end()))); 1329 1330 while (!CaseVec.empty()) { 1331 // Grab a record representing a case range to process off the worklist 1332 CaseRec CR = CaseVec.back(); 1333 CaseVec.pop_back(); 1334 1335 // Size is the number of Cases represented by this range. If Size is 1, 1336 // then we are processing a leaf of the binary search tree. Otherwise, 1337 // we need to pick a pivot, and push left and right ranges onto the 1338 // worklist. 1339 unsigned Size = CR.Range.second - CR.Range.first; 1340 1341 if (Size == 1) { 1342 // Create a CaseBlock record representing a conditional branch to 1343 // the Case's target mbb if the value being switched on SV is equal 1344 // to C. Otherwise, branch to default. 1345 Constant *C = CR.Range.first->first; 1346 MachineBasicBlock *Target = CR.Range.first->second; 1347 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default, 1348 CR.CaseBB); 1349 1350 // If the MBB representing the leaf node is the current MBB, then just 1351 // call visitSwitchCase to emit the code into the current block. 1352 // Otherwise, push the CaseBlock onto the vector to be later processed 1353 // by SDISel, and insert the node's MBB before the next MBB. 1354 if (CR.CaseBB == CurMBB) 1355 visitSwitchCase(CB); 1356 else 1357 SwitchCases.push_back(CB); 1358 } else { 1359 // split case range at pivot 1360 CaseItr Pivot = CR.Range.first + (Size / 2); 1361 CaseRange LHSR(CR.Range.first, Pivot); 1362 CaseRange RHSR(Pivot, CR.Range.second); 1363 Constant *C = Pivot->first; 1364 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1365 1366 // We know that we branch to the LHS if the Value being switched on is 1367 // less than the Pivot value, C. We use this to optimize our binary 1368 // tree a bit, by recognizing that if SV is greater than or equal to the 1369 // LHS's Case Value, and that Case Value is exactly one less than the 1370 // Pivot's Value, then we can branch directly to the LHS's Target, 1371 // rather than creating a leaf node for it. 1372 if ((LHSR.second - LHSR.first) == 1 && 1373 LHSR.first->first == CR.GE && 1374 cast<ConstantIntegral>(C)->getZExtValue() == 1375 (cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) { 1376 TrueBB = LHSR.first->second; 1377 } else { 1378 TrueBB = new MachineBasicBlock(LLVMBB); 1379 CurMF->getBasicBlockList().insert(BBI, TrueBB); 1380 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1381 } 1382 1383 // Similar to the optimization above, if the Value being switched on is 1384 // known to be less than the Constant CR.LT, and the current Case Value 1385 // is CR.LT - 1, then we can branch directly to the target block for 1386 // the current Case Value, rather than emitting a RHS leaf node for it. 1387 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1388 cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() == 1389 (cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) { 1390 FalseBB = RHSR.first->second; 1391 } else { 1392 FalseBB = new MachineBasicBlock(LLVMBB); 1393 CurMF->getBasicBlockList().insert(BBI, FalseBB); 1394 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1395 } 1396 1397 // Create a CaseBlock record representing a conditional branch to 1398 // the LHS node if the value being switched on SV is less than C. 1399 // Otherwise, branch to LHS. 1400 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT; 1401 SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB); 1402 1403 if (CR.CaseBB == CurMBB) 1404 visitSwitchCase(CB); 1405 else 1406 SwitchCases.push_back(CB); 1407 } 1408 } 1409} 1410 1411void SelectionDAGLowering::visitSub(User &I) { 1412 // -0.0 - X --> fneg 1413 if (I.getType()->isFloatingPoint()) { 1414 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 1415 if (CFP->isExactlyValue(-0.0)) { 1416 SDOperand Op2 = getValue(I.getOperand(1)); 1417 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); 1418 return; 1419 } 1420 visitFPBinary(I, ISD::FSUB, ISD::VSUB); 1421 } else 1422 visitIntBinary(I, ISD::SUB, ISD::VSUB); 1423} 1424 1425void 1426SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) { 1427 const Type *Ty = I.getType(); 1428 SDOperand Op1 = getValue(I.getOperand(0)); 1429 SDOperand Op2 = getValue(I.getOperand(1)); 1430 1431 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1432 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32); 1433 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType())); 1434 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ)); 1435 } else { 1436 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2)); 1437 } 1438} 1439 1440void 1441SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) { 1442 const Type *Ty = I.getType(); 1443 SDOperand Op1 = getValue(I.getOperand(0)); 1444 SDOperand Op2 = getValue(I.getOperand(1)); 1445 1446 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1447 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32); 1448 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType())); 1449 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ)); 1450 } else { 1451 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2)); 1452 } 1453} 1454 1455void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { 1456 SDOperand Op1 = getValue(I.getOperand(0)); 1457 SDOperand Op2 = getValue(I.getOperand(1)); 1458 1459 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); 1460 1461 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); 1462} 1463 1464void SelectionDAGLowering::visitICmp(User &I) { 1465 ICmpInst *IC = cast<ICmpInst>(&I); 1466 SDOperand Op1 = getValue(IC->getOperand(0)); 1467 SDOperand Op2 = getValue(IC->getOperand(1)); 1468 ISD::CondCode Opcode; 1469 switch (IC->getPredicate()) { 1470 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break; 1471 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break; 1472 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break; 1473 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break; 1474 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break; 1475 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break; 1476 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break; 1477 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break; 1478 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break; 1479 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break; 1480 default: 1481 assert(!"Invalid ICmp predicate value"); 1482 Opcode = ISD::SETEQ; 1483 break; 1484 } 1485 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1486} 1487 1488void SelectionDAGLowering::visitFCmp(User &I) { 1489 FCmpInst *FC = cast<FCmpInst>(&I); 1490 SDOperand Op1 = getValue(FC->getOperand(0)); 1491 SDOperand Op2 = getValue(FC->getOperand(1)); 1492 ISD::CondCode Opcode; 1493 switch (FC->getPredicate()) { 1494 case FCmpInst::FCMP_FALSE : Opcode = ISD::SETFALSE; 1495 case FCmpInst::FCMP_OEQ : Opcode = ISD::SETOEQ; 1496 case FCmpInst::FCMP_OGT : Opcode = ISD::SETOGT; 1497 case FCmpInst::FCMP_OGE : Opcode = ISD::SETOGE; 1498 case FCmpInst::FCMP_OLT : Opcode = ISD::SETOLT; 1499 case FCmpInst::FCMP_OLE : Opcode = ISD::SETOLE; 1500 case FCmpInst::FCMP_ONE : Opcode = ISD::SETONE; 1501 case FCmpInst::FCMP_ORD : Opcode = ISD::SETO; 1502 case FCmpInst::FCMP_UNO : Opcode = ISD::SETUO; 1503 case FCmpInst::FCMP_UEQ : Opcode = ISD::SETUEQ; 1504 case FCmpInst::FCMP_UGT : Opcode = ISD::SETUGT; 1505 case FCmpInst::FCMP_UGE : Opcode = ISD::SETUGE; 1506 case FCmpInst::FCMP_ULT : Opcode = ISD::SETULT; 1507 case FCmpInst::FCMP_ULE : Opcode = ISD::SETULE; 1508 case FCmpInst::FCMP_UNE : Opcode = ISD::SETUNE; 1509 case FCmpInst::FCMP_TRUE : Opcode = ISD::SETTRUE; 1510 default: 1511 assert(!"Invalid FCmp predicate value"); 1512 Opcode = ISD::SETFALSE; 1513 break; 1514 } 1515 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1516} 1517 1518void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode, 1519 ISD::CondCode UnsignedOpcode, 1520 ISD::CondCode FPOpcode) { 1521 SDOperand Op1 = getValue(I.getOperand(0)); 1522 SDOperand Op2 = getValue(I.getOperand(1)); 1523 ISD::CondCode Opcode = SignedOpcode; 1524 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint()) 1525 Opcode = FPOpcode; 1526 else if (I.getOperand(0)->getType()->isUnsigned()) 1527 Opcode = UnsignedOpcode; 1528 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); 1529} 1530 1531void SelectionDAGLowering::visitSelect(User &I) { 1532 SDOperand Cond = getValue(I.getOperand(0)); 1533 SDOperand TrueVal = getValue(I.getOperand(1)); 1534 SDOperand FalseVal = getValue(I.getOperand(2)); 1535 if (!isa<PackedType>(I.getType())) { 1536 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, 1537 TrueVal, FalseVal)); 1538 } else { 1539 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, 1540 *(TrueVal.Val->op_end()-2), 1541 *(TrueVal.Val->op_end()-1))); 1542 } 1543} 1544 1545 1546void SelectionDAGLowering::visitTrunc(User &I) { 1547 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 1548 SDOperand N = getValue(I.getOperand(0)); 1549 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1550 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1551} 1552 1553void SelectionDAGLowering::visitZExt(User &I) { 1554 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 1555 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 1556 SDOperand N = getValue(I.getOperand(0)); 1557 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1558 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1559} 1560 1561void SelectionDAGLowering::visitSExt(User &I) { 1562 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 1563 // SExt also can't be a cast to bool for same reason. So, nothing much to do 1564 SDOperand N = getValue(I.getOperand(0)); 1565 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1566 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); 1567} 1568 1569void SelectionDAGLowering::visitFPTrunc(User &I) { 1570 // FPTrunc is never a no-op cast, no need to check 1571 SDOperand N = getValue(I.getOperand(0)); 1572 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1573 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); 1574} 1575 1576void SelectionDAGLowering::visitFPExt(User &I){ 1577 // FPTrunc is never a no-op cast, no need to check 1578 SDOperand N = getValue(I.getOperand(0)); 1579 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1580 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); 1581} 1582 1583void SelectionDAGLowering::visitFPToUI(User &I) { 1584 // FPToUI is never a no-op cast, no need to check 1585 SDOperand N = getValue(I.getOperand(0)); 1586 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1587 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); 1588} 1589 1590void SelectionDAGLowering::visitFPToSI(User &I) { 1591 // FPToSI is never a no-op cast, no need to check 1592 SDOperand N = getValue(I.getOperand(0)); 1593 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1594 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); 1595} 1596 1597void SelectionDAGLowering::visitUIToFP(User &I) { 1598 // UIToFP is never a no-op cast, no need to check 1599 SDOperand N = getValue(I.getOperand(0)); 1600 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1601 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); 1602} 1603 1604void SelectionDAGLowering::visitSIToFP(User &I){ 1605 // UIToFP is never a no-op cast, no need to check 1606 SDOperand N = getValue(I.getOperand(0)); 1607 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1608 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); 1609} 1610 1611void SelectionDAGLowering::visitPtrToInt(User &I) { 1612 // What to do depends on the size of the integer and the size of the pointer. 1613 // We can either truncate, zero extend, or no-op, accordingly. 1614 SDOperand N = getValue(I.getOperand(0)); 1615 MVT::ValueType SrcVT = N.getValueType(); 1616 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1617 SDOperand Result; 1618 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 1619 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); 1620 else 1621 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 1622 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); 1623 setValue(&I, Result); 1624} 1625 1626void SelectionDAGLowering::visitIntToPtr(User &I) { 1627 // What to do depends on the size of the integer and the size of the pointer. 1628 // We can either truncate, zero extend, or no-op, accordingly. 1629 SDOperand N = getValue(I.getOperand(0)); 1630 MVT::ValueType SrcVT = N.getValueType(); 1631 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1632 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) 1633 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); 1634 else 1635 // Note: ZERO_EXTEND can handle cases where the sizes are equal too 1636 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); 1637} 1638 1639void SelectionDAGLowering::visitBitCast(User &I) { 1640 SDOperand N = getValue(I.getOperand(0)); 1641 MVT::ValueType DestVT = TLI.getValueType(I.getType()); 1642 if (DestVT == MVT::Vector) { 1643 // This is a cast to a vector from something else. 1644 // Get information about the output vector. 1645 const PackedType *DestTy = cast<PackedType>(I.getType()); 1646 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1647 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N, 1648 DAG.getConstant(DestTy->getNumElements(),MVT::i32), 1649 DAG.getValueType(EltVT))); 1650 return; 1651 } 1652 MVT::ValueType SrcVT = N.getValueType(); 1653 if (SrcVT == MVT::Vector) { 1654 // This is a cast from a vctor to something else. 1655 // Get information about the input vector. 1656 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N)); 1657 return; 1658 } 1659 1660 // BitCast assures us that source and destination are the same size so this 1661 // is either a BIT_CONVERT or a no-op. 1662 if (DestVT != N.getValueType()) 1663 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types 1664 else 1665 setValue(&I, N); // noop cast. 1666} 1667 1668void SelectionDAGLowering::visitInsertElement(User &I) { 1669 SDOperand InVec = getValue(I.getOperand(0)); 1670 SDOperand InVal = getValue(I.getOperand(1)); 1671 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1672 getValue(I.getOperand(2))); 1673 1674 SDOperand Num = *(InVec.Val->op_end()-2); 1675 SDOperand Typ = *(InVec.Val->op_end()-1); 1676 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector, 1677 InVec, InVal, InIdx, Num, Typ)); 1678} 1679 1680void SelectionDAGLowering::visitExtractElement(User &I) { 1681 SDOperand InVec = getValue(I.getOperand(0)); 1682 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), 1683 getValue(I.getOperand(1))); 1684 SDOperand Typ = *(InVec.Val->op_end()-1); 1685 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, 1686 TLI.getValueType(I.getType()), InVec, InIdx)); 1687} 1688 1689void SelectionDAGLowering::visitShuffleVector(User &I) { 1690 SDOperand V1 = getValue(I.getOperand(0)); 1691 SDOperand V2 = getValue(I.getOperand(1)); 1692 SDOperand Mask = getValue(I.getOperand(2)); 1693 1694 SDOperand Num = *(V1.Val->op_end()-2); 1695 SDOperand Typ = *(V2.Val->op_end()-1); 1696 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 1697 V1, V2, Mask, Num, Typ)); 1698} 1699 1700 1701void SelectionDAGLowering::visitGetElementPtr(User &I) { 1702 SDOperand N = getValue(I.getOperand(0)); 1703 const Type *Ty = I.getOperand(0)->getType(); 1704 1705 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); 1706 OI != E; ++OI) { 1707 Value *Idx = *OI; 1708 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 1709 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 1710 if (Field) { 1711 // N = N + Offset 1712 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field]; 1713 N = DAG.getNode(ISD::ADD, N.getValueType(), N, 1714 getIntPtrConstant(Offset)); 1715 } 1716 Ty = StTy->getElementType(Field); 1717 } else { 1718 Ty = cast<SequentialType>(Ty)->getElementType(); 1719 1720 // If this is a constant subscript, handle it quickly. 1721 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 1722 if (CI->getZExtValue() == 0) continue; 1723 uint64_t Offs; 1724 if (CI->getType()->isSigned()) 1725 Offs = (int64_t) 1726 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 1727 else 1728 Offs = 1729 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getZExtValue(); 1730 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); 1731 continue; 1732 } 1733 1734 // N = N + Idx * ElementSize; 1735 uint64_t ElementSize = TD->getTypeSize(Ty); 1736 SDOperand IdxN = getValue(Idx); 1737 1738 // If the index is smaller or larger than intptr_t, truncate or extend 1739 // it. 1740 if (IdxN.getValueType() < N.getValueType()) { 1741 if (Idx->getType()->isSigned()) 1742 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); 1743 else 1744 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN); 1745 } else if (IdxN.getValueType() > N.getValueType()) 1746 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); 1747 1748 // If this is a multiply by a power of two, turn it into a shl 1749 // immediately. This is a very common case. 1750 if (isPowerOf2_64(ElementSize)) { 1751 unsigned Amt = Log2_64(ElementSize); 1752 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, 1753 DAG.getConstant(Amt, TLI.getShiftAmountTy())); 1754 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1755 continue; 1756 } 1757 1758 SDOperand Scale = getIntPtrConstant(ElementSize); 1759 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); 1760 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); 1761 } 1762 } 1763 setValue(&I, N); 1764} 1765 1766void SelectionDAGLowering::visitAlloca(AllocaInst &I) { 1767 // If this is a fixed sized alloca in the entry block of the function, 1768 // allocate it statically on the stack. 1769 if (FuncInfo.StaticAllocaMap.count(&I)) 1770 return; // getValue will auto-populate this. 1771 1772 const Type *Ty = I.getAllocatedType(); 1773 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 1774 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), 1775 I.getAlignment()); 1776 1777 SDOperand AllocSize = getValue(I.getArraySize()); 1778 MVT::ValueType IntPtr = TLI.getPointerTy(); 1779 if (IntPtr < AllocSize.getValueType()) 1780 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); 1781 else if (IntPtr > AllocSize.getValueType()) 1782 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); 1783 1784 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, 1785 getIntPtrConstant(TySize)); 1786 1787 // Handle alignment. If the requested alignment is less than or equal to the 1788 // stack alignment, ignore it and round the size of the allocation up to the 1789 // stack alignment size. If the size is greater than the stack alignment, we 1790 // note this in the DYNAMIC_STACKALLOC node. 1791 unsigned StackAlign = 1792 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1793 if (Align <= StackAlign) { 1794 Align = 0; 1795 // Add SA-1 to the size. 1796 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, 1797 getIntPtrConstant(StackAlign-1)); 1798 // Mask out the low bits for alignment purposes. 1799 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, 1800 getIntPtrConstant(~(uint64_t)(StackAlign-1))); 1801 } 1802 1803 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) }; 1804 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), 1805 MVT::Other); 1806 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); 1807 DAG.setRoot(setValue(&I, DSA).getValue(1)); 1808 1809 // Inform the Frame Information that we have just allocated a variable-sized 1810 // object. 1811 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject(); 1812} 1813 1814void SelectionDAGLowering::visitLoad(LoadInst &I) { 1815 SDOperand Ptr = getValue(I.getOperand(0)); 1816 1817 SDOperand Root; 1818 if (I.isVolatile()) 1819 Root = getRoot(); 1820 else { 1821 // Do not serialize non-volatile loads against each other. 1822 Root = DAG.getRoot(); 1823 } 1824 1825 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), 1826 Root, I.isVolatile())); 1827} 1828 1829SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, 1830 const Value *SV, SDOperand Root, 1831 bool isVolatile) { 1832 SDOperand L; 1833 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) { 1834 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); 1835 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, 1836 DAG.getSrcValue(SV)); 1837 } else { 1838 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile); 1839 } 1840 1841 if (isVolatile) 1842 DAG.setRoot(L.getValue(1)); 1843 else 1844 PendingLoads.push_back(L.getValue(1)); 1845 1846 return L; 1847} 1848 1849 1850void SelectionDAGLowering::visitStore(StoreInst &I) { 1851 Value *SrcV = I.getOperand(0); 1852 SDOperand Src = getValue(SrcV); 1853 SDOperand Ptr = getValue(I.getOperand(1)); 1854 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 1855 I.isVolatile())); 1856} 1857 1858/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot 1859/// access memory and has no other side effects at all. 1860static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) { 1861#define GET_NO_MEMORY_INTRINSICS 1862#include "llvm/Intrinsics.gen" 1863#undef GET_NO_MEMORY_INTRINSICS 1864 return false; 1865} 1866 1867// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't 1868// have any side-effects or if it only reads memory. 1869static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) { 1870#define GET_SIDE_EFFECT_INFO 1871#include "llvm/Intrinsics.gen" 1872#undef GET_SIDE_EFFECT_INFO 1873 return false; 1874} 1875 1876/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 1877/// node. 1878void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 1879 unsigned Intrinsic) { 1880 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic); 1881 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic); 1882 1883 // Build the operand list. 1884 SmallVector<SDOperand, 8> Ops; 1885 if (HasChain) { // If this intrinsic has side-effects, chainify it. 1886 if (OnlyLoad) { 1887 // We don't need to serialize loads against other loads. 1888 Ops.push_back(DAG.getRoot()); 1889 } else { 1890 Ops.push_back(getRoot()); 1891 } 1892 } 1893 1894 // Add the intrinsic ID as an integer operand. 1895 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 1896 1897 // Add all operands of the call to the operand list. 1898 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 1899 SDOperand Op = getValue(I.getOperand(i)); 1900 1901 // If this is a vector type, force it to the right packed type. 1902 if (Op.getValueType() == MVT::Vector) { 1903 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType()); 1904 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType()); 1905 1906 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements()); 1907 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?"); 1908 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op); 1909 } 1910 1911 assert(TLI.isTypeLegal(Op.getValueType()) && 1912 "Intrinsic uses a non-legal type?"); 1913 Ops.push_back(Op); 1914 } 1915 1916 std::vector<MVT::ValueType> VTs; 1917 if (I.getType() != Type::VoidTy) { 1918 MVT::ValueType VT = TLI.getValueType(I.getType()); 1919 if (VT == MVT::Vector) { 1920 const PackedType *DestTy = cast<PackedType>(I.getType()); 1921 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); 1922 1923 VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); 1924 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); 1925 } 1926 1927 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); 1928 VTs.push_back(VT); 1929 } 1930 if (HasChain) 1931 VTs.push_back(MVT::Other); 1932 1933 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); 1934 1935 // Create the node. 1936 SDOperand Result; 1937 if (!HasChain) 1938 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), 1939 &Ops[0], Ops.size()); 1940 else if (I.getType() != Type::VoidTy) 1941 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), 1942 &Ops[0], Ops.size()); 1943 else 1944 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), 1945 &Ops[0], Ops.size()); 1946 1947 if (HasChain) { 1948 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1); 1949 if (OnlyLoad) 1950 PendingLoads.push_back(Chain); 1951 else 1952 DAG.setRoot(Chain); 1953 } 1954 if (I.getType() != Type::VoidTy) { 1955 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) { 1956 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType()); 1957 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 1958 DAG.getConstant(PTy->getNumElements(), MVT::i32), 1959 DAG.getValueType(EVT)); 1960 } 1961 setValue(&I, Result); 1962 } 1963} 1964 1965/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 1966/// we want to emit this as a call to a named external function, return the name 1967/// otherwise lower it and return null. 1968const char * 1969SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 1970 switch (Intrinsic) { 1971 default: 1972 // By default, turn this into a target intrinsic node. 1973 visitTargetIntrinsic(I, Intrinsic); 1974 return 0; 1975 case Intrinsic::vastart: visitVAStart(I); return 0; 1976 case Intrinsic::vaend: visitVAEnd(I); return 0; 1977 case Intrinsic::vacopy: visitVACopy(I); return 0; 1978 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0; 1979 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0; 1980 case Intrinsic::setjmp: 1981 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 1982 break; 1983 case Intrinsic::longjmp: 1984 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 1985 break; 1986 case Intrinsic::memcpy_i32: 1987 case Intrinsic::memcpy_i64: 1988 visitMemIntrinsic(I, ISD::MEMCPY); 1989 return 0; 1990 case Intrinsic::memset_i32: 1991 case Intrinsic::memset_i64: 1992 visitMemIntrinsic(I, ISD::MEMSET); 1993 return 0; 1994 case Intrinsic::memmove_i32: 1995 case Intrinsic::memmove_i64: 1996 visitMemIntrinsic(I, ISD::MEMMOVE); 1997 return 0; 1998 1999 case Intrinsic::dbg_stoppoint: { 2000 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 2001 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); 2002 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) { 2003 SDOperand Ops[5]; 2004 2005 Ops[0] = getRoot(); 2006 Ops[1] = getValue(SPI.getLineValue()); 2007 Ops[2] = getValue(SPI.getColumnValue()); 2008 2009 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext()); 2010 assert(DD && "Not a debug information descriptor"); 2011 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD); 2012 2013 Ops[3] = DAG.getString(CompileUnit->getFileName()); 2014 Ops[4] = DAG.getString(CompileUnit->getDirectory()); 2015 2016 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5)); 2017 } 2018 2019 return 0; 2020 } 2021 case Intrinsic::dbg_region_start: { 2022 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 2023 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); 2024 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) { 2025 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext()); 2026 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(), 2027 DAG.getConstant(LabelID, MVT::i32))); 2028 } 2029 2030 return 0; 2031 } 2032 case Intrinsic::dbg_region_end: { 2033 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 2034 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); 2035 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) { 2036 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext()); 2037 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 2038 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2039 } 2040 2041 return 0; 2042 } 2043 case Intrinsic::dbg_func_start: { 2044 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 2045 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); 2046 if (DebugInfo && FSI.getSubprogram() && 2047 DebugInfo->Verify(FSI.getSubprogram())) { 2048 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram()); 2049 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, 2050 getRoot(), DAG.getConstant(LabelID, MVT::i32))); 2051 } 2052 2053 return 0; 2054 } 2055 case Intrinsic::dbg_declare: { 2056 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 2057 DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 2058 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) { 2059 SDOperand AddressOp = getValue(DI.getAddress()); 2060 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) 2061 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex()); 2062 } 2063 2064 return 0; 2065 } 2066 2067 case Intrinsic::isunordered_f32: 2068 case Intrinsic::isunordered_f64: 2069 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), 2070 getValue(I.getOperand(2)), ISD::SETUO)); 2071 return 0; 2072 2073 case Intrinsic::sqrt_f32: 2074 case Intrinsic::sqrt_f64: 2075 setValue(&I, DAG.getNode(ISD::FSQRT, 2076 getValue(I.getOperand(1)).getValueType(), 2077 getValue(I.getOperand(1)))); 2078 return 0; 2079 case Intrinsic::powi_f32: 2080 case Intrinsic::powi_f64: 2081 setValue(&I, DAG.getNode(ISD::FPOWI, 2082 getValue(I.getOperand(1)).getValueType(), 2083 getValue(I.getOperand(1)), 2084 getValue(I.getOperand(2)))); 2085 return 0; 2086 case Intrinsic::pcmarker: { 2087 SDOperand Tmp = getValue(I.getOperand(1)); 2088 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); 2089 return 0; 2090 } 2091 case Intrinsic::readcyclecounter: { 2092 SDOperand Op = getRoot(); 2093 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, 2094 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, 2095 &Op, 1); 2096 setValue(&I, Tmp); 2097 DAG.setRoot(Tmp.getValue(1)); 2098 return 0; 2099 } 2100 case Intrinsic::bswap_i16: 2101 case Intrinsic::bswap_i32: 2102 case Intrinsic::bswap_i64: 2103 setValue(&I, DAG.getNode(ISD::BSWAP, 2104 getValue(I.getOperand(1)).getValueType(), 2105 getValue(I.getOperand(1)))); 2106 return 0; 2107 case Intrinsic::cttz_i8: 2108 case Intrinsic::cttz_i16: 2109 case Intrinsic::cttz_i32: 2110 case Intrinsic::cttz_i64: 2111 setValue(&I, DAG.getNode(ISD::CTTZ, 2112 getValue(I.getOperand(1)).getValueType(), 2113 getValue(I.getOperand(1)))); 2114 return 0; 2115 case Intrinsic::ctlz_i8: 2116 case Intrinsic::ctlz_i16: 2117 case Intrinsic::ctlz_i32: 2118 case Intrinsic::ctlz_i64: 2119 setValue(&I, DAG.getNode(ISD::CTLZ, 2120 getValue(I.getOperand(1)).getValueType(), 2121 getValue(I.getOperand(1)))); 2122 return 0; 2123 case Intrinsic::ctpop_i8: 2124 case Intrinsic::ctpop_i16: 2125 case Intrinsic::ctpop_i32: 2126 case Intrinsic::ctpop_i64: 2127 setValue(&I, DAG.getNode(ISD::CTPOP, 2128 getValue(I.getOperand(1)).getValueType(), 2129 getValue(I.getOperand(1)))); 2130 return 0; 2131 case Intrinsic::stacksave: { 2132 SDOperand Op = getRoot(); 2133 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, 2134 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); 2135 setValue(&I, Tmp); 2136 DAG.setRoot(Tmp.getValue(1)); 2137 return 0; 2138 } 2139 case Intrinsic::stackrestore: { 2140 SDOperand Tmp = getValue(I.getOperand(1)); 2141 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); 2142 return 0; 2143 } 2144 case Intrinsic::prefetch: 2145 // FIXME: Currently discarding prefetches. 2146 return 0; 2147 } 2148} 2149 2150 2151void SelectionDAGLowering::visitCall(CallInst &I) { 2152 const char *RenameFn = 0; 2153 if (Function *F = I.getCalledFunction()) { 2154 if (F->isExternal()) 2155 if (unsigned IID = F->getIntrinsicID()) { 2156 RenameFn = visitIntrinsicCall(I, IID); 2157 if (!RenameFn) 2158 return; 2159 } else { // Not an LLVM intrinsic. 2160 const std::string &Name = F->getName(); 2161 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) { 2162 if (I.getNumOperands() == 3 && // Basic sanity checks. 2163 I.getOperand(1)->getType()->isFloatingPoint() && 2164 I.getType() == I.getOperand(1)->getType() && 2165 I.getType() == I.getOperand(2)->getType()) { 2166 SDOperand LHS = getValue(I.getOperand(1)); 2167 SDOperand RHS = getValue(I.getOperand(2)); 2168 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), 2169 LHS, RHS)); 2170 return; 2171 } 2172 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) { 2173 if (I.getNumOperands() == 2 && // Basic sanity checks. 2174 I.getOperand(1)->getType()->isFloatingPoint() && 2175 I.getType() == I.getOperand(1)->getType()) { 2176 SDOperand Tmp = getValue(I.getOperand(1)); 2177 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); 2178 return; 2179 } 2180 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) { 2181 if (I.getNumOperands() == 2 && // Basic sanity checks. 2182 I.getOperand(1)->getType()->isFloatingPoint() && 2183 I.getType() == I.getOperand(1)->getType()) { 2184 SDOperand Tmp = getValue(I.getOperand(1)); 2185 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); 2186 return; 2187 } 2188 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) { 2189 if (I.getNumOperands() == 2 && // Basic sanity checks. 2190 I.getOperand(1)->getType()->isFloatingPoint() && 2191 I.getType() == I.getOperand(1)->getType()) { 2192 SDOperand Tmp = getValue(I.getOperand(1)); 2193 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); 2194 return; 2195 } 2196 } 2197 } 2198 } else if (isa<InlineAsm>(I.getOperand(0))) { 2199 visitInlineAsm(I); 2200 return; 2201 } 2202 2203 SDOperand Callee; 2204 if (!RenameFn) 2205 Callee = getValue(I.getOperand(0)); 2206 else 2207 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 2208 std::vector<std::pair<SDOperand, const Type*> > Args; 2209 Args.reserve(I.getNumOperands()); 2210 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2211 Value *Arg = I.getOperand(i); 2212 SDOperand ArgNode = getValue(Arg); 2213 Args.push_back(std::make_pair(ArgNode, Arg->getType())); 2214 } 2215 2216 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType()); 2217 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2218 2219 std::pair<SDOperand,SDOperand> Result = 2220 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(), 2221 I.isTailCall(), Callee, Args, DAG); 2222 if (I.getType() != Type::VoidTy) 2223 setValue(&I, Result.first); 2224 DAG.setRoot(Result.second); 2225} 2226 2227SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 2228 SDOperand &Chain, SDOperand &Flag)const{ 2229 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag); 2230 Chain = Val.getValue(1); 2231 Flag = Val.getValue(2); 2232 2233 // If the result was expanded, copy from the top part. 2234 if (Regs.size() > 1) { 2235 assert(Regs.size() == 2 && 2236 "Cannot expand to more than 2 elts yet!"); 2237 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag); 2238 Chain = Hi.getValue(1); 2239 Flag = Hi.getValue(2); 2240 if (DAG.getTargetLoweringInfo().isLittleEndian()) 2241 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi); 2242 else 2243 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val); 2244 } 2245 2246 // Otherwise, if the return value was promoted or extended, truncate it to the 2247 // appropriate type. 2248 if (RegVT == ValueVT) 2249 return Val; 2250 2251 if (MVT::isInteger(RegVT)) { 2252 if (ValueVT < RegVT) 2253 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); 2254 else 2255 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); 2256 } else { 2257 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val); 2258 } 2259} 2260 2261/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 2262/// specified value into the registers specified by this object. This uses 2263/// Chain/Flag as the input and updates them for the output Chain/Flag. 2264void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, 2265 SDOperand &Chain, SDOperand &Flag, 2266 MVT::ValueType PtrVT) const { 2267 if (Regs.size() == 1) { 2268 // If there is a single register and the types differ, this must be 2269 // a promotion. 2270 if (RegVT != ValueVT) { 2271 if (MVT::isInteger(RegVT)) { 2272 if (RegVT < ValueVT) 2273 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val); 2274 else 2275 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val); 2276 } else 2277 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val); 2278 } 2279 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag); 2280 Flag = Chain.getValue(1); 2281 } else { 2282 std::vector<unsigned> R(Regs); 2283 if (!DAG.getTargetLoweringInfo().isLittleEndian()) 2284 std::reverse(R.begin(), R.end()); 2285 2286 for (unsigned i = 0, e = R.size(); i != e; ++i) { 2287 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, 2288 DAG.getConstant(i, PtrVT)); 2289 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); 2290 Flag = Chain.getValue(1); 2291 } 2292 } 2293} 2294 2295/// AddInlineAsmOperands - Add this value to the specified inlineasm node 2296/// operand list. This adds the code marker and includes the number of 2297/// values added into it. 2298void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, 2299 std::vector<SDOperand> &Ops) const { 2300 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32)); 2301 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 2302 Ops.push_back(DAG.getRegister(Regs[i], RegVT)); 2303} 2304 2305/// isAllocatableRegister - If the specified register is safe to allocate, 2306/// i.e. it isn't a stack pointer or some other special register, return the 2307/// register class for the register. Otherwise, return null. 2308static const TargetRegisterClass * 2309isAllocatableRegister(unsigned Reg, MachineFunction &MF, 2310 const TargetLowering &TLI, const MRegisterInfo *MRI) { 2311 MVT::ValueType FoundVT = MVT::Other; 2312 const TargetRegisterClass *FoundRC = 0; 2313 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), 2314 E = MRI->regclass_end(); RCI != E; ++RCI) { 2315 MVT::ValueType ThisVT = MVT::Other; 2316 2317 const TargetRegisterClass *RC = *RCI; 2318 // If none of the the value types for this register class are valid, we 2319 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2320 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2321 I != E; ++I) { 2322 if (TLI.isTypeLegal(*I)) { 2323 // If we have already found this register in a different register class, 2324 // choose the one with the largest VT specified. For example, on 2325 // PowerPC, we favor f64 register classes over f32. 2326 if (FoundVT == MVT::Other || 2327 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { 2328 ThisVT = *I; 2329 break; 2330 } 2331 } 2332 } 2333 2334 if (ThisVT == MVT::Other) continue; 2335 2336 // NOTE: This isn't ideal. In particular, this might allocate the 2337 // frame pointer in functions that need it (due to them not being taken 2338 // out of allocation, because a variable sized allocation hasn't been seen 2339 // yet). This is a slight code pessimization, but should still work. 2340 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 2341 E = RC->allocation_order_end(MF); I != E; ++I) 2342 if (*I == Reg) { 2343 // We found a matching register class. Keep looking at others in case 2344 // we find one with larger registers that this physreg is also in. 2345 FoundRC = RC; 2346 FoundVT = ThisVT; 2347 break; 2348 } 2349 } 2350 return FoundRC; 2351} 2352 2353RegsForValue SelectionDAGLowering:: 2354GetRegistersForValue(const std::string &ConstrCode, 2355 MVT::ValueType VT, bool isOutReg, bool isInReg, 2356 std::set<unsigned> &OutputRegs, 2357 std::set<unsigned> &InputRegs) { 2358 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 2359 TLI.getRegForInlineAsmConstraint(ConstrCode, VT); 2360 std::vector<unsigned> Regs; 2361 2362 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1; 2363 MVT::ValueType RegVT; 2364 MVT::ValueType ValueVT = VT; 2365 2366 // If this is a constraint for a specific physical register, like {r17}, 2367 // assign it now. 2368 if (PhysReg.first) { 2369 if (VT == MVT::Other) 2370 ValueVT = *PhysReg.second->vt_begin(); 2371 2372 // Get the actual register value type. This is important, because the user 2373 // may have asked for (e.g.) the AX register in i32 type. We need to 2374 // remember that AX is actually i16 to get the right extension. 2375 RegVT = *PhysReg.second->vt_begin(); 2376 2377 // This is a explicit reference to a physical register. 2378 Regs.push_back(PhysReg.first); 2379 2380 // If this is an expanded reference, add the rest of the regs to Regs. 2381 if (NumRegs != 1) { 2382 TargetRegisterClass::iterator I = PhysReg.second->begin(); 2383 TargetRegisterClass::iterator E = PhysReg.second->end(); 2384 for (; *I != PhysReg.first; ++I) 2385 assert(I != E && "Didn't find reg!"); 2386 2387 // Already added the first reg. 2388 --NumRegs; ++I; 2389 for (; NumRegs; --NumRegs, ++I) { 2390 assert(I != E && "Ran out of registers to allocate!"); 2391 Regs.push_back(*I); 2392 } 2393 } 2394 return RegsForValue(Regs, RegVT, ValueVT); 2395 } 2396 2397 // Otherwise, if this was a reference to an LLVM register class, create vregs 2398 // for this reference. 2399 std::vector<unsigned> RegClassRegs; 2400 if (PhysReg.second) { 2401 // If this is an early clobber or tied register, our regalloc doesn't know 2402 // how to maintain the constraint. If it isn't, go ahead and create vreg 2403 // and let the regalloc do the right thing. 2404 if (!isOutReg || !isInReg) { 2405 if (VT == MVT::Other) 2406 ValueVT = *PhysReg.second->vt_begin(); 2407 RegVT = *PhysReg.second->vt_begin(); 2408 2409 // Create the appropriate number of virtual registers. 2410 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap(); 2411 for (; NumRegs; --NumRegs) 2412 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); 2413 2414 return RegsForValue(Regs, RegVT, ValueVT); 2415 } 2416 2417 // Otherwise, we can't allocate it. Let the code below figure out how to 2418 // maintain these constraints. 2419 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); 2420 2421 } else { 2422 // This is a reference to a register class that doesn't directly correspond 2423 // to an LLVM register class. Allocate NumRegs consecutive, available, 2424 // registers from the class. 2425 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT); 2426 } 2427 2428 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); 2429 MachineFunction &MF = *CurMBB->getParent(); 2430 unsigned NumAllocated = 0; 2431 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 2432 unsigned Reg = RegClassRegs[i]; 2433 // See if this register is available. 2434 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 2435 (isInReg && InputRegs.count(Reg))) { // Already used. 2436 // Make sure we find consecutive registers. 2437 NumAllocated = 0; 2438 continue; 2439 } 2440 2441 // Check to see if this register is allocatable (i.e. don't give out the 2442 // stack pointer). 2443 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI); 2444 if (!RC) { 2445 // Make sure we find consecutive registers. 2446 NumAllocated = 0; 2447 continue; 2448 } 2449 2450 // Okay, this register is good, we can use it. 2451 ++NumAllocated; 2452 2453 // If we allocated enough consecutive 2454 if (NumAllocated == NumRegs) { 2455 unsigned RegStart = (i-NumAllocated)+1; 2456 unsigned RegEnd = i+1; 2457 // Mark all of the allocated registers used. 2458 for (unsigned i = RegStart; i != RegEnd; ++i) { 2459 unsigned Reg = RegClassRegs[i]; 2460 Regs.push_back(Reg); 2461 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used. 2462 if (isInReg) InputRegs.insert(Reg); // Mark reg used. 2463 } 2464 2465 return RegsForValue(Regs, *RC->vt_begin(), VT); 2466 } 2467 } 2468 2469 // Otherwise, we couldn't allocate enough registers for this. 2470 return RegsForValue(); 2471} 2472 2473 2474/// visitInlineAsm - Handle a call to an InlineAsm object. 2475/// 2476void SelectionDAGLowering::visitInlineAsm(CallInst &I) { 2477 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0)); 2478 2479 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 2480 MVT::Other); 2481 2482 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 2483 std::vector<MVT::ValueType> ConstraintVTs; 2484 2485 /// AsmNodeOperands - A list of pairs. The first element is a register, the 2486 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set 2487 /// if it is a def of that register. 2488 std::vector<SDOperand> AsmNodeOperands; 2489 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain 2490 AsmNodeOperands.push_back(AsmStr); 2491 2492 SDOperand Chain = getRoot(); 2493 SDOperand Flag; 2494 2495 // We fully assign registers here at isel time. This is not optimal, but 2496 // should work. For register classes that correspond to LLVM classes, we 2497 // could let the LLVM RA do its thing, but we currently don't. Do a prepass 2498 // over the constraints, collecting fixed registers that we know we can't use. 2499 std::set<unsigned> OutputRegs, InputRegs; 2500 unsigned OpNum = 1; 2501 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2502 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2503 std::string &ConstraintCode = Constraints[i].Codes[0]; 2504 2505 MVT::ValueType OpVT; 2506 2507 // Compute the value type for each operand and add it to ConstraintVTs. 2508 switch (Constraints[i].Type) { 2509 case InlineAsm::isOutput: 2510 if (!Constraints[i].isIndirectOutput) { 2511 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2512 OpVT = TLI.getValueType(I.getType()); 2513 } else { 2514 const Type *OpTy = I.getOperand(OpNum)->getType(); 2515 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType()); 2516 OpNum++; // Consumes a call operand. 2517 } 2518 break; 2519 case InlineAsm::isInput: 2520 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType()); 2521 OpNum++; // Consumes a call operand. 2522 break; 2523 case InlineAsm::isClobber: 2524 OpVT = MVT::Other; 2525 break; 2526 } 2527 2528 ConstraintVTs.push_back(OpVT); 2529 2530 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0) 2531 continue; // Not assigned a fixed reg. 2532 2533 // Build a list of regs that this operand uses. This always has a single 2534 // element for promoted/expanded operands. 2535 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT, 2536 false, false, 2537 OutputRegs, InputRegs); 2538 2539 switch (Constraints[i].Type) { 2540 case InlineAsm::isOutput: 2541 // We can't assign any other output to this register. 2542 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2543 // If this is an early-clobber output, it cannot be assigned to the same 2544 // value as the input reg. 2545 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2546 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2547 break; 2548 case InlineAsm::isInput: 2549 // We can't assign any other input to this register. 2550 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2551 break; 2552 case InlineAsm::isClobber: 2553 // Clobbered regs cannot be used as inputs or outputs. 2554 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2555 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end()); 2556 break; 2557 } 2558 } 2559 2560 // Loop over all of the inputs, copying the operand values into the 2561 // appropriate registers and processing the output regs. 2562 RegsForValue RetValRegs; 2563 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 2564 OpNum = 1; 2565 2566 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { 2567 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); 2568 std::string &ConstraintCode = Constraints[i].Codes[0]; 2569 2570 switch (Constraints[i].Type) { 2571 case InlineAsm::isOutput: { 2572 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2573 if (ConstraintCode.size() == 1) // not a physreg name. 2574 CTy = TLI.getConstraintType(ConstraintCode[0]); 2575 2576 if (CTy == TargetLowering::C_Memory) { 2577 // Memory output. 2578 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2579 2580 // Check that the operand (the address to store to) isn't a float. 2581 if (!MVT::isInteger(InOperandVal.getValueType())) 2582 assert(0 && "MATCH FAIL!"); 2583 2584 if (!Constraints[i].isIndirectOutput) 2585 assert(0 && "MATCH FAIL!"); 2586 2587 OpNum++; // Consumes a call operand. 2588 2589 // Extend/truncate to the right pointer type if needed. 2590 MVT::ValueType PtrType = TLI.getPointerTy(); 2591 if (InOperandVal.getValueType() < PtrType) 2592 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2593 else if (InOperandVal.getValueType() > PtrType) 2594 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2595 2596 // Add information to the INLINEASM node to know about this output. 2597 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2598 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2599 AsmNodeOperands.push_back(InOperandVal); 2600 break; 2601 } 2602 2603 // Otherwise, this is a register output. 2604 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2605 2606 // If this is an early-clobber output, or if there is an input 2607 // constraint that matches this, we need to reserve the input register 2608 // so no other inputs allocate to it. 2609 bool UsesInputRegister = false; 2610 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput) 2611 UsesInputRegister = true; 2612 2613 // Copy the output from the appropriate register. Find a register that 2614 // we can use. 2615 RegsForValue Regs = 2616 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2617 true, UsesInputRegister, 2618 OutputRegs, InputRegs); 2619 if (Regs.Regs.empty()) { 2620 cerr << "Couldn't allocate output reg for contraint '" 2621 << ConstraintCode << "'!\n"; 2622 exit(1); 2623 } 2624 2625 if (!Constraints[i].isIndirectOutput) { 2626 assert(RetValRegs.Regs.empty() && 2627 "Cannot have multiple output constraints yet!"); 2628 assert(I.getType() != Type::VoidTy && "Bad inline asm!"); 2629 RetValRegs = Regs; 2630 } else { 2631 IndirectStoresToEmit.push_back(std::make_pair(Regs, 2632 I.getOperand(OpNum))); 2633 OpNum++; // Consumes a call operand. 2634 } 2635 2636 // Add information to the INLINEASM node to know that this register is 2637 // set. 2638 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands); 2639 break; 2640 } 2641 case InlineAsm::isInput: { 2642 SDOperand InOperandVal = getValue(I.getOperand(OpNum)); 2643 OpNum++; // Consumes a call operand. 2644 2645 if (isdigit(ConstraintCode[0])) { // Matching constraint? 2646 // If this is required to match an output register we have already set, 2647 // just use its register. 2648 unsigned OperandNo = atoi(ConstraintCode.c_str()); 2649 2650 // Scan until we find the definition we already emitted of this operand. 2651 // When we find it, create a RegsForValue operand. 2652 unsigned CurOp = 2; // The first operand. 2653 for (; OperandNo; --OperandNo) { 2654 // Advance to the next operand. 2655 unsigned NumOps = 2656 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2657 assert(((NumOps & 7) == 2 /*REGDEF*/ || 2658 (NumOps & 7) == 4 /*MEM*/) && 2659 "Skipped past definitions?"); 2660 CurOp += (NumOps>>3)+1; 2661 } 2662 2663 unsigned NumOps = 2664 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue(); 2665 assert((NumOps & 7) == 2 /*REGDEF*/ && 2666 "Skipped past definitions?"); 2667 2668 // Add NumOps>>3 registers to MatchedRegs. 2669 RegsForValue MatchedRegs; 2670 MatchedRegs.ValueVT = InOperandVal.getValueType(); 2671 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType(); 2672 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) { 2673 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); 2674 MatchedRegs.Regs.push_back(Reg); 2675 } 2676 2677 // Use the produced MatchedRegs object to 2678 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, 2679 TLI.getPointerTy()); 2680 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); 2681 break; 2682 } 2683 2684 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass; 2685 if (ConstraintCode.size() == 1) // not a physreg name. 2686 CTy = TLI.getConstraintType(ConstraintCode[0]); 2687 2688 if (CTy == TargetLowering::C_Other) { 2689 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal, 2690 ConstraintCode[0], DAG); 2691 if (!InOperandVal.Val) { 2692 cerr << "Invalid operand for inline asm constraint '" 2693 << ConstraintCode << "'!\n"; 2694 exit(1); 2695 } 2696 2697 // Add information to the INLINEASM node to know about this input. 2698 unsigned ResOpType = 3 /*IMM*/ | (1 << 3); 2699 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2700 AsmNodeOperands.push_back(InOperandVal); 2701 break; 2702 } else if (CTy == TargetLowering::C_Memory) { 2703 // Memory input. 2704 2705 // Check that the operand isn't a float. 2706 if (!MVT::isInteger(InOperandVal.getValueType())) 2707 assert(0 && "MATCH FAIL!"); 2708 2709 // Extend/truncate to the right pointer type if needed. 2710 MVT::ValueType PtrType = TLI.getPointerTy(); 2711 if (InOperandVal.getValueType() < PtrType) 2712 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal); 2713 else if (InOperandVal.getValueType() > PtrType) 2714 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal); 2715 2716 // Add information to the INLINEASM node to know about this input. 2717 unsigned ResOpType = 4/*MEM*/ | (1 << 3); 2718 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32)); 2719 AsmNodeOperands.push_back(InOperandVal); 2720 break; 2721 } 2722 2723 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!"); 2724 2725 // Copy the input into the appropriate registers. 2726 RegsForValue InRegs = 2727 GetRegistersForValue(ConstraintCode, ConstraintVTs[i], 2728 false, true, OutputRegs, InputRegs); 2729 // FIXME: should be match fail. 2730 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); 2731 2732 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); 2733 2734 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); 2735 break; 2736 } 2737 case InlineAsm::isClobber: { 2738 RegsForValue ClobberedRegs = 2739 GetRegistersForValue(ConstraintCode, MVT::Other, false, false, 2740 OutputRegs, InputRegs); 2741 // Add the clobbered value to the operand list, so that the register 2742 // allocator is aware that the physreg got clobbered. 2743 if (!ClobberedRegs.Regs.empty()) 2744 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands); 2745 break; 2746 } 2747 } 2748 } 2749 2750 // Finish up input operands. 2751 AsmNodeOperands[0] = Chain; 2752 if (Flag.Val) AsmNodeOperands.push_back(Flag); 2753 2754 Chain = DAG.getNode(ISD::INLINEASM, 2755 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, 2756 &AsmNodeOperands[0], AsmNodeOperands.size()); 2757 Flag = Chain.getValue(1); 2758 2759 // If this asm returns a register value, copy the result from that register 2760 // and set it as the value of the call. 2761 if (!RetValRegs.Regs.empty()) 2762 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag)); 2763 2764 std::vector<std::pair<SDOperand, Value*> > StoresToEmit; 2765 2766 // Process indirect outputs, first output all of the flagged copies out of 2767 // physregs. 2768 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 2769 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 2770 Value *Ptr = IndirectStoresToEmit[i].second; 2771 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag); 2772 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 2773 } 2774 2775 // Emit the non-flagged stores from the physregs. 2776 SmallVector<SDOperand, 8> OutChains; 2777 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) 2778 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, 2779 getValue(StoresToEmit[i].second), 2780 StoresToEmit[i].second, 0)); 2781 if (!OutChains.empty()) 2782 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2783 &OutChains[0], OutChains.size()); 2784 DAG.setRoot(Chain); 2785} 2786 2787 2788void SelectionDAGLowering::visitMalloc(MallocInst &I) { 2789 SDOperand Src = getValue(I.getOperand(0)); 2790 2791 MVT::ValueType IntPtr = TLI.getPointerTy(); 2792 2793 if (IntPtr < Src.getValueType()) 2794 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); 2795 else if (IntPtr > Src.getValueType()) 2796 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); 2797 2798 // Scale the source by the type size. 2799 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); 2800 Src = DAG.getNode(ISD::MUL, Src.getValueType(), 2801 Src, getIntPtrConstant(ElementSize)); 2802 2803 std::vector<std::pair<SDOperand, const Type*> > Args; 2804 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType())); 2805 2806 std::pair<SDOperand,SDOperand> Result = 2807 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, 2808 DAG.getExternalSymbol("malloc", IntPtr), 2809 Args, DAG); 2810 setValue(&I, Result.first); // Pointers always fit in registers 2811 DAG.setRoot(Result.second); 2812} 2813 2814void SelectionDAGLowering::visitFree(FreeInst &I) { 2815 std::vector<std::pair<SDOperand, const Type*> > Args; 2816 Args.push_back(std::make_pair(getValue(I.getOperand(0)), 2817 TLI.getTargetData()->getIntPtrType())); 2818 MVT::ValueType IntPtr = TLI.getPointerTy(); 2819 std::pair<SDOperand,SDOperand> Result = 2820 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, 2821 DAG.getExternalSymbol("free", IntPtr), Args, DAG); 2822 DAG.setRoot(Result.second); 2823} 2824 2825// InsertAtEndOfBasicBlock - This method should be implemented by targets that 2826// mark instructions with the 'usesCustomDAGSchedInserter' flag. These 2827// instructions are special in various ways, which require special support to 2828// insert. The specified MachineInstr is created but not inserted into any 2829// basic blocks, and the scheduler passes ownership of it to this method. 2830MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2831 MachineBasicBlock *MBB) { 2832 cerr << "If a target marks an instruction with " 2833 << "'usesCustomDAGSchedInserter', it must implement " 2834 << "TargetLowering::InsertAtEndOfBasicBlock!\n"; 2835 abort(); 2836 return 0; 2837} 2838 2839void SelectionDAGLowering::visitVAStart(CallInst &I) { 2840 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), 2841 getValue(I.getOperand(1)), 2842 DAG.getSrcValue(I.getOperand(1)))); 2843} 2844 2845void SelectionDAGLowering::visitVAArg(VAArgInst &I) { 2846 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), 2847 getValue(I.getOperand(0)), 2848 DAG.getSrcValue(I.getOperand(0))); 2849 setValue(&I, V); 2850 DAG.setRoot(V.getValue(1)); 2851} 2852 2853void SelectionDAGLowering::visitVAEnd(CallInst &I) { 2854 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), 2855 getValue(I.getOperand(1)), 2856 DAG.getSrcValue(I.getOperand(1)))); 2857} 2858 2859void SelectionDAGLowering::visitVACopy(CallInst &I) { 2860 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), 2861 getValue(I.getOperand(1)), 2862 getValue(I.getOperand(2)), 2863 DAG.getSrcValue(I.getOperand(1)), 2864 DAG.getSrcValue(I.getOperand(2)))); 2865} 2866 2867/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either 2868/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate. 2869static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg, 2870 unsigned &i, SelectionDAG &DAG, 2871 TargetLowering &TLI) { 2872 if (TLI.getTypeAction(VT) != TargetLowering::Expand) 2873 return SDOperand(Arg, i++); 2874 2875 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 2876 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 2877 if (NumVals == 1) { 2878 return DAG.getNode(ISD::BIT_CONVERT, VT, 2879 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI)); 2880 } else if (NumVals == 2) { 2881 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 2882 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); 2883 if (!TLI.isLittleEndian()) 2884 std::swap(Lo, Hi); 2885 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 2886 } else { 2887 // Value scalarized into many values. Unimp for now. 2888 assert(0 && "Cannot expand i64 -> i16 yet!"); 2889 } 2890 return SDOperand(); 2891} 2892 2893/// TargetLowering::LowerArguments - This is the default LowerArguments 2894/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all 2895/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be 2896/// integrated into SDISel. 2897std::vector<SDOperand> 2898TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 2899 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. 2900 std::vector<SDOperand> Ops; 2901 Ops.push_back(DAG.getRoot()); 2902 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); 2903 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); 2904 2905 // Add one result value for each formal argument. 2906 std::vector<MVT::ValueType> RetVals; 2907 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2908 MVT::ValueType VT = getValueType(I->getType()); 2909 2910 switch (getTypeAction(VT)) { 2911 default: assert(0 && "Unknown type action!"); 2912 case Legal: 2913 RetVals.push_back(VT); 2914 break; 2915 case Promote: 2916 RetVals.push_back(getTypeToTransformTo(VT)); 2917 break; 2918 case Expand: 2919 if (VT != MVT::Vector) { 2920 // If this is a large integer, it needs to be broken up into small 2921 // integers. Figure out what the destination type is and how many small 2922 // integers it turns into. 2923 MVT::ValueType NVT = getTypeToExpandTo(VT); 2924 unsigned NumVals = getNumElements(VT); 2925 for (unsigned i = 0; i != NumVals; ++i) 2926 RetVals.push_back(NVT); 2927 } else { 2928 // Otherwise, this is a vector type. We only support legal vectors 2929 // right now. 2930 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements(); 2931 const Type *EltTy = cast<PackedType>(I->getType())->getElementType(); 2932 2933 // Figure out if there is a Packed type corresponding to this Vector 2934 // type. If so, convert to the packed type. 2935 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2936 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2937 RetVals.push_back(TVT); 2938 } else { 2939 assert(0 && "Don't support illegal by-val vector arguments yet!"); 2940 } 2941 } 2942 break; 2943 } 2944 } 2945 2946 RetVals.push_back(MVT::Other); 2947 2948 // Create the node. 2949 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, 2950 DAG.getNodeValueTypes(RetVals), RetVals.size(), 2951 &Ops[0], Ops.size()).Val; 2952 2953 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); 2954 2955 // Set up the return result vector. 2956 Ops.clear(); 2957 unsigned i = 0; 2958 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 2959 MVT::ValueType VT = getValueType(I->getType()); 2960 2961 switch (getTypeAction(VT)) { 2962 default: assert(0 && "Unknown type action!"); 2963 case Legal: 2964 Ops.push_back(SDOperand(Result, i++)); 2965 break; 2966 case Promote: { 2967 SDOperand Op(Result, i++); 2968 if (MVT::isInteger(VT)) { 2969 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 2970 : ISD::AssertZext; 2971 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT)); 2972 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2973 } else { 2974 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 2975 Op = DAG.getNode(ISD::FP_ROUND, VT, Op); 2976 } 2977 Ops.push_back(Op); 2978 break; 2979 } 2980 case Expand: 2981 if (VT != MVT::Vector) { 2982 // If this is a large integer or a floating point node that needs to be 2983 // expanded, it needs to be reassembled from small integers. Figure out 2984 // what the source elt type is and how many small integers it is. 2985 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this)); 2986 } else { 2987 // Otherwise, this is a vector type. We only support legal vectors 2988 // right now. 2989 const PackedType *PTy = cast<PackedType>(I->getType()); 2990 unsigned NumElems = PTy->getNumElements(); 2991 const Type *EltTy = PTy->getElementType(); 2992 2993 // Figure out if there is a Packed type corresponding to this Vector 2994 // type. If so, convert to the packed type. 2995 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 2996 if (TVT != MVT::Other && isTypeLegal(TVT)) { 2997 SDOperand N = SDOperand(Result, i++); 2998 // Handle copies from generic vectors to registers. 2999 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, 3000 DAG.getConstant(NumElems, MVT::i32), 3001 DAG.getValueType(getValueType(EltTy))); 3002 Ops.push_back(N); 3003 } else { 3004 assert(0 && "Don't support illegal by-val vector arguments yet!"); 3005 abort(); 3006 } 3007 } 3008 break; 3009 } 3010 } 3011 return Ops; 3012} 3013 3014 3015/// ExpandScalarCallArgs - Recursively expand call argument node by 3016/// bit_converting it or extract a pair of elements from the larger node. 3017static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, 3018 bool isSigned, 3019 SmallVector<SDOperand, 32> &Ops, 3020 SelectionDAG &DAG, 3021 TargetLowering &TLI) { 3022 if (TLI.getTypeAction(VT) != TargetLowering::Expand) { 3023 Ops.push_back(Arg); 3024 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 3025 return; 3026 } 3027 3028 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); 3029 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); 3030 if (NumVals == 1) { 3031 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); 3032 ExpandScalarCallArgs(EVT, Arg, isSigned, Ops, DAG, TLI); 3033 } else if (NumVals == 2) { 3034 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3035 DAG.getConstant(0, TLI.getPointerTy())); 3036 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, 3037 DAG.getConstant(1, TLI.getPointerTy())); 3038 if (!TLI.isLittleEndian()) 3039 std::swap(Lo, Hi); 3040 ExpandScalarCallArgs(EVT, Lo, isSigned, Ops, DAG, TLI); 3041 ExpandScalarCallArgs(EVT, Hi, isSigned, Ops, DAG, TLI); 3042 } else { 3043 // Value scalarized into many values. Unimp for now. 3044 assert(0 && "Cannot expand i64 -> i16 yet!"); 3045 } 3046} 3047 3048/// TargetLowering::LowerCallTo - This is the default LowerCallTo 3049/// implementation, which just inserts an ISD::CALL node, which is later custom 3050/// lowered by the target to something concrete. FIXME: When all targets are 3051/// migrated to using ISD::CALL, this hook should be integrated into SDISel. 3052std::pair<SDOperand, SDOperand> 3053TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 3054 unsigned CallingConv, bool isTailCall, 3055 SDOperand Callee, 3056 ArgListTy &Args, SelectionDAG &DAG) { 3057 SmallVector<SDOperand, 32> Ops; 3058 Ops.push_back(Chain); // Op#0 - Chain 3059 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC 3060 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg 3061 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail 3062 Ops.push_back(Callee); 3063 3064 // Handle all of the outgoing arguments. 3065 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 3066 MVT::ValueType VT = getValueType(Args[i].second); 3067 SDOperand Op = Args[i].first; 3068 bool isSigned = Args[i].second->isSigned(); 3069 switch (getTypeAction(VT)) { 3070 default: assert(0 && "Unknown type action!"); 3071 case Legal: 3072 Ops.push_back(Op); 3073 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 3074 break; 3075 case Promote: 3076 if (MVT::isInteger(VT)) { 3077 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3078 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); 3079 } else { 3080 assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); 3081 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); 3082 } 3083 Ops.push_back(Op); 3084 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 3085 break; 3086 case Expand: 3087 if (VT != MVT::Vector) { 3088 // If this is a large integer, it needs to be broken down into small 3089 // integers. Figure out what the source elt type is and how many small 3090 // integers it is. 3091 ExpandScalarCallArgs(VT, Op, isSigned, Ops, DAG, *this); 3092 } else { 3093 // Otherwise, this is a vector type. We only support legal vectors 3094 // right now. 3095 const PackedType *PTy = cast<PackedType>(Args[i].second); 3096 unsigned NumElems = PTy->getNumElements(); 3097 const Type *EltTy = PTy->getElementType(); 3098 3099 // Figure out if there is a Packed type corresponding to this Vector 3100 // type. If so, convert to the packed type. 3101 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3102 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3103 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. 3104 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); 3105 Ops.push_back(Op); 3106 Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); 3107 } else { 3108 assert(0 && "Don't support illegal by-val vector call args yet!"); 3109 abort(); 3110 } 3111 } 3112 break; 3113 } 3114 } 3115 3116 // Figure out the result value types. 3117 SmallVector<MVT::ValueType, 4> RetTys; 3118 3119 if (RetTy != Type::VoidTy) { 3120 MVT::ValueType VT = getValueType(RetTy); 3121 switch (getTypeAction(VT)) { 3122 default: assert(0 && "Unknown type action!"); 3123 case Legal: 3124 RetTys.push_back(VT); 3125 break; 3126 case Promote: 3127 RetTys.push_back(getTypeToTransformTo(VT)); 3128 break; 3129 case Expand: 3130 if (VT != MVT::Vector) { 3131 // If this is a large integer, it needs to be reassembled from small 3132 // integers. Figure out what the source elt type is and how many small 3133 // integers it is. 3134 MVT::ValueType NVT = getTypeToExpandTo(VT); 3135 unsigned NumVals = getNumElements(VT); 3136 for (unsigned i = 0; i != NumVals; ++i) 3137 RetTys.push_back(NVT); 3138 } else { 3139 // Otherwise, this is a vector type. We only support legal vectors 3140 // right now. 3141 const PackedType *PTy = cast<PackedType>(RetTy); 3142 unsigned NumElems = PTy->getNumElements(); 3143 const Type *EltTy = PTy->getElementType(); 3144 3145 // Figure out if there is a Packed type corresponding to this Vector 3146 // type. If so, convert to the packed type. 3147 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3148 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3149 RetTys.push_back(TVT); 3150 } else { 3151 assert(0 && "Don't support illegal by-val vector call results yet!"); 3152 abort(); 3153 } 3154 } 3155 } 3156 } 3157 3158 RetTys.push_back(MVT::Other); // Always has a chain. 3159 3160 // Finally, create the CALL node. 3161 SDOperand Res = DAG.getNode(ISD::CALL, 3162 DAG.getVTList(&RetTys[0], RetTys.size()), 3163 &Ops[0], Ops.size()); 3164 3165 // This returns a pair of operands. The first element is the 3166 // return value for the function (if RetTy is not VoidTy). The second 3167 // element is the outgoing token chain. 3168 SDOperand ResVal; 3169 if (RetTys.size() != 1) { 3170 MVT::ValueType VT = getValueType(RetTy); 3171 if (RetTys.size() == 2) { 3172 ResVal = Res; 3173 3174 // If this value was promoted, truncate it down. 3175 if (ResVal.getValueType() != VT) { 3176 if (VT == MVT::Vector) { 3177 // Insert a VBITCONVERT to convert from the packed result type to the 3178 // MVT::Vector type. 3179 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements(); 3180 const Type *EltTy = cast<PackedType>(RetTy)->getElementType(); 3181 3182 // Figure out if there is a Packed type corresponding to this Vector 3183 // type. If so, convert to the packed type. 3184 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); 3185 if (TVT != MVT::Other && isTypeLegal(TVT)) { 3186 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a 3187 // "N x PTyElementVT" MVT::Vector type. 3188 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, 3189 DAG.getConstant(NumElems, MVT::i32), 3190 DAG.getValueType(getValueType(EltTy))); 3191 } else { 3192 abort(); 3193 } 3194 } else if (MVT::isInteger(VT)) { 3195 unsigned AssertOp = RetTy->isSigned() ? 3196 ISD::AssertSext : ISD::AssertZext; 3197 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, 3198 DAG.getValueType(VT)); 3199 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); 3200 } else { 3201 assert(MVT::isFloatingPoint(VT)); 3202 if (getTypeAction(VT) == Expand) 3203 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal); 3204 else 3205 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); 3206 } 3207 } 3208 } else if (RetTys.size() == 3) { 3209 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, 3210 Res.getValue(0), Res.getValue(1)); 3211 3212 } else { 3213 assert(0 && "Case not handled yet!"); 3214 } 3215 } 3216 3217 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); 3218} 3219 3220 3221 3222// It is always conservatively correct for llvm.returnaddress and 3223// llvm.frameaddress to return 0. 3224// 3225// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be 3226// expanded to 0 if the target wants. 3227std::pair<SDOperand, SDOperand> 3228TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, 3229 unsigned Depth, SelectionDAG &DAG) { 3230 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain); 3231} 3232 3233SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3234 assert(0 && "LowerOperation not implemented for this target!"); 3235 abort(); 3236 return SDOperand(); 3237} 3238 3239SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, 3240 SelectionDAG &DAG) { 3241 assert(0 && "CustomPromoteOperation not implemented for this target!"); 3242 abort(); 3243 return SDOperand(); 3244} 3245 3246void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) { 3247 unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue(); 3248 std::pair<SDOperand,SDOperand> Result = 3249 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG); 3250 setValue(&I, Result.first); 3251 DAG.setRoot(Result.second); 3252} 3253 3254/// getMemsetValue - Vectorized representation of the memset value 3255/// operand. 3256static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, 3257 SelectionDAG &DAG) { 3258 MVT::ValueType CurVT = VT; 3259 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 3260 uint64_t Val = C->getValue() & 255; 3261 unsigned Shift = 8; 3262 while (CurVT != MVT::i8) { 3263 Val = (Val << Shift) | Val; 3264 Shift <<= 1; 3265 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 3266 } 3267 return DAG.getConstant(Val, VT); 3268 } else { 3269 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 3270 unsigned Shift = 8; 3271 while (CurVT != MVT::i8) { 3272 Value = 3273 DAG.getNode(ISD::OR, VT, 3274 DAG.getNode(ISD::SHL, VT, Value, 3275 DAG.getConstant(Shift, MVT::i8)), Value); 3276 Shift <<= 1; 3277 CurVT = (MVT::ValueType)((unsigned)CurVT - 1); 3278 } 3279 3280 return Value; 3281 } 3282} 3283 3284/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 3285/// used when a memcpy is turned into a memset when the source is a constant 3286/// string ptr. 3287static SDOperand getMemsetStringVal(MVT::ValueType VT, 3288 SelectionDAG &DAG, TargetLowering &TLI, 3289 std::string &Str, unsigned Offset) { 3290 uint64_t Val = 0; 3291 unsigned MSB = getSizeInBits(VT) / 8; 3292 if (TLI.isLittleEndian()) 3293 Offset = Offset + MSB - 1; 3294 for (unsigned i = 0; i != MSB; ++i) { 3295 Val = (Val << 8) | (unsigned char)Str[Offset]; 3296 Offset += TLI.isLittleEndian() ? -1 : 1; 3297 } 3298 return DAG.getConstant(Val, VT); 3299} 3300 3301/// getMemBasePlusOffset - Returns base and offset node for the 3302static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, 3303 SelectionDAG &DAG, TargetLowering &TLI) { 3304 MVT::ValueType VT = Base.getValueType(); 3305 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 3306} 3307 3308/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3309/// to replace the memset / memcpy is below the threshold. It also returns the 3310/// types of the sequence of memory ops to perform memset / memcpy. 3311static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, 3312 unsigned Limit, uint64_t Size, 3313 unsigned Align, TargetLowering &TLI) { 3314 MVT::ValueType VT; 3315 3316 if (TLI.allowsUnalignedMemoryAccesses()) { 3317 VT = MVT::i64; 3318 } else { 3319 switch (Align & 7) { 3320 case 0: 3321 VT = MVT::i64; 3322 break; 3323 case 4: 3324 VT = MVT::i32; 3325 break; 3326 case 2: 3327 VT = MVT::i16; 3328 break; 3329 default: 3330 VT = MVT::i8; 3331 break; 3332 } 3333 } 3334 3335 MVT::ValueType LVT = MVT::i64; 3336 while (!TLI.isTypeLegal(LVT)) 3337 LVT = (MVT::ValueType)((unsigned)LVT - 1); 3338 assert(MVT::isInteger(LVT)); 3339 3340 if (VT > LVT) 3341 VT = LVT; 3342 3343 unsigned NumMemOps = 0; 3344 while (Size != 0) { 3345 unsigned VTSize = getSizeInBits(VT) / 8; 3346 while (VTSize > Size) { 3347 VT = (MVT::ValueType)((unsigned)VT - 1); 3348 VTSize >>= 1; 3349 } 3350 assert(MVT::isInteger(VT)); 3351 3352 if (++NumMemOps > Limit) 3353 return false; 3354 MemOps.push_back(VT); 3355 Size -= VTSize; 3356 } 3357 3358 return true; 3359} 3360 3361void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { 3362 SDOperand Op1 = getValue(I.getOperand(1)); 3363 SDOperand Op2 = getValue(I.getOperand(2)); 3364 SDOperand Op3 = getValue(I.getOperand(3)); 3365 SDOperand Op4 = getValue(I.getOperand(4)); 3366 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue(); 3367 if (Align == 0) Align = 1; 3368 3369 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) { 3370 std::vector<MVT::ValueType> MemOps; 3371 3372 // Expand memset / memcpy to a series of load / store ops 3373 // if the size operand falls below a certain threshold. 3374 SmallVector<SDOperand, 8> OutChains; 3375 switch (Op) { 3376 default: break; // Do nothing for now. 3377 case ISD::MEMSET: { 3378 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(), 3379 Size->getValue(), Align, TLI)) { 3380 unsigned NumMemOps = MemOps.size(); 3381 unsigned Offset = 0; 3382 for (unsigned i = 0; i < NumMemOps; i++) { 3383 MVT::ValueType VT = MemOps[i]; 3384 unsigned VTSize = getSizeInBits(VT) / 8; 3385 SDOperand Value = getMemsetValue(Op2, VT, DAG); 3386 SDOperand Store = DAG.getStore(getRoot(), Value, 3387 getMemBasePlusOffset(Op1, Offset, DAG, TLI), 3388 I.getOperand(1), Offset); 3389 OutChains.push_back(Store); 3390 Offset += VTSize; 3391 } 3392 } 3393 break; 3394 } 3395 case ISD::MEMCPY: { 3396 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(), 3397 Size->getValue(), Align, TLI)) { 3398 unsigned NumMemOps = MemOps.size(); 3399 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0; 3400 GlobalAddressSDNode *G = NULL; 3401 std::string Str; 3402 bool CopyFromStr = false; 3403 3404 if (Op2.getOpcode() == ISD::GlobalAddress) 3405 G = cast<GlobalAddressSDNode>(Op2); 3406 else if (Op2.getOpcode() == ISD::ADD && 3407 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress && 3408 Op2.getOperand(1).getOpcode() == ISD::Constant) { 3409 G = cast<GlobalAddressSDNode>(Op2.getOperand(0)); 3410 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue(); 3411 } 3412 if (G) { 3413 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3414 if (GV && GV->isConstant()) { 3415 Str = GV->getStringValue(false); 3416 if (!Str.empty()) { 3417 CopyFromStr = true; 3418 SrcOff += SrcDelta; 3419 } 3420 } 3421 } 3422 3423 for (unsigned i = 0; i < NumMemOps; i++) { 3424 MVT::ValueType VT = MemOps[i]; 3425 unsigned VTSize = getSizeInBits(VT) / 8; 3426 SDOperand Value, Chain, Store; 3427 3428 if (CopyFromStr) { 3429 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 3430 Chain = getRoot(); 3431 Store = 3432 DAG.getStore(Chain, Value, 3433 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 3434 I.getOperand(1), DstOff); 3435 } else { 3436 Value = DAG.getLoad(VT, getRoot(), 3437 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), 3438 I.getOperand(2), SrcOff); 3439 Chain = Value.getValue(1); 3440 Store = 3441 DAG.getStore(Chain, Value, 3442 getMemBasePlusOffset(Op1, DstOff, DAG, TLI), 3443 I.getOperand(1), DstOff); 3444 } 3445 OutChains.push_back(Store); 3446 SrcOff += VTSize; 3447 DstOff += VTSize; 3448 } 3449 } 3450 break; 3451 } 3452 } 3453 3454 if (!OutChains.empty()) { 3455 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 3456 &OutChains[0], OutChains.size())); 3457 return; 3458 } 3459 } 3460 3461 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4)); 3462} 3463 3464//===----------------------------------------------------------------------===// 3465// SelectionDAGISel code 3466//===----------------------------------------------------------------------===// 3467 3468unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { 3469 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); 3470} 3471 3472void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 3473 // FIXME: we only modify the CFG to split critical edges. This 3474 // updates dom and loop info. 3475 AU.addRequired<AliasAnalysis>(); 3476} 3477 3478 3479/// OptimizeNoopCopyExpression - We have determined that the specified cast 3480/// instruction is a noop copy (e.g. it's casting from one pointer type to 3481/// another, int->uint, or int->sbyte on PPC. 3482/// 3483/// Return true if any changes are made. 3484static bool OptimizeNoopCopyExpression(CastInst *CI) { 3485 BasicBlock *DefBB = CI->getParent(); 3486 3487 /// InsertedCasts - Only insert a cast in each block once. 3488 std::map<BasicBlock*, CastInst*> InsertedCasts; 3489 3490 bool MadeChange = false; 3491 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); 3492 UI != E; ) { 3493 Use &TheUse = UI.getUse(); 3494 Instruction *User = cast<Instruction>(*UI); 3495 3496 // Figure out which BB this cast is used in. For PHI's this is the 3497 // appropriate predecessor block. 3498 BasicBlock *UserBB = User->getParent(); 3499 if (PHINode *PN = dyn_cast<PHINode>(User)) { 3500 unsigned OpVal = UI.getOperandNo()/2; 3501 UserBB = PN->getIncomingBlock(OpVal); 3502 } 3503 3504 // Preincrement use iterator so we don't invalidate it. 3505 ++UI; 3506 3507 // If this user is in the same block as the cast, don't change the cast. 3508 if (UserBB == DefBB) continue; 3509 3510 // If we have already inserted a cast into this block, use it. 3511 CastInst *&InsertedCast = InsertedCasts[UserBB]; 3512 3513 if (!InsertedCast) { 3514 BasicBlock::iterator InsertPt = UserBB->begin(); 3515 while (isa<PHINode>(InsertPt)) ++InsertPt; 3516 3517 InsertedCast = 3518 CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "", 3519 InsertPt); 3520 MadeChange = true; 3521 } 3522 3523 // Replace a use of the cast with a use of the new casat. 3524 TheUse = InsertedCast; 3525 } 3526 3527 // If we removed all uses, nuke the cast. 3528 if (CI->use_empty()) 3529 CI->eraseFromParent(); 3530 3531 return MadeChange; 3532} 3533 3534/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, 3535/// casting to the type of GEPI. 3536static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB, 3537 Instruction *GEPI, Value *Ptr, 3538 Value *PtrOffset) { 3539 if (V) return V; // Already computed. 3540 3541 // Figure out the insertion point 3542 BasicBlock::iterator InsertPt; 3543 if (BB == GEPI->getParent()) { 3544 // If GEP is already inserted into BB, insert right after the GEP. 3545 InsertPt = GEPI; 3546 ++InsertPt; 3547 } else { 3548 // Otherwise, insert at the top of BB, after any PHI nodes 3549 InsertPt = BB->begin(); 3550 while (isa<PHINode>(InsertPt)) ++InsertPt; 3551 } 3552 3553 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into 3554 // BB so that there is only one value live across basic blocks (the cast 3555 // operand). 3556 if (CastInst *CI = dyn_cast<CastInst>(Ptr)) 3557 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType())) 3558 Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), 3559 "", InsertPt); 3560 3561 // Add the offset, cast it to the right type. 3562 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); 3563 // Ptr is an integer type, GEPI is pointer type ==> IntToPtr 3564 return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI->getType(), 3565 "", InsertPt); 3566} 3567 3568/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to 3569/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One 3570/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's 3571/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to 3572/// sink PtrOffset into user blocks where doing so will likely allow us to fold 3573/// the constant add into a load or store instruction. Additionally, if a user 3574/// is a pointer-pointer cast, we look through it to find its users. 3575static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, 3576 Constant *PtrOffset, BasicBlock *DefBB, 3577 GetElementPtrInst *GEPI, 3578 std::map<BasicBlock*,Instruction*> &InsertedExprs) { 3579 while (!RepPtr->use_empty()) { 3580 Instruction *User = cast<Instruction>(RepPtr->use_back()); 3581 3582 // If the user is a Pointer-Pointer cast, recurse. Only BitCast can be 3583 // used for a Pointer-Pointer cast. 3584 if (isa<BitCastInst>(User)) { 3585 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3586 3587 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we 3588 // could invalidate an iterator. 3589 User->setOperand(0, UndefValue::get(RepPtr->getType())); 3590 continue; 3591 } 3592 3593 // If this is a load of the pointer, or a store through the pointer, emit 3594 // the increment into the load/store block. 3595 Instruction *NewVal; 3596 if (isa<LoadInst>(User) || 3597 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) { 3598 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], 3599 User->getParent(), GEPI, 3600 Ptr, PtrOffset); 3601 } else { 3602 // If this use is not foldable into the addressing mode, use a version 3603 // emitted in the GEP block. 3604 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, 3605 Ptr, PtrOffset); 3606 } 3607 3608 if (GEPI->getType() != RepPtr->getType()) { 3609 BasicBlock::iterator IP = NewVal; 3610 ++IP; 3611 // NewVal must be a GEP which must be pointer type, so BitCast 3612 NewVal = new BitCastInst(NewVal, RepPtr->getType(), "", IP); 3613 } 3614 User->replaceUsesOfWith(RepPtr, NewVal); 3615 } 3616} 3617 3618 3619/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction 3620/// selection, we want to be a bit careful about some things. In particular, if 3621/// we have a GEP instruction that is used in a different block than it is 3622/// defined, the addressing expression of the GEP cannot be folded into loads or 3623/// stores that use it. In this case, decompose the GEP and move constant 3624/// indices into blocks that use it. 3625static bool OptimizeGEPExpression(GetElementPtrInst *GEPI, 3626 const TargetData *TD) { 3627 // If this GEP is only used inside the block it is defined in, there is no 3628 // need to rewrite it. 3629 bool isUsedOutsideDefBB = false; 3630 BasicBlock *DefBB = GEPI->getParent(); 3631 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end(); 3632 UI != E; ++UI) { 3633 if (cast<Instruction>(*UI)->getParent() != DefBB) { 3634 isUsedOutsideDefBB = true; 3635 break; 3636 } 3637 } 3638 if (!isUsedOutsideDefBB) return false; 3639 3640 // If this GEP has no non-zero constant indices, there is nothing we can do, 3641 // ignore it. 3642 bool hasConstantIndex = false; 3643 bool hasVariableIndex = false; 3644 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3645 E = GEPI->op_end(); OI != E; ++OI) { 3646 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) { 3647 if (CI->getZExtValue()) { 3648 hasConstantIndex = true; 3649 break; 3650 } 3651 } else { 3652 hasVariableIndex = true; 3653 } 3654 } 3655 3656 // If this is a "GEP X, 0, 0, 0", turn this into a cast. 3657 if (!hasConstantIndex && !hasVariableIndex) { 3658 /// The GEP operand must be a pointer, so must its result -> BitCast 3659 Value *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(), 3660 GEPI->getName(), GEPI); 3661 GEPI->replaceAllUsesWith(NC); 3662 GEPI->eraseFromParent(); 3663 return true; 3664 } 3665 3666 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses. 3667 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) 3668 return false; 3669 3670 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the 3671 // constant offset (which we now know is non-zero) and deal with it later. 3672 uint64_t ConstantOffset = 0; 3673 const Type *UIntPtrTy = TD->getIntPtrType(); 3674 Value *Ptr = new PtrToIntInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI); 3675 const Type *Ty = GEPI->getOperand(0)->getType(); 3676 3677 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, 3678 E = GEPI->op_end(); OI != E; ++OI) { 3679 Value *Idx = *OI; 3680 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 3681 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3682 if (Field) 3683 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field]; 3684 Ty = StTy->getElementType(Field); 3685 } else { 3686 Ty = cast<SequentialType>(Ty)->getElementType(); 3687 3688 // Handle constant subscripts. 3689 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3690 if (CI->getZExtValue() == 0) continue; 3691 if (CI->getType()->isSigned()) 3692 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue(); 3693 else 3694 ConstantOffset += TD->getTypeSize(Ty)*CI->getZExtValue(); 3695 continue; 3696 } 3697 3698 // Ptr = Ptr + Idx * ElementSize; 3699 3700 // Cast Idx to UIntPtrTy if needed. 3701 Idx = CastInst::createIntegerCast(Idx, UIntPtrTy, true/*SExt*/, "", GEPI); 3702 3703 uint64_t ElementSize = TD->getTypeSize(Ty); 3704 // Mask off bits that should not be set. 3705 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3706 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize); 3707 3708 // Multiply by the element size and add to the base. 3709 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI); 3710 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI); 3711 } 3712 } 3713 3714 // Make sure that the offset fits in uintptr_t. 3715 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); 3716 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset); 3717 3718 // Okay, we have now emitted all of the variable index parts to the BB that 3719 // the GEP is defined in. Loop over all of the using instructions, inserting 3720 // an "add Ptr, ConstantOffset" into each block that uses it and update the 3721 // instruction to use the newly computed value, making GEPI dead. When the 3722 // user is a load or store instruction address, we emit the add into the user 3723 // block, otherwise we use a canonical version right next to the gep (these 3724 // won't be foldable as addresses, so we might as well share the computation). 3725 3726 std::map<BasicBlock*,Instruction*> InsertedExprs; 3727 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); 3728 3729 // Finally, the GEP is dead, remove it. 3730 GEPI->eraseFromParent(); 3731 3732 return true; 3733} 3734 3735 3736/// SplitEdgeNicely - Split the critical edge from TI to it's specified 3737/// successor if it will improve codegen. We only do this if the successor has 3738/// phi nodes (otherwise critical edges are ok). If there is already another 3739/// predecessor of the succ that is empty (and thus has no phi nodes), use it 3740/// instead of introducing a new block. 3741static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) { 3742 BasicBlock *TIBB = TI->getParent(); 3743 BasicBlock *Dest = TI->getSuccessor(SuccNum); 3744 assert(isa<PHINode>(Dest->begin()) && 3745 "This should only be called if Dest has a PHI!"); 3746 3747 /// TIPHIValues - This array is lazily computed to determine the values of 3748 /// PHIs in Dest that TI would provide. 3749 std::vector<Value*> TIPHIValues; 3750 3751 // Check to see if Dest has any blocks that can be used as a split edge for 3752 // this terminator. 3753 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) { 3754 BasicBlock *Pred = *PI; 3755 // To be usable, the pred has to end with an uncond branch to the dest. 3756 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator()); 3757 if (!PredBr || !PredBr->isUnconditional() || 3758 // Must be empty other than the branch. 3759 &Pred->front() != PredBr) 3760 continue; 3761 3762 // Finally, since we know that Dest has phi nodes in it, we have to make 3763 // sure that jumping to Pred will have the same affect as going to Dest in 3764 // terms of PHI values. 3765 PHINode *PN; 3766 unsigned PHINo = 0; 3767 bool FoundMatch = true; 3768 for (BasicBlock::iterator I = Dest->begin(); 3769 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) { 3770 if (PHINo == TIPHIValues.size()) 3771 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB)); 3772 3773 // If the PHI entry doesn't work, we can't use this pred. 3774 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) { 3775 FoundMatch = false; 3776 break; 3777 } 3778 } 3779 3780 // If we found a workable predecessor, change TI to branch to Succ. 3781 if (FoundMatch) { 3782 Dest->removePredecessor(TIBB); 3783 TI->setSuccessor(SuccNum, Pred); 3784 return; 3785 } 3786 } 3787 3788 SplitCriticalEdge(TI, SuccNum, P, true); 3789} 3790 3791 3792bool SelectionDAGISel::runOnFunction(Function &Fn) { 3793 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); 3794 RegMap = MF.getSSARegMap(); 3795 DOUT << "\n\n\n=== " << Fn.getName() << "\n"; 3796 3797 // First, split all critical edges. 3798 // 3799 // In this pass we also look for GEP and cast instructions that are used 3800 // across basic blocks and rewrite them to improve basic-block-at-a-time 3801 // selection. 3802 // 3803 bool MadeChange = true; 3804 while (MadeChange) { 3805 MadeChange = false; 3806 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 3807 // Split all critical edges where the dest block has a PHI. 3808 TerminatorInst *BBTI = BB->getTerminator(); 3809 if (BBTI->getNumSuccessors() > 1) { 3810 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i) 3811 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) && 3812 isCriticalEdge(BBTI, i, true)) 3813 SplitEdgeNicely(BBTI, i, this); 3814 } 3815 3816 3817 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) { 3818 Instruction *I = BBI++; 3819 3820 if (CallInst *CI = dyn_cast<CallInst>(I)) { 3821 // If we found an inline asm expession, and if the target knows how to 3822 // lower it to normal LLVM code, do so now. 3823 if (isa<InlineAsm>(CI->getCalledValue())) 3824 if (const TargetAsmInfo *TAI = 3825 TLI.getTargetMachine().getTargetAsmInfo()) { 3826 if (TAI->ExpandInlineAsm(CI)) 3827 BBI = BB->begin(); 3828 } 3829 } else if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) { 3830 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData()); 3831 } else if (CastInst *CI = dyn_cast<CastInst>(I)) { 3832 // If the source of the cast is a constant, then this should have 3833 // already been constant folded. The only reason NOT to constant fold 3834 // it is if something (e.g. LSR) was careful to place the constant 3835 // evaluation in a block other than then one that uses it (e.g. to hoist 3836 // the address of globals out of a loop). If this is the case, we don't 3837 // want to forward-subst the cast. 3838 if (isa<Constant>(CI->getOperand(0))) 3839 continue; 3840 3841 // If this is a noop copy, sink it into user blocks to reduce the number 3842 // of virtual registers that must be created and coallesced. 3843 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); 3844 MVT::ValueType DstVT = TLI.getValueType(CI->getType()); 3845 3846 // This is an fp<->int conversion? 3847 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) 3848 continue; 3849 3850 // If this is an extension, it will be a zero or sign extension, which 3851 // isn't a noop. 3852 if (SrcVT < DstVT) continue; 3853 3854 // If these values will be promoted, find out what they will be promoted 3855 // to. This helps us consider truncates on PPC as noop copies when they 3856 // are. 3857 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) 3858 SrcVT = TLI.getTypeToTransformTo(SrcVT); 3859 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) 3860 DstVT = TLI.getTypeToTransformTo(DstVT); 3861 3862 // If, after promotion, these are the same types, this is a noop copy. 3863 if (SrcVT == DstVT) 3864 MadeChange |= OptimizeNoopCopyExpression(CI); 3865 } 3866 } 3867 } 3868 } 3869 3870 FunctionLoweringInfo FuncInfo(TLI, Fn, MF); 3871 3872 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 3873 SelectBasicBlock(I, MF, FuncInfo); 3874 3875 return true; 3876} 3877 3878SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, 3879 unsigned Reg) { 3880 SDOperand Op = getValue(V); 3881 assert((Op.getOpcode() != ISD::CopyFromReg || 3882 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 3883 "Copy from a reg to the same reg!"); 3884 3885 // If this type is not legal, we must make sure to not create an invalid 3886 // register use. 3887 MVT::ValueType SrcVT = Op.getValueType(); 3888 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT); 3889 if (SrcVT == DestVT) { 3890 return DAG.getCopyToReg(getRoot(), Reg, Op); 3891 } else if (SrcVT == MVT::Vector) { 3892 // Handle copies from generic vectors to registers. 3893 MVT::ValueType PTyElementVT, PTyLegalElementVT; 3894 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()), 3895 PTyElementVT, PTyLegalElementVT); 3896 3897 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 3898 // MVT::Vector type. 3899 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, 3900 DAG.getConstant(NE, MVT::i32), 3901 DAG.getValueType(PTyElementVT)); 3902 3903 // Loop over all of the elements of the resultant vector, 3904 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then 3905 // copying them into output registers. 3906 SmallVector<SDOperand, 8> OutChains; 3907 SDOperand Root = getRoot(); 3908 for (unsigned i = 0; i != NE; ++i) { 3909 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, 3910 Op, DAG.getConstant(i, TLI.getPointerTy())); 3911 if (PTyElementVT == PTyLegalElementVT) { 3912 // Elements are legal. 3913 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3914 } else if (PTyLegalElementVT > PTyElementVT) { 3915 // Elements are promoted. 3916 if (MVT::isFloatingPoint(PTyLegalElementVT)) 3917 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt); 3918 else 3919 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt); 3920 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); 3921 } else { 3922 // Elements are expanded. 3923 // The src value is expanded into multiple registers. 3924 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3925 Elt, DAG.getConstant(0, TLI.getPointerTy())); 3926 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, 3927 Elt, DAG.getConstant(1, TLI.getPointerTy())); 3928 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); 3929 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); 3930 } 3931 } 3932 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3933 &OutChains[0], OutChains.size()); 3934 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) { 3935 // The src value is promoted to the register. 3936 if (MVT::isFloatingPoint(SrcVT)) 3937 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op); 3938 else 3939 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); 3940 return DAG.getCopyToReg(getRoot(), Reg, Op); 3941 } else { 3942 DestVT = TLI.getTypeToExpandTo(SrcVT); 3943 unsigned NumVals = TLI.getNumElements(SrcVT); 3944 if (NumVals == 1) 3945 return DAG.getCopyToReg(getRoot(), Reg, 3946 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); 3947 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!"); 3948 // The src value is expanded into multiple registers. 3949 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3950 Op, DAG.getConstant(0, TLI.getPointerTy())); 3951 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, 3952 Op, DAG.getConstant(1, TLI.getPointerTy())); 3953 Op = DAG.getCopyToReg(getRoot(), Reg, Lo); 3954 return DAG.getCopyToReg(Op, Reg+1, Hi); 3955 } 3956} 3957 3958void SelectionDAGISel:: 3959LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 3960 std::vector<SDOperand> &UnorderedChains) { 3961 // If this is the entry block, emit arguments. 3962 Function &F = *BB->getParent(); 3963 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo; 3964 SDOperand OldRoot = SDL.DAG.getRoot(); 3965 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG); 3966 3967 unsigned a = 0; 3968 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); 3969 AI != E; ++AI, ++a) 3970 if (!AI->use_empty()) { 3971 SDL.setValue(AI, Args[a]); 3972 3973 // If this argument is live outside of the entry block, insert a copy from 3974 // whereever we got it to the vreg that other BB's will reference it as. 3975 if (FuncInfo.ValueMap.count(AI)) { 3976 SDOperand Copy = 3977 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]); 3978 UnorderedChains.push_back(Copy); 3979 } 3980 } 3981 3982 // Finally, if the target has anything special to do, allow it to do so. 3983 // FIXME: this should insert code into the DAG! 3984 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); 3985} 3986 3987void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 3988 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 3989 FunctionLoweringInfo &FuncInfo) { 3990 SelectionDAGLowering SDL(DAG, TLI, FuncInfo); 3991 3992 std::vector<SDOperand> UnorderedChains; 3993 3994 // Lower any arguments needed in this block if this is the entry block. 3995 if (LLVMBB == &LLVMBB->getParent()->front()) 3996 LowerArguments(LLVMBB, SDL, UnorderedChains); 3997 3998 BB = FuncInfo.MBBMap[LLVMBB]; 3999 SDL.setCurrentBasicBlock(BB); 4000 4001 // Lower all of the non-terminator instructions. 4002 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end(); 4003 I != E; ++I) 4004 SDL.visit(*I); 4005 4006 // Ensure that all instructions which are used outside of their defining 4007 // blocks are available as virtual registers. 4008 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I) 4009 if (!I->use_empty() && !isa<PHINode>(I)) { 4010 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I); 4011 if (VMI != FuncInfo.ValueMap.end()) 4012 UnorderedChains.push_back( 4013 SDL.CopyValueToVirtualRegister(I, VMI->second)); 4014 } 4015 4016 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 4017 // ensure constants are generated when needed. Remember the virtual registers 4018 // that need to be added to the Machine PHI nodes as input. We cannot just 4019 // directly add them, because expansion might result in multiple MBB's for one 4020 // BB. As such, the start of the BB might correspond to a different MBB than 4021 // the end. 4022 // 4023 TerminatorInst *TI = LLVMBB->getTerminator(); 4024 4025 // Emit constants only once even if used by multiple PHI nodes. 4026 std::map<Constant*, unsigned> ConstantsOut; 4027 4028 // Vector bool would be better, but vector<bool> is really slow. 4029 std::vector<unsigned char> SuccsHandled; 4030 if (TI->getNumSuccessors()) 4031 SuccsHandled.resize(BB->getParent()->getNumBlockIDs()); 4032 4033 // Check successor nodes PHI nodes that expect a constant to be available from 4034 // this block. 4035 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 4036 BasicBlock *SuccBB = TI->getSuccessor(succ); 4037 if (!isa<PHINode>(SuccBB->begin())) continue; 4038 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 4039 4040 // If this terminator has multiple identical successors (common for 4041 // switches), only handle each succ once. 4042 unsigned SuccMBBNo = SuccMBB->getNumber(); 4043 if (SuccsHandled[SuccMBBNo]) continue; 4044 SuccsHandled[SuccMBBNo] = true; 4045 4046 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 4047 PHINode *PN; 4048 4049 // At this point we know that there is a 1-1 correspondence between LLVM PHI 4050 // nodes and Machine PHI nodes, but the incoming operands have not been 4051 // emitted yet. 4052 for (BasicBlock::iterator I = SuccBB->begin(); 4053 (PN = dyn_cast<PHINode>(I)); ++I) { 4054 // Ignore dead phi's. 4055 if (PN->use_empty()) continue; 4056 4057 unsigned Reg; 4058 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 4059 4060 if (Constant *C = dyn_cast<Constant>(PHIOp)) { 4061 unsigned &RegOut = ConstantsOut[C]; 4062 if (RegOut == 0) { 4063 RegOut = FuncInfo.CreateRegForValue(C); 4064 UnorderedChains.push_back( 4065 SDL.CopyValueToVirtualRegister(C, RegOut)); 4066 } 4067 Reg = RegOut; 4068 } else { 4069 Reg = FuncInfo.ValueMap[PHIOp]; 4070 if (Reg == 0) { 4071 assert(isa<AllocaInst>(PHIOp) && 4072 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 4073 "Didn't codegen value into a register!??"); 4074 Reg = FuncInfo.CreateRegForValue(PHIOp); 4075 UnorderedChains.push_back( 4076 SDL.CopyValueToVirtualRegister(PHIOp, Reg)); 4077 } 4078 } 4079 4080 // Remember that this register needs to added to the machine PHI node as 4081 // the input for this MBB. 4082 MVT::ValueType VT = TLI.getValueType(PN->getType()); 4083 unsigned NumElements; 4084 if (VT != MVT::Vector) 4085 NumElements = TLI.getNumElements(VT); 4086 else { 4087 MVT::ValueType VT1,VT2; 4088 NumElements = 4089 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()), 4090 VT1, VT2); 4091 } 4092 for (unsigned i = 0, e = NumElements; i != e; ++i) 4093 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 4094 } 4095 } 4096 ConstantsOut.clear(); 4097 4098 // Turn all of the unordered chains into one factored node. 4099 if (!UnorderedChains.empty()) { 4100 SDOperand Root = SDL.getRoot(); 4101 if (Root.getOpcode() != ISD::EntryToken) { 4102 unsigned i = 0, e = UnorderedChains.size(); 4103 for (; i != e; ++i) { 4104 assert(UnorderedChains[i].Val->getNumOperands() > 1); 4105 if (UnorderedChains[i].Val->getOperand(0) == Root) 4106 break; // Don't add the root if we already indirectly depend on it. 4107 } 4108 4109 if (i == e) 4110 UnorderedChains.push_back(Root); 4111 } 4112 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 4113 &UnorderedChains[0], UnorderedChains.size())); 4114 } 4115 4116 // Lower the terminator after the copies are emitted. 4117 SDL.visit(*LLVMBB->getTerminator()); 4118 4119 // Copy over any CaseBlock records that may now exist due to SwitchInst 4120 // lowering, as well as any jump table information. 4121 SwitchCases.clear(); 4122 SwitchCases = SDL.SwitchCases; 4123 JT = SDL.JT; 4124 4125 // Make sure the root of the DAG is up-to-date. 4126 DAG.setRoot(SDL.getRoot()); 4127} 4128 4129void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { 4130 // Get alias analysis for load/store combining. 4131 AliasAnalysis &AA = getAnalysis<AliasAnalysis>(); 4132 4133 // Run the DAG combiner in pre-legalize mode. 4134 DAG.Combine(false, AA); 4135 4136 DOUT << "Lowered selection DAG:\n"; 4137 DEBUG(DAG.dump()); 4138 4139 // Second step, hack on the DAG until it only uses operations and types that 4140 // the target supports. 4141 DAG.Legalize(); 4142 4143 DOUT << "Legalized selection DAG:\n"; 4144 DEBUG(DAG.dump()); 4145 4146 // Run the DAG combiner in post-legalize mode. 4147 DAG.Combine(true, AA); 4148 4149 if (ViewISelDAGs) DAG.viewGraph(); 4150 4151 // Third, instruction select all of the operations to machine code, adding the 4152 // code to the MachineBasicBlock. 4153 InstructionSelectBasicBlock(DAG); 4154 4155 DOUT << "Selected machine code:\n"; 4156 DEBUG(BB->dump()); 4157} 4158 4159void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, 4160 FunctionLoweringInfo &FuncInfo) { 4161 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 4162 { 4163 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 4164 CurDAG = &DAG; 4165 4166 // First step, lower LLVM code to some DAG. This DAG may use operations and 4167 // types that are not supported by the target. 4168 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo); 4169 4170 // Second step, emit the lowered DAG as machine code. 4171 CodeGenAndEmitDAG(DAG); 4172 } 4173 4174 // Next, now that we know what the last MBB the LLVM BB expanded is, update 4175 // PHI nodes in successors. 4176 if (SwitchCases.empty() && JT.Reg == 0) { 4177 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4178 MachineInstr *PHI = PHINodesToUpdate[i].first; 4179 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4180 "This is not a machine PHI node that we are updating!"); 4181 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4182 PHI->addMachineBasicBlockOperand(BB); 4183 } 4184 return; 4185 } 4186 4187 // If the JumpTable record is filled in, then we need to emit a jump table. 4188 // Updating the PHI nodes is tricky in this case, since we need to determine 4189 // whether the PHI is a successor of the range check MBB or the jump table MBB 4190 if (JT.Reg) { 4191 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch"); 4192 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 4193 CurDAG = &SDAG; 4194 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4195 MachineBasicBlock *RangeBB = BB; 4196 // Set the current basic block to the mbb we wish to insert the code into 4197 BB = JT.MBB; 4198 SDL.setCurrentBasicBlock(BB); 4199 // Emit the code 4200 SDL.visitJumpTable(JT); 4201 SDAG.setRoot(SDL.getRoot()); 4202 CodeGenAndEmitDAG(SDAG); 4203 // Update PHI Nodes 4204 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) { 4205 MachineInstr *PHI = PHINodesToUpdate[pi].first; 4206 MachineBasicBlock *PHIBB = PHI->getParent(); 4207 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4208 "This is not a machine PHI node that we are updating!"); 4209 if (PHIBB == JT.Default) { 4210 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4211 PHI->addMachineBasicBlockOperand(RangeBB); 4212 } 4213 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { 4214 PHI->addRegOperand(PHINodesToUpdate[pi].second, false); 4215 PHI->addMachineBasicBlockOperand(BB); 4216 } 4217 } 4218 return; 4219 } 4220 4221 // If the switch block involved a branch to one of the actual successors, we 4222 // need to update PHI nodes in that block. 4223 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) { 4224 MachineInstr *PHI = PHINodesToUpdate[i].first; 4225 assert(PHI->getOpcode() == TargetInstrInfo::PHI && 4226 "This is not a machine PHI node that we are updating!"); 4227 if (BB->isSuccessor(PHI->getParent())) { 4228 PHI->addRegOperand(PHINodesToUpdate[i].second, false); 4229 PHI->addMachineBasicBlockOperand(BB); 4230 } 4231 } 4232 4233 // If we generated any switch lowering information, build and codegen any 4234 // additional DAGs necessary. 4235 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { 4236 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>()); 4237 CurDAG = &SDAG; 4238 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo); 4239 4240 // Set the current basic block to the mbb we wish to insert the code into 4241 BB = SwitchCases[i].ThisBB; 4242 SDL.setCurrentBasicBlock(BB); 4243 4244 // Emit the code 4245 SDL.visitSwitchCase(SwitchCases[i]); 4246 SDAG.setRoot(SDL.getRoot()); 4247 CodeGenAndEmitDAG(SDAG); 4248 4249 // Handle any PHI nodes in successors of this chunk, as if we were coming 4250 // from the original BB before switch expansion. Note that PHI nodes can 4251 // occur multiple times in PHINodesToUpdate. We have to be very careful to 4252 // handle them the right number of times. 4253 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS. 4254 for (MachineBasicBlock::iterator Phi = BB->begin(); 4255 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){ 4256 // This value for this PHI node is recorded in PHINodesToUpdate, get it. 4257 for (unsigned pn = 0; ; ++pn) { 4258 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!"); 4259 if (PHINodesToUpdate[pn].first == Phi) { 4260 Phi->addRegOperand(PHINodesToUpdate[pn].second, false); 4261 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB); 4262 break; 4263 } 4264 } 4265 } 4266 4267 // Don't process RHS if same block as LHS. 4268 if (BB == SwitchCases[i].FalseBB) 4269 SwitchCases[i].FalseBB = 0; 4270 4271 // If we haven't handled the RHS, do so now. Otherwise, we're done. 4272 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB; 4273 SwitchCases[i].FalseBB = 0; 4274 } 4275 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0); 4276 } 4277} 4278 4279 4280//===----------------------------------------------------------------------===// 4281/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each 4282/// target node in the graph. 4283void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { 4284 if (ViewSchedDAGs) DAG.viewGraph(); 4285 4286 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 4287 4288 if (!Ctor) { 4289 Ctor = ISHeuristic; 4290 RegisterScheduler::setDefault(Ctor); 4291 } 4292 4293 ScheduleDAG *SL = Ctor(this, &DAG, BB); 4294 BB = SL->Run(); 4295 delete SL; 4296} 4297 4298 4299HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { 4300 return new HazardRecognizer(); 4301} 4302 4303//===----------------------------------------------------------------------===// 4304// Helper functions used by the generated instruction selector. 4305//===----------------------------------------------------------------------===// 4306// Calls to these methods are generated by tblgen. 4307 4308/// CheckAndMask - The isel is trying to match something like (and X, 255). If 4309/// the dag combiner simplified the 255, we still want to match. RHS is the 4310/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 4311/// specified in the .td file (e.g. 255). 4312bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, 4313 int64_t DesiredMaskS) { 4314 uint64_t ActualMask = RHS->getValue(); 4315 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4316 4317 // If the actual mask exactly matches, success! 4318 if (ActualMask == DesiredMask) 4319 return true; 4320 4321 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4322 if (ActualMask & ~DesiredMask) 4323 return false; 4324 4325 // Otherwise, the DAG Combiner may have proven that the value coming in is 4326 // either already zero or is not demanded. Check for known zero input bits. 4327 uint64_t NeededMask = DesiredMask & ~ActualMask; 4328 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) 4329 return true; 4330 4331 // TODO: check to see if missing bits are just not demanded. 4332 4333 // Otherwise, this pattern doesn't match. 4334 return false; 4335} 4336 4337/// CheckOrMask - The isel is trying to match something like (or X, 255). If 4338/// the dag combiner simplified the 255, we still want to match. RHS is the 4339/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 4340/// specified in the .td file (e.g. 255). 4341bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, 4342 int64_t DesiredMaskS) { 4343 uint64_t ActualMask = RHS->getValue(); 4344 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); 4345 4346 // If the actual mask exactly matches, success! 4347 if (ActualMask == DesiredMask) 4348 return true; 4349 4350 // If the actual AND mask is allowing unallowed bits, this doesn't match. 4351 if (ActualMask & ~DesiredMask) 4352 return false; 4353 4354 // Otherwise, the DAG Combiner may have proven that the value coming in is 4355 // either already zero or is not demanded. Check for known zero input bits. 4356 uint64_t NeededMask = DesiredMask & ~ActualMask; 4357 4358 uint64_t KnownZero, KnownOne; 4359 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); 4360 4361 // If all the missing bits in the or are already known to be set, match! 4362 if ((NeededMask & KnownOne) == NeededMask) 4363 return true; 4364 4365 // TODO: check to see if missing bits are just not demanded. 4366 4367 // Otherwise, this pattern doesn't match. 4368 return false; 4369} 4370 4371 4372/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 4373/// by tblgen. Others should not call it. 4374void SelectionDAGISel:: 4375SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { 4376 std::vector<SDOperand> InOps; 4377 std::swap(InOps, Ops); 4378 4379 Ops.push_back(InOps[0]); // input chain. 4380 Ops.push_back(InOps[1]); // input asm string. 4381 4382 unsigned i = 2, e = InOps.size(); 4383 if (InOps[e-1].getValueType() == MVT::Flag) 4384 --e; // Don't process a flag operand if it is here. 4385 4386 while (i != e) { 4387 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue(); 4388 if ((Flags & 7) != 4 /*MEM*/) { 4389 // Just skip over this operand, copying the operands verbatim. 4390 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1); 4391 i += (Flags >> 3) + 1; 4392 } else { 4393 assert((Flags >> 3) == 1 && "Memory operand with multiple values?"); 4394 // Otherwise, this is a memory operand. Ask the target to select it. 4395 std::vector<SDOperand> SelOps; 4396 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) { 4397 cerr << "Could not match memory address. Inline asm failure!\n"; 4398 exit(1); 4399 } 4400 4401 // Add this to the output node. 4402 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32)); 4403 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 4404 i += 2; 4405 } 4406 } 4407 4408 // Add the flag input back if present. 4409 if (e != InOps.size()) 4410 Ops.push_back(InOps.back()); 4411} 4412