TargetLowering.cpp revision 810d6d3354a31f24125abef831e4afccbbbe973d 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/Target/TargetData.h"
18#include "llvm/Target/TargetLoweringObjectFile.h"
19#include "llvm/Target/TargetMachine.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/Analysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/MathExtras.h"
32#include <cctype>
33using namespace llvm;
34
35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
40  cl::desc("Allow promotion of integer vector element types"));
41
42namespace llvm {
43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44  bool isLocal = GV->hasLocalLinkage();
45  bool isDeclaration = GV->isDeclaration();
46  // FIXME: what should we do for protected and internal visibility?
47  // For variables, is internal different from hidden?
48  bool isHidden = GV->hasHiddenVisibility();
49
50  if (reloc == Reloc::PIC_) {
51    if (isLocal || isHidden)
52      return TLSModel::LocalDynamic;
53    else
54      return TLSModel::GeneralDynamic;
55  } else {
56    if (!isDeclaration || isHidden)
57      return TLSModel::LocalExec;
58    else
59      return TLSModel::InitialExec;
60  }
61}
62}
63
64/// InitLibcallNames - Set default libcall names.
65///
66static void InitLibcallNames(const char **Names) {
67  Names[RTLIB::SHL_I16] = "__ashlhi3";
68  Names[RTLIB::SHL_I32] = "__ashlsi3";
69  Names[RTLIB::SHL_I64] = "__ashldi3";
70  Names[RTLIB::SHL_I128] = "__ashlti3";
71  Names[RTLIB::SRL_I16] = "__lshrhi3";
72  Names[RTLIB::SRL_I32] = "__lshrsi3";
73  Names[RTLIB::SRL_I64] = "__lshrdi3";
74  Names[RTLIB::SRL_I128] = "__lshrti3";
75  Names[RTLIB::SRA_I16] = "__ashrhi3";
76  Names[RTLIB::SRA_I32] = "__ashrsi3";
77  Names[RTLIB::SRA_I64] = "__ashrdi3";
78  Names[RTLIB::SRA_I128] = "__ashrti3";
79  Names[RTLIB::MUL_I8] = "__mulqi3";
80  Names[RTLIB::MUL_I16] = "__mulhi3";
81  Names[RTLIB::MUL_I32] = "__mulsi3";
82  Names[RTLIB::MUL_I64] = "__muldi3";
83  Names[RTLIB::MUL_I128] = "__multi3";
84  Names[RTLIB::MULO_I32] = "__mulosi4";
85  Names[RTLIB::MULO_I64] = "__mulodi4";
86  Names[RTLIB::MULO_I128] = "__muloti4";
87  Names[RTLIB::SDIV_I8] = "__divqi3";
88  Names[RTLIB::SDIV_I16] = "__divhi3";
89  Names[RTLIB::SDIV_I32] = "__divsi3";
90  Names[RTLIB::SDIV_I64] = "__divdi3";
91  Names[RTLIB::SDIV_I128] = "__divti3";
92  Names[RTLIB::UDIV_I8] = "__udivqi3";
93  Names[RTLIB::UDIV_I16] = "__udivhi3";
94  Names[RTLIB::UDIV_I32] = "__udivsi3";
95  Names[RTLIB::UDIV_I64] = "__udivdi3";
96  Names[RTLIB::UDIV_I128] = "__udivti3";
97  Names[RTLIB::SREM_I8] = "__modqi3";
98  Names[RTLIB::SREM_I16] = "__modhi3";
99  Names[RTLIB::SREM_I32] = "__modsi3";
100  Names[RTLIB::SREM_I64] = "__moddi3";
101  Names[RTLIB::SREM_I128] = "__modti3";
102  Names[RTLIB::UREM_I8] = "__umodqi3";
103  Names[RTLIB::UREM_I16] = "__umodhi3";
104  Names[RTLIB::UREM_I32] = "__umodsi3";
105  Names[RTLIB::UREM_I64] = "__umoddi3";
106  Names[RTLIB::UREM_I128] = "__umodti3";
107
108  // These are generally not available.
109  Names[RTLIB::SDIVREM_I8] = 0;
110  Names[RTLIB::SDIVREM_I16] = 0;
111  Names[RTLIB::SDIVREM_I32] = 0;
112  Names[RTLIB::SDIVREM_I64] = 0;
113  Names[RTLIB::SDIVREM_I128] = 0;
114  Names[RTLIB::UDIVREM_I8] = 0;
115  Names[RTLIB::UDIVREM_I16] = 0;
116  Names[RTLIB::UDIVREM_I32] = 0;
117  Names[RTLIB::UDIVREM_I64] = 0;
118  Names[RTLIB::UDIVREM_I128] = 0;
119
120  Names[RTLIB::NEG_I32] = "__negsi2";
121  Names[RTLIB::NEG_I64] = "__negdi2";
122  Names[RTLIB::ADD_F32] = "__addsf3";
123  Names[RTLIB::ADD_F64] = "__adddf3";
124  Names[RTLIB::ADD_F80] = "__addxf3";
125  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
126  Names[RTLIB::SUB_F32] = "__subsf3";
127  Names[RTLIB::SUB_F64] = "__subdf3";
128  Names[RTLIB::SUB_F80] = "__subxf3";
129  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
130  Names[RTLIB::MUL_F32] = "__mulsf3";
131  Names[RTLIB::MUL_F64] = "__muldf3";
132  Names[RTLIB::MUL_F80] = "__mulxf3";
133  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
134  Names[RTLIB::DIV_F32] = "__divsf3";
135  Names[RTLIB::DIV_F64] = "__divdf3";
136  Names[RTLIB::DIV_F80] = "__divxf3";
137  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
138  Names[RTLIB::REM_F32] = "fmodf";
139  Names[RTLIB::REM_F64] = "fmod";
140  Names[RTLIB::REM_F80] = "fmodl";
141  Names[RTLIB::REM_PPCF128] = "fmodl";
142  Names[RTLIB::FMA_F32] = "fmaf";
143  Names[RTLIB::FMA_F64] = "fma";
144  Names[RTLIB::FMA_F80] = "fmal";
145  Names[RTLIB::FMA_PPCF128] = "fmal";
146  Names[RTLIB::POWI_F32] = "__powisf2";
147  Names[RTLIB::POWI_F64] = "__powidf2";
148  Names[RTLIB::POWI_F80] = "__powixf2";
149  Names[RTLIB::POWI_PPCF128] = "__powitf2";
150  Names[RTLIB::SQRT_F32] = "sqrtf";
151  Names[RTLIB::SQRT_F64] = "sqrt";
152  Names[RTLIB::SQRT_F80] = "sqrtl";
153  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
154  Names[RTLIB::LOG_F32] = "logf";
155  Names[RTLIB::LOG_F64] = "log";
156  Names[RTLIB::LOG_F80] = "logl";
157  Names[RTLIB::LOG_PPCF128] = "logl";
158  Names[RTLIB::LOG2_F32] = "log2f";
159  Names[RTLIB::LOG2_F64] = "log2";
160  Names[RTLIB::LOG2_F80] = "log2l";
161  Names[RTLIB::LOG2_PPCF128] = "log2l";
162  Names[RTLIB::LOG10_F32] = "log10f";
163  Names[RTLIB::LOG10_F64] = "log10";
164  Names[RTLIB::LOG10_F80] = "log10l";
165  Names[RTLIB::LOG10_PPCF128] = "log10l";
166  Names[RTLIB::EXP_F32] = "expf";
167  Names[RTLIB::EXP_F64] = "exp";
168  Names[RTLIB::EXP_F80] = "expl";
169  Names[RTLIB::EXP_PPCF128] = "expl";
170  Names[RTLIB::EXP2_F32] = "exp2f";
171  Names[RTLIB::EXP2_F64] = "exp2";
172  Names[RTLIB::EXP2_F80] = "exp2l";
173  Names[RTLIB::EXP2_PPCF128] = "exp2l";
174  Names[RTLIB::SIN_F32] = "sinf";
175  Names[RTLIB::SIN_F64] = "sin";
176  Names[RTLIB::SIN_F80] = "sinl";
177  Names[RTLIB::SIN_PPCF128] = "sinl";
178  Names[RTLIB::COS_F32] = "cosf";
179  Names[RTLIB::COS_F64] = "cos";
180  Names[RTLIB::COS_F80] = "cosl";
181  Names[RTLIB::COS_PPCF128] = "cosl";
182  Names[RTLIB::POW_F32] = "powf";
183  Names[RTLIB::POW_F64] = "pow";
184  Names[RTLIB::POW_F80] = "powl";
185  Names[RTLIB::POW_PPCF128] = "powl";
186  Names[RTLIB::CEIL_F32] = "ceilf";
187  Names[RTLIB::CEIL_F64] = "ceil";
188  Names[RTLIB::CEIL_F80] = "ceill";
189  Names[RTLIB::CEIL_PPCF128] = "ceill";
190  Names[RTLIB::TRUNC_F32] = "truncf";
191  Names[RTLIB::TRUNC_F64] = "trunc";
192  Names[RTLIB::TRUNC_F80] = "truncl";
193  Names[RTLIB::TRUNC_PPCF128] = "truncl";
194  Names[RTLIB::RINT_F32] = "rintf";
195  Names[RTLIB::RINT_F64] = "rint";
196  Names[RTLIB::RINT_F80] = "rintl";
197  Names[RTLIB::RINT_PPCF128] = "rintl";
198  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
199  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
200  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
201  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
202  Names[RTLIB::FLOOR_F32] = "floorf";
203  Names[RTLIB::FLOOR_F64] = "floor";
204  Names[RTLIB::FLOOR_F80] = "floorl";
205  Names[RTLIB::FLOOR_PPCF128] = "floorl";
206  Names[RTLIB::COPYSIGN_F32] = "copysignf";
207  Names[RTLIB::COPYSIGN_F64] = "copysign";
208  Names[RTLIB::COPYSIGN_F80] = "copysignl";
209  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
210  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
211  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
212  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
213  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
214  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
215  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
216  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
217  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
218  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
219  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
220  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
221  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
222  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
223  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
224  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
225  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
226  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
227  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
228  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
229  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
230  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
231  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
232  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
233  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
234  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
236  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
238  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
239  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
241  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
243  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
244  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
246  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
247  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
248  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
249  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
250  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
251  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
252  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
253  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
254  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
255  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
256  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
257  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
258  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
259  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
260  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
261  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
262  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
263  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
264  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
265  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
266  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
267  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
268  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
269  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
270  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
271  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
272  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
273  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
274  Names[RTLIB::OEQ_F32] = "__eqsf2";
275  Names[RTLIB::OEQ_F64] = "__eqdf2";
276  Names[RTLIB::UNE_F32] = "__nesf2";
277  Names[RTLIB::UNE_F64] = "__nedf2";
278  Names[RTLIB::OGE_F32] = "__gesf2";
279  Names[RTLIB::OGE_F64] = "__gedf2";
280  Names[RTLIB::OLT_F32] = "__ltsf2";
281  Names[RTLIB::OLT_F64] = "__ltdf2";
282  Names[RTLIB::OLE_F32] = "__lesf2";
283  Names[RTLIB::OLE_F64] = "__ledf2";
284  Names[RTLIB::OGT_F32] = "__gtsf2";
285  Names[RTLIB::OGT_F64] = "__gtdf2";
286  Names[RTLIB::UO_F32] = "__unordsf2";
287  Names[RTLIB::UO_F64] = "__unorddf2";
288  Names[RTLIB::O_F32] = "__unordsf2";
289  Names[RTLIB::O_F64] = "__unorddf2";
290  Names[RTLIB::MEMCPY] = "memcpy";
291  Names[RTLIB::MEMMOVE] = "memmove";
292  Names[RTLIB::MEMSET] = "memset";
293  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
294  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
295  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
296  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
297  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
298  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
299  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
300  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
301  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
302  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
303  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
304  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
305  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
306  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
307  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
308  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
309  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
310  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
311  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
312  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
313  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
314  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
315  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
316  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
317  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
318  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
319  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
320  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
321  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
322  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
323  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
324  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
325  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
326}
327
328/// InitLibcallCallingConvs - Set default libcall CallingConvs.
329///
330static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
331  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
332    CCs[i] = CallingConv::C;
333  }
334}
335
336/// getFPEXT - Return the FPEXT_*_* value for the given types, or
337/// UNKNOWN_LIBCALL if there is none.
338RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
339  if (OpVT == MVT::f32) {
340    if (RetVT == MVT::f64)
341      return FPEXT_F32_F64;
342  }
343
344  return UNKNOWN_LIBCALL;
345}
346
347/// getFPROUND - Return the FPROUND_*_* value for the given types, or
348/// UNKNOWN_LIBCALL if there is none.
349RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
350  if (RetVT == MVT::f32) {
351    if (OpVT == MVT::f64)
352      return FPROUND_F64_F32;
353    if (OpVT == MVT::f80)
354      return FPROUND_F80_F32;
355    if (OpVT == MVT::ppcf128)
356      return FPROUND_PPCF128_F32;
357  } else if (RetVT == MVT::f64) {
358    if (OpVT == MVT::f80)
359      return FPROUND_F80_F64;
360    if (OpVT == MVT::ppcf128)
361      return FPROUND_PPCF128_F64;
362  }
363
364  return UNKNOWN_LIBCALL;
365}
366
367/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
368/// UNKNOWN_LIBCALL if there is none.
369RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
370  if (OpVT == MVT::f32) {
371    if (RetVT == MVT::i8)
372      return FPTOSINT_F32_I8;
373    if (RetVT == MVT::i16)
374      return FPTOSINT_F32_I16;
375    if (RetVT == MVT::i32)
376      return FPTOSINT_F32_I32;
377    if (RetVT == MVT::i64)
378      return FPTOSINT_F32_I64;
379    if (RetVT == MVT::i128)
380      return FPTOSINT_F32_I128;
381  } else if (OpVT == MVT::f64) {
382    if (RetVT == MVT::i8)
383      return FPTOSINT_F64_I8;
384    if (RetVT == MVT::i16)
385      return FPTOSINT_F64_I16;
386    if (RetVT == MVT::i32)
387      return FPTOSINT_F64_I32;
388    if (RetVT == MVT::i64)
389      return FPTOSINT_F64_I64;
390    if (RetVT == MVT::i128)
391      return FPTOSINT_F64_I128;
392  } else if (OpVT == MVT::f80) {
393    if (RetVT == MVT::i32)
394      return FPTOSINT_F80_I32;
395    if (RetVT == MVT::i64)
396      return FPTOSINT_F80_I64;
397    if (RetVT == MVT::i128)
398      return FPTOSINT_F80_I128;
399  } else if (OpVT == MVT::ppcf128) {
400    if (RetVT == MVT::i32)
401      return FPTOSINT_PPCF128_I32;
402    if (RetVT == MVT::i64)
403      return FPTOSINT_PPCF128_I64;
404    if (RetVT == MVT::i128)
405      return FPTOSINT_PPCF128_I128;
406  }
407  return UNKNOWN_LIBCALL;
408}
409
410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411/// UNKNOWN_LIBCALL if there is none.
412RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
413  if (OpVT == MVT::f32) {
414    if (RetVT == MVT::i8)
415      return FPTOUINT_F32_I8;
416    if (RetVT == MVT::i16)
417      return FPTOUINT_F32_I16;
418    if (RetVT == MVT::i32)
419      return FPTOUINT_F32_I32;
420    if (RetVT == MVT::i64)
421      return FPTOUINT_F32_I64;
422    if (RetVT == MVT::i128)
423      return FPTOUINT_F32_I128;
424  } else if (OpVT == MVT::f64) {
425    if (RetVT == MVT::i8)
426      return FPTOUINT_F64_I8;
427    if (RetVT == MVT::i16)
428      return FPTOUINT_F64_I16;
429    if (RetVT == MVT::i32)
430      return FPTOUINT_F64_I32;
431    if (RetVT == MVT::i64)
432      return FPTOUINT_F64_I64;
433    if (RetVT == MVT::i128)
434      return FPTOUINT_F64_I128;
435  } else if (OpVT == MVT::f80) {
436    if (RetVT == MVT::i32)
437      return FPTOUINT_F80_I32;
438    if (RetVT == MVT::i64)
439      return FPTOUINT_F80_I64;
440    if (RetVT == MVT::i128)
441      return FPTOUINT_F80_I128;
442  } else if (OpVT == MVT::ppcf128) {
443    if (RetVT == MVT::i32)
444      return FPTOUINT_PPCF128_I32;
445    if (RetVT == MVT::i64)
446      return FPTOUINT_PPCF128_I64;
447    if (RetVT == MVT::i128)
448      return FPTOUINT_PPCF128_I128;
449  }
450  return UNKNOWN_LIBCALL;
451}
452
453/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
454/// UNKNOWN_LIBCALL if there is none.
455RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
456  if (OpVT == MVT::i32) {
457    if (RetVT == MVT::f32)
458      return SINTTOFP_I32_F32;
459    else if (RetVT == MVT::f64)
460      return SINTTOFP_I32_F64;
461    else if (RetVT == MVT::f80)
462      return SINTTOFP_I32_F80;
463    else if (RetVT == MVT::ppcf128)
464      return SINTTOFP_I32_PPCF128;
465  } else if (OpVT == MVT::i64) {
466    if (RetVT == MVT::f32)
467      return SINTTOFP_I64_F32;
468    else if (RetVT == MVT::f64)
469      return SINTTOFP_I64_F64;
470    else if (RetVT == MVT::f80)
471      return SINTTOFP_I64_F80;
472    else if (RetVT == MVT::ppcf128)
473      return SINTTOFP_I64_PPCF128;
474  } else if (OpVT == MVT::i128) {
475    if (RetVT == MVT::f32)
476      return SINTTOFP_I128_F32;
477    else if (RetVT == MVT::f64)
478      return SINTTOFP_I128_F64;
479    else if (RetVT == MVT::f80)
480      return SINTTOFP_I128_F80;
481    else if (RetVT == MVT::ppcf128)
482      return SINTTOFP_I128_PPCF128;
483  }
484  return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490  if (OpVT == MVT::i32) {
491    if (RetVT == MVT::f32)
492      return UINTTOFP_I32_F32;
493    else if (RetVT == MVT::f64)
494      return UINTTOFP_I32_F64;
495    else if (RetVT == MVT::f80)
496      return UINTTOFP_I32_F80;
497    else if (RetVT == MVT::ppcf128)
498      return UINTTOFP_I32_PPCF128;
499  } else if (OpVT == MVT::i64) {
500    if (RetVT == MVT::f32)
501      return UINTTOFP_I64_F32;
502    else if (RetVT == MVT::f64)
503      return UINTTOFP_I64_F64;
504    else if (RetVT == MVT::f80)
505      return UINTTOFP_I64_F80;
506    else if (RetVT == MVT::ppcf128)
507      return UINTTOFP_I64_PPCF128;
508  } else if (OpVT == MVT::i128) {
509    if (RetVT == MVT::f32)
510      return UINTTOFP_I128_F32;
511    else if (RetVT == MVT::f64)
512      return UINTTOFP_I128_F64;
513    else if (RetVT == MVT::f80)
514      return UINTTOFP_I128_F80;
515    else if (RetVT == MVT::ppcf128)
516      return UINTTOFP_I128_PPCF128;
517  }
518  return UNKNOWN_LIBCALL;
519}
520
521/// InitCmpLibcallCCs - Set default comparison libcall CC.
522///
523static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527  CCs[RTLIB::UNE_F32] = ISD::SETNE;
528  CCs[RTLIB::UNE_F64] = ISD::SETNE;
529  CCs[RTLIB::OGE_F32] = ISD::SETGE;
530  CCs[RTLIB::OGE_F64] = ISD::SETGE;
531  CCs[RTLIB::OLT_F32] = ISD::SETLT;
532  CCs[RTLIB::OLT_F64] = ISD::SETLT;
533  CCs[RTLIB::OLE_F32] = ISD::SETLE;
534  CCs[RTLIB::OLE_F64] = ISD::SETLE;
535  CCs[RTLIB::OGT_F32] = ISD::SETGT;
536  CCs[RTLIB::OGT_F64] = ISD::SETGT;
537  CCs[RTLIB::UO_F32] = ISD::SETNE;
538  CCs[RTLIB::UO_F64] = ISD::SETNE;
539  CCs[RTLIB::O_F32] = ISD::SETEQ;
540  CCs[RTLIB::O_F64] = ISD::SETEQ;
541}
542
543/// NOTE: The constructor takes ownership of TLOF.
544TargetLowering::TargetLowering(const TargetMachine &tm,
545                               const TargetLoweringObjectFile *tlof)
546  : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
547  mayPromoteElements(AllowPromoteIntElem) {
548  // All operations default to being supported.
549  memset(OpActions, 0, sizeof(OpActions));
550  memset(LoadExtActions, 0, sizeof(LoadExtActions));
551  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
552  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
553  memset(CondCodeActions, 0, sizeof(CondCodeActions));
554
555  // Set default actions for various operations.
556  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
557    // Default all indexed load / store to expand.
558    for (unsigned IM = (unsigned)ISD::PRE_INC;
559         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
560      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
561      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
562    }
563
564    // These operations default to expand.
565    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
566    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
567  }
568
569  // Most targets ignore the @llvm.prefetch intrinsic.
570  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
571
572  // ConstantFP nodes default to expand.  Targets can either change this to
573  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
574  // to optimize expansions for certain constants.
575  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
576  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
577  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
578  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
579
580  // These library functions default to expand.
581  setOperationAction(ISD::FLOG ,  MVT::f16, Expand);
582  setOperationAction(ISD::FLOG2,  MVT::f16, Expand);
583  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
584  setOperationAction(ISD::FEXP ,  MVT::f16, Expand);
585  setOperationAction(ISD::FEXP2,  MVT::f16, Expand);
586  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
587  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
588  setOperationAction(ISD::FCEIL,  MVT::f16, Expand);
589  setOperationAction(ISD::FRINT,  MVT::f16, Expand);
590  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
591  setOperationAction(ISD::FLOG ,  MVT::f32, Expand);
592  setOperationAction(ISD::FLOG2,  MVT::f32, Expand);
593  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
594  setOperationAction(ISD::FEXP ,  MVT::f32, Expand);
595  setOperationAction(ISD::FEXP2,  MVT::f32, Expand);
596  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
597  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
598  setOperationAction(ISD::FCEIL,  MVT::f32, Expand);
599  setOperationAction(ISD::FRINT,  MVT::f32, Expand);
600  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
601  setOperationAction(ISD::FLOG ,  MVT::f64, Expand);
602  setOperationAction(ISD::FLOG2,  MVT::f64, Expand);
603  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
604  setOperationAction(ISD::FEXP ,  MVT::f64, Expand);
605  setOperationAction(ISD::FEXP2,  MVT::f64, Expand);
606  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
607  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
608  setOperationAction(ISD::FCEIL,  MVT::f64, Expand);
609  setOperationAction(ISD::FRINT,  MVT::f64, Expand);
610  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
611
612  // Default ISD::TRAP to expand (which turns it into abort).
613  setOperationAction(ISD::TRAP, MVT::Other, Expand);
614
615  IsLittleEndian = TD->isLittleEndian();
616  PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
617  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
618  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
619  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
620  maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
621    = maxStoresPerMemmoveOptSize = 4;
622  benefitFromCodePlacementOpt = false;
623  UseUnderscoreSetJmp = false;
624  UseUnderscoreLongJmp = false;
625  SelectIsExpensive = false;
626  IntDivIsCheap = false;
627  Pow2DivIsCheap = false;
628  JumpIsExpensive = false;
629  StackPointerRegisterToSaveRestore = 0;
630  ExceptionPointerRegister = 0;
631  ExceptionSelectorRegister = 0;
632  BooleanContents = UndefinedBooleanContent;
633  BooleanVectorContents = UndefinedBooleanContent;
634  SchedPreferenceInfo = Sched::ILP;
635  JumpBufSize = 0;
636  JumpBufAlignment = 0;
637  MinFunctionAlignment = 0;
638  PrefFunctionAlignment = 0;
639  PrefLoopAlignment = 0;
640  MinStackArgumentAlignment = 1;
641  ShouldFoldAtomicFences = false;
642  InsertFencesForAtomic = false;
643
644  InitLibcallNames(LibcallRoutineNames);
645  InitCmpLibcallCCs(CmpLibcallCCs);
646  InitLibcallCallingConvs(LibcallCallingConvs);
647}
648
649TargetLowering::~TargetLowering() {
650  delete &TLOF;
651}
652
653MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
654  return MVT::getIntegerVT(8*TD->getPointerSize());
655}
656
657/// canOpTrap - Returns true if the operation can trap for the value type.
658/// VT must be a legal type.
659bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
660  assert(isTypeLegal(VT));
661  switch (Op) {
662  default:
663    return false;
664  case ISD::FDIV:
665  case ISD::FREM:
666  case ISD::SDIV:
667  case ISD::UDIV:
668  case ISD::SREM:
669  case ISD::UREM:
670    return true;
671  }
672}
673
674
675static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
676                                          unsigned &NumIntermediates,
677                                          EVT &RegisterVT,
678                                          TargetLowering *TLI) {
679  // Figure out the right, legal destination reg to copy into.
680  unsigned NumElts = VT.getVectorNumElements();
681  MVT EltTy = VT.getVectorElementType();
682
683  unsigned NumVectorRegs = 1;
684
685  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
686  // could break down into LHS/RHS like LegalizeDAG does.
687  if (!isPowerOf2_32(NumElts)) {
688    NumVectorRegs = NumElts;
689    NumElts = 1;
690  }
691
692  // Divide the input until we get to a supported size.  This will always
693  // end with a scalar if the target doesn't support vectors.
694  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
695    NumElts >>= 1;
696    NumVectorRegs <<= 1;
697  }
698
699  NumIntermediates = NumVectorRegs;
700
701  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
702  if (!TLI->isTypeLegal(NewVT))
703    NewVT = EltTy;
704  IntermediateVT = NewVT;
705
706  unsigned NewVTSize = NewVT.getSizeInBits();
707
708  // Convert sizes such as i33 to i64.
709  if (!isPowerOf2_32(NewVTSize))
710    NewVTSize = NextPowerOf2(NewVTSize);
711
712  EVT DestVT = TLI->getRegisterType(NewVT);
713  RegisterVT = DestVT;
714  if (EVT(DestVT).bitsLT(NewVT))    // Value is expanded, e.g. i64 -> i16.
715    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
716
717  // Otherwise, promotion or legal types use the same number of registers as
718  // the vector decimated to the appropriate level.
719  return NumVectorRegs;
720}
721
722/// isLegalRC - Return true if the value types that can be represented by the
723/// specified register class are all legal.
724bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
725  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
726       I != E; ++I) {
727    if (isTypeLegal(*I))
728      return true;
729  }
730  return false;
731}
732
733/// hasLegalSuperRegRegClasses - Return true if the specified register class
734/// has one or more super-reg register classes that are legal.
735bool
736TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
737  if (*RC->superregclasses_begin() == 0)
738    return false;
739  for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
740         E = RC->superregclasses_end(); I != E; ++I) {
741    const TargetRegisterClass *RRC = *I;
742    if (isLegalRC(RRC))
743      return true;
744  }
745  return false;
746}
747
748/// findRepresentativeClass - Return the largest legal super-reg register class
749/// of the register class for the specified type and its associated "cost".
750std::pair<const TargetRegisterClass*, uint8_t>
751TargetLowering::findRepresentativeClass(EVT VT) const {
752  const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
753  if (!RC)
754    return std::make_pair(RC, 0);
755  const TargetRegisterClass *BestRC = RC;
756  for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
757         E = RC->superregclasses_end(); I != E; ++I) {
758    const TargetRegisterClass *RRC = *I;
759    if (RRC->isASubClass() || !isLegalRC(RRC))
760      continue;
761    if (!hasLegalSuperRegRegClasses(RRC))
762      return std::make_pair(RRC, 1);
763    BestRC = RRC;
764  }
765  return std::make_pair(BestRC, 1);
766}
767
768
769/// computeRegisterProperties - Once all of the register classes are added,
770/// this allows us to compute derived properties we expose.
771void TargetLowering::computeRegisterProperties() {
772  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
773         "Too many value types for ValueTypeActions to hold!");
774
775  // Everything defaults to needing one register.
776  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
777    NumRegistersForVT[i] = 1;
778    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
779  }
780  // ...except isVoid, which doesn't need any registers.
781  NumRegistersForVT[MVT::isVoid] = 0;
782
783  // Find the largest integer register class.
784  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
785  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
786    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
787
788  // Every integer value type larger than this largest register takes twice as
789  // many registers to represent as the previous ValueType.
790  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
791    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
792    if (!ExpandedVT.isInteger())
793      break;
794    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
795    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
796    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
797    ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
798  }
799
800  // Inspect all of the ValueType's smaller than the largest integer
801  // register to see which ones need promotion.
802  unsigned LegalIntReg = LargestIntReg;
803  for (unsigned IntReg = LargestIntReg - 1;
804       IntReg >= (unsigned)MVT::i1; --IntReg) {
805    EVT IVT = (MVT::SimpleValueType)IntReg;
806    if (isTypeLegal(IVT)) {
807      LegalIntReg = IntReg;
808    } else {
809      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
810        (MVT::SimpleValueType)LegalIntReg;
811      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
812    }
813  }
814
815  // ppcf128 type is really two f64's.
816  if (!isTypeLegal(MVT::ppcf128)) {
817    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
818    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
819    TransformToType[MVT::ppcf128] = MVT::f64;
820    ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
821  }
822
823  // Decide how to handle f64. If the target does not have native f64 support,
824  // expand it to i64 and we will be generating soft float library calls.
825  if (!isTypeLegal(MVT::f64)) {
826    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
827    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
828    TransformToType[MVT::f64] = MVT::i64;
829    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
830  }
831
832  // Decide how to handle f32. If the target does not have native support for
833  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
834  if (!isTypeLegal(MVT::f32)) {
835    if (isTypeLegal(MVT::f64)) {
836      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
837      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
838      TransformToType[MVT::f32] = MVT::f64;
839      ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
840    } else {
841      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
842      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
843      TransformToType[MVT::f32] = MVT::i32;
844      ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
845    }
846  }
847
848  // Loop over all of the vector value types to see which need transformations.
849  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
850       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
851    MVT VT = (MVT::SimpleValueType)i;
852    if (isTypeLegal(VT)) continue;
853
854    // Determine if there is a legal wider type.  If so, we should promote to
855    // that wider vector type.
856    EVT EltVT = VT.getVectorElementType();
857    unsigned NElts = VT.getVectorNumElements();
858    if (NElts != 1) {
859      bool IsLegalWiderType = false;
860      // If we allow the promotion of vector elements using a flag,
861      // then return TypePromoteInteger on vector elements.
862      // First try to promote the elements of integer vectors. If no legal
863      // promotion was found, fallback to the widen-vector method.
864      if (mayPromoteElements)
865      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
866        EVT SVT = (MVT::SimpleValueType)nVT;
867        // Promote vectors of integers to vectors with the same number
868        // of elements, with a wider element type.
869        if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
870            && SVT.getVectorNumElements() == NElts &&
871            isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
872          TransformToType[i] = SVT;
873          RegisterTypeForVT[i] = SVT;
874          NumRegistersForVT[i] = 1;
875          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
876          IsLegalWiderType = true;
877          break;
878        }
879      }
880
881      if (IsLegalWiderType) continue;
882
883      // Try to widen the vector.
884      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
885        EVT SVT = (MVT::SimpleValueType)nVT;
886        if (SVT.getVectorElementType() == EltVT &&
887            SVT.getVectorNumElements() > NElts &&
888            isTypeLegal(SVT)) {
889          TransformToType[i] = SVT;
890          RegisterTypeForVT[i] = SVT;
891          NumRegistersForVT[i] = 1;
892          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
893          IsLegalWiderType = true;
894          break;
895        }
896      }
897      if (IsLegalWiderType) continue;
898    }
899
900    MVT IntermediateVT;
901    EVT RegisterVT;
902    unsigned NumIntermediates;
903    NumRegistersForVT[i] =
904      getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
905                                RegisterVT, this);
906    RegisterTypeForVT[i] = RegisterVT;
907
908    EVT NVT = VT.getPow2VectorType();
909    if (NVT == VT) {
910      // Type is already a power of 2.  The default action is to split.
911      TransformToType[i] = MVT::Other;
912      unsigned NumElts = VT.getVectorNumElements();
913      ValueTypeActions.setTypeAction(VT,
914            NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
915    } else {
916      TransformToType[i] = NVT;
917      ValueTypeActions.setTypeAction(VT, TypeWidenVector);
918    }
919  }
920
921  // Determine the 'representative' register class for each value type.
922  // An representative register class is the largest (meaning one which is
923  // not a sub-register class / subreg register class) legal register class for
924  // a group of value types. For example, on i386, i8, i16, and i32
925  // representative would be GR32; while on x86_64 it's GR64.
926  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
927    const TargetRegisterClass* RRC;
928    uint8_t Cost;
929    tie(RRC, Cost) =  findRepresentativeClass((MVT::SimpleValueType)i);
930    RepRegClassForVT[i] = RRC;
931    RepRegClassCostForVT[i] = Cost;
932  }
933}
934
935const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
936  return NULL;
937}
938
939
940EVT TargetLowering::getSetCCResultType(EVT VT) const {
941  assert(!VT.isVector() && "No default SetCC type for vectors!");
942  return PointerTy.SimpleTy;
943}
944
945MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
946  return MVT::i32; // return the default value
947}
948
949/// getVectorTypeBreakdown - Vector types are broken down into some number of
950/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
951/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
952/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
953///
954/// This method returns the number of registers needed, and the VT for each
955/// register.  It also returns the VT and quantity of the intermediate values
956/// before they are promoted/expanded.
957///
958unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
959                                                EVT &IntermediateVT,
960                                                unsigned &NumIntermediates,
961                                                EVT &RegisterVT) const {
962  unsigned NumElts = VT.getVectorNumElements();
963
964  // If there is a wider vector type with the same element type as this one,
965  // we should widen to that legal vector type.  This handles things like
966  // <2 x float> -> <4 x float>.
967  if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
968    RegisterVT = getTypeToTransformTo(Context, VT);
969    if (isTypeLegal(RegisterVT)) {
970      IntermediateVT = RegisterVT;
971      NumIntermediates = 1;
972      return 1;
973    }
974  }
975
976  // Figure out the right, legal destination reg to copy into.
977  EVT EltTy = VT.getVectorElementType();
978
979  unsigned NumVectorRegs = 1;
980
981  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
982  // could break down into LHS/RHS like LegalizeDAG does.
983  if (!isPowerOf2_32(NumElts)) {
984    NumVectorRegs = NumElts;
985    NumElts = 1;
986  }
987
988  // Divide the input until we get to a supported size.  This will always
989  // end with a scalar if the target doesn't support vectors.
990  while (NumElts > 1 && !isTypeLegal(
991                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
992    NumElts >>= 1;
993    NumVectorRegs <<= 1;
994  }
995
996  NumIntermediates = NumVectorRegs;
997
998  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
999  if (!isTypeLegal(NewVT))
1000    NewVT = EltTy;
1001  IntermediateVT = NewVT;
1002
1003  EVT DestVT = getRegisterType(Context, NewVT);
1004  RegisterVT = DestVT;
1005  unsigned NewVTSize = NewVT.getSizeInBits();
1006
1007  // Convert sizes such as i33 to i64.
1008  if (!isPowerOf2_32(NewVTSize))
1009    NewVTSize = NextPowerOf2(NewVTSize);
1010
1011  if (DestVT.bitsLT(NewVT))   // Value is expanded, e.g. i64 -> i16.
1012    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1013
1014  // Otherwise, promotion or legal types use the same number of registers as
1015  // the vector decimated to the appropriate level.
1016  return NumVectorRegs;
1017}
1018
1019/// Get the EVTs and ArgFlags collections that represent the legalized return
1020/// type of the given function.  This does not require a DAG or a return value,
1021/// and is suitable for use before any DAGs for the function are constructed.
1022/// TODO: Move this out of TargetLowering.cpp.
1023void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
1024                         SmallVectorImpl<ISD::OutputArg> &Outs,
1025                         const TargetLowering &TLI,
1026                         SmallVectorImpl<uint64_t> *Offsets) {
1027  SmallVector<EVT, 4> ValueVTs;
1028  ComputeValueVTs(TLI, ReturnType, ValueVTs);
1029  unsigned NumValues = ValueVTs.size();
1030  if (NumValues == 0) return;
1031  unsigned Offset = 0;
1032
1033  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1034    EVT VT = ValueVTs[j];
1035    ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1036
1037    if (attr & Attribute::SExt)
1038      ExtendKind = ISD::SIGN_EXTEND;
1039    else if (attr & Attribute::ZExt)
1040      ExtendKind = ISD::ZERO_EXTEND;
1041
1042    // FIXME: C calling convention requires the return type to be promoted to
1043    // at least 32-bit. But this is not necessary for non-C calling
1044    // conventions. The frontend should mark functions whose return values
1045    // require promoting with signext or zeroext attributes.
1046    if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1047      EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1048      if (VT.bitsLT(MinVT))
1049        VT = MinVT;
1050    }
1051
1052    unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1053    EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1054    unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1055                        PartVT.getTypeForEVT(ReturnType->getContext()));
1056
1057    // 'inreg' on function refers to return value
1058    ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1059    if (attr & Attribute::InReg)
1060      Flags.setInReg();
1061
1062    // Propagate extension type if any
1063    if (attr & Attribute::SExt)
1064      Flags.setSExt();
1065    else if (attr & Attribute::ZExt)
1066      Flags.setZExt();
1067
1068    for (unsigned i = 0; i < NumParts; ++i) {
1069      Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1070      if (Offsets) {
1071        Offsets->push_back(Offset);
1072        Offset += PartSize;
1073      }
1074    }
1075  }
1076}
1077
1078/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1079/// function arguments in the caller parameter area.  This is the actual
1080/// alignment, not its logarithm.
1081unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1082  return TD->getCallFrameTypeAlignment(Ty);
1083}
1084
1085/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1086/// current function.  The returned value is a member of the
1087/// MachineJumpTableInfo::JTEntryKind enum.
1088unsigned TargetLowering::getJumpTableEncoding() const {
1089  // In non-pic modes, just use the address of a block.
1090  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1091    return MachineJumpTableInfo::EK_BlockAddress;
1092
1093  // In PIC mode, if the target supports a GPRel32 directive, use it.
1094  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1095    return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1096
1097  // Otherwise, use a label difference.
1098  return MachineJumpTableInfo::EK_LabelDifference32;
1099}
1100
1101SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1102                                                 SelectionDAG &DAG) const {
1103  // If our PIC model is GP relative, use the global offset table as the base.
1104  if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1105    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1106  return Table;
1107}
1108
1109/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1110/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1111/// MCExpr.
1112const MCExpr *
1113TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1114                                             unsigned JTI,MCContext &Ctx) const{
1115  // The normal PIC reloc base is the label at the start of the jump table.
1116  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1117}
1118
1119bool
1120TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1121  // Assume that everything is safe in static mode.
1122  if (getTargetMachine().getRelocationModel() == Reloc::Static)
1123    return true;
1124
1125  // In dynamic-no-pic mode, assume that known defined values are safe.
1126  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1127      GA &&
1128      !GA->getGlobal()->isDeclaration() &&
1129      !GA->getGlobal()->isWeakForLinker())
1130    return true;
1131
1132  // Otherwise assume nothing is safe.
1133  return false;
1134}
1135
1136//===----------------------------------------------------------------------===//
1137//  Optimization Methods
1138//===----------------------------------------------------------------------===//
1139
1140/// ShrinkDemandedConstant - Check to see if the specified operand of the
1141/// specified instruction is a constant integer.  If so, check to see if there
1142/// are any bits set in the constant that are not demanded.  If so, shrink the
1143/// constant and return true.
1144bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1145                                                        const APInt &Demanded) {
1146  DebugLoc dl = Op.getDebugLoc();
1147
1148  // FIXME: ISD::SELECT, ISD::SELECT_CC
1149  switch (Op.getOpcode()) {
1150  default: break;
1151  case ISD::XOR:
1152  case ISD::AND:
1153  case ISD::OR: {
1154    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1155    if (!C) return false;
1156
1157    if (Op.getOpcode() == ISD::XOR &&
1158        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1159      return false;
1160
1161    // if we can expand it to have all bits set, do it
1162    if (C->getAPIntValue().intersects(~Demanded)) {
1163      EVT VT = Op.getValueType();
1164      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1165                                DAG.getConstant(Demanded &
1166                                                C->getAPIntValue(),
1167                                                VT));
1168      return CombineTo(Op, New);
1169    }
1170
1171    break;
1172  }
1173  }
1174
1175  return false;
1176}
1177
1178/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1179/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
1180/// cast, but it could be generalized for targets with other types of
1181/// implicit widening casts.
1182bool
1183TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1184                                                    unsigned BitWidth,
1185                                                    const APInt &Demanded,
1186                                                    DebugLoc dl) {
1187  assert(Op.getNumOperands() == 2 &&
1188         "ShrinkDemandedOp only supports binary operators!");
1189  assert(Op.getNode()->getNumValues() == 1 &&
1190         "ShrinkDemandedOp only supports nodes with one result!");
1191
1192  // Don't do this if the node has another user, which may require the
1193  // full value.
1194  if (!Op.getNode()->hasOneUse())
1195    return false;
1196
1197  // Search for the smallest integer type with free casts to and from
1198  // Op's type. For expedience, just check power-of-2 integer types.
1199  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1200  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1201  if (!isPowerOf2_32(SmallVTBits))
1202    SmallVTBits = NextPowerOf2(SmallVTBits);
1203  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1204    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1205    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1206        TLI.isZExtFree(SmallVT, Op.getValueType())) {
1207      // We found a type with free casts.
1208      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1209                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1210                                          Op.getNode()->getOperand(0)),
1211                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1212                                          Op.getNode()->getOperand(1)));
1213      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1214      return CombineTo(Op, Z);
1215    }
1216  }
1217  return false;
1218}
1219
1220/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
1221/// DemandedMask bits of the result of Op are ever used downstream.  If we can
1222/// use this information to simplify Op, create a new simplified DAG node and
1223/// return true, returning the original and new nodes in Old and New. Otherwise,
1224/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1225/// the expression (used to simplify the caller).  The KnownZero/One bits may
1226/// only be accurate for those bits in the DemandedMask.
1227bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1228                                          const APInt &DemandedMask,
1229                                          APInt &KnownZero,
1230                                          APInt &KnownOne,
1231                                          TargetLoweringOpt &TLO,
1232                                          unsigned Depth) const {
1233  unsigned BitWidth = DemandedMask.getBitWidth();
1234  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1235         "Mask size mismatches value type size!");
1236  APInt NewMask = DemandedMask;
1237  DebugLoc dl = Op.getDebugLoc();
1238
1239  // Don't know anything.
1240  KnownZero = KnownOne = APInt(BitWidth, 0);
1241
1242  // Other users may use these bits.
1243  if (!Op.getNode()->hasOneUse()) {
1244    if (Depth != 0) {
1245      // If not at the root, Just compute the KnownZero/KnownOne bits to
1246      // simplify things downstream.
1247      TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1248      return false;
1249    }
1250    // If this is the root being simplified, allow it to have multiple uses,
1251    // just set the NewMask to all bits.
1252    NewMask = APInt::getAllOnesValue(BitWidth);
1253  } else if (DemandedMask == 0) {
1254    // Not demanding any bits from Op.
1255    if (Op.getOpcode() != ISD::UNDEF)
1256      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1257    return false;
1258  } else if (Depth == 6) {        // Limit search depth.
1259    return false;
1260  }
1261
1262  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1263  switch (Op.getOpcode()) {
1264  case ISD::Constant:
1265    // We know all of the bits for a constant!
1266    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1267    KnownZero = ~KnownOne & NewMask;
1268    return false;   // Don't fall through, will infinitely loop.
1269  case ISD::AND:
1270    // If the RHS is a constant, check to see if the LHS would be zero without
1271    // using the bits from the RHS.  Below, we use knowledge about the RHS to
1272    // simplify the LHS, here we're using information from the LHS to simplify
1273    // the RHS.
1274    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1275      APInt LHSZero, LHSOne;
1276      // Do not increment Depth here; that can cause an infinite loop.
1277      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1278                                LHSZero, LHSOne, Depth);
1279      // If the LHS already has zeros where RHSC does, this and is dead.
1280      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1281        return TLO.CombineTo(Op, Op.getOperand(0));
1282      // If any of the set bits in the RHS are known zero on the LHS, shrink
1283      // the constant.
1284      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1285        return true;
1286    }
1287
1288    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1289                             KnownOne, TLO, Depth+1))
1290      return true;
1291    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1292    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1293                             KnownZero2, KnownOne2, TLO, Depth+1))
1294      return true;
1295    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1296
1297    // If all of the demanded bits are known one on one side, return the other.
1298    // These bits cannot contribute to the result of the 'and'.
1299    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1300      return TLO.CombineTo(Op, Op.getOperand(0));
1301    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1302      return TLO.CombineTo(Op, Op.getOperand(1));
1303    // If all of the demanded bits in the inputs are known zeros, return zero.
1304    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1305      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1306    // If the RHS is a constant, see if we can simplify it.
1307    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1308      return true;
1309    // If the operation can be done in a smaller type, do so.
1310    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1311      return true;
1312
1313    // Output known-1 bits are only known if set in both the LHS & RHS.
1314    KnownOne &= KnownOne2;
1315    // Output known-0 are known to be clear if zero in either the LHS | RHS.
1316    KnownZero |= KnownZero2;
1317    break;
1318  case ISD::OR:
1319    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1320                             KnownOne, TLO, Depth+1))
1321      return true;
1322    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1323    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1324                             KnownZero2, KnownOne2, TLO, Depth+1))
1325      return true;
1326    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1327
1328    // If all of the demanded bits are known zero on one side, return the other.
1329    // These bits cannot contribute to the result of the 'or'.
1330    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1331      return TLO.CombineTo(Op, Op.getOperand(0));
1332    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1333      return TLO.CombineTo(Op, Op.getOperand(1));
1334    // If all of the potentially set bits on one side are known to be set on
1335    // the other side, just use the 'other' side.
1336    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1337      return TLO.CombineTo(Op, Op.getOperand(0));
1338    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1339      return TLO.CombineTo(Op, Op.getOperand(1));
1340    // If the RHS is a constant, see if we can simplify it.
1341    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1342      return true;
1343    // If the operation can be done in a smaller type, do so.
1344    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1345      return true;
1346
1347    // Output known-0 bits are only known if clear in both the LHS & RHS.
1348    KnownZero &= KnownZero2;
1349    // Output known-1 are known to be set if set in either the LHS | RHS.
1350    KnownOne |= KnownOne2;
1351    break;
1352  case ISD::XOR:
1353    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1354                             KnownOne, TLO, Depth+1))
1355      return true;
1356    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1357    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1358                             KnownOne2, TLO, Depth+1))
1359      return true;
1360    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1361
1362    // If all of the demanded bits are known zero on one side, return the other.
1363    // These bits cannot contribute to the result of the 'xor'.
1364    if ((KnownZero & NewMask) == NewMask)
1365      return TLO.CombineTo(Op, Op.getOperand(0));
1366    if ((KnownZero2 & NewMask) == NewMask)
1367      return TLO.CombineTo(Op, Op.getOperand(1));
1368    // If the operation can be done in a smaller type, do so.
1369    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1370      return true;
1371
1372    // If all of the unknown bits are known to be zero on one side or the other
1373    // (but not both) turn this into an *inclusive* or.
1374    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1375    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1376      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1377                                               Op.getOperand(0),
1378                                               Op.getOperand(1)));
1379
1380    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1381    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1382    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1383    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1384
1385    // If all of the demanded bits on one side are known, and all of the set
1386    // bits on that side are also known to be set on the other side, turn this
1387    // into an AND, as we know the bits will be cleared.
1388    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1389    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1390      if ((KnownOne & KnownOne2) == KnownOne) {
1391        EVT VT = Op.getValueType();
1392        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1393        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1394                                                 Op.getOperand(0), ANDC));
1395      }
1396    }
1397
1398    // If the RHS is a constant, see if we can simplify it.
1399    // for XOR, we prefer to force bits to 1 if they will make a -1.
1400    // if we can't force bits, try to shrink constant
1401    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1402      APInt Expanded = C->getAPIntValue() | (~NewMask);
1403      // if we can expand it to have all bits set, do it
1404      if (Expanded.isAllOnesValue()) {
1405        if (Expanded != C->getAPIntValue()) {
1406          EVT VT = Op.getValueType();
1407          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1408                                          TLO.DAG.getConstant(Expanded, VT));
1409          return TLO.CombineTo(Op, New);
1410        }
1411        // if it already has all the bits set, nothing to change
1412        // but don't shrink either!
1413      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1414        return true;
1415      }
1416    }
1417
1418    KnownZero = KnownZeroOut;
1419    KnownOne  = KnownOneOut;
1420    break;
1421  case ISD::SELECT:
1422    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1423                             KnownOne, TLO, Depth+1))
1424      return true;
1425    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1426                             KnownOne2, TLO, Depth+1))
1427      return true;
1428    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1429    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1430
1431    // If the operands are constants, see if we can simplify them.
1432    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1433      return true;
1434
1435    // Only known if known in both the LHS and RHS.
1436    KnownOne &= KnownOne2;
1437    KnownZero &= KnownZero2;
1438    break;
1439  case ISD::SELECT_CC:
1440    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1441                             KnownOne, TLO, Depth+1))
1442      return true;
1443    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1444                             KnownOne2, TLO, Depth+1))
1445      return true;
1446    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1447    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1448
1449    // If the operands are constants, see if we can simplify them.
1450    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1451      return true;
1452
1453    // Only known if known in both the LHS and RHS.
1454    KnownOne &= KnownOne2;
1455    KnownZero &= KnownZero2;
1456    break;
1457  case ISD::SHL:
1458    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1459      unsigned ShAmt = SA->getZExtValue();
1460      SDValue InOp = Op.getOperand(0);
1461
1462      // If the shift count is an invalid immediate, don't do anything.
1463      if (ShAmt >= BitWidth)
1464        break;
1465
1466      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1467      // single shift.  We can do this if the bottom bits (which are shifted
1468      // out) are never demanded.
1469      if (InOp.getOpcode() == ISD::SRL &&
1470          isa<ConstantSDNode>(InOp.getOperand(1))) {
1471        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1472          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1473          unsigned Opc = ISD::SHL;
1474          int Diff = ShAmt-C1;
1475          if (Diff < 0) {
1476            Diff = -Diff;
1477            Opc = ISD::SRL;
1478          }
1479
1480          SDValue NewSA =
1481            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1482          EVT VT = Op.getValueType();
1483          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1484                                                   InOp.getOperand(0), NewSA));
1485        }
1486      }
1487
1488      if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1489                               KnownZero, KnownOne, TLO, Depth+1))
1490        return true;
1491
1492      // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1493      // are not demanded. This will likely allow the anyext to be folded away.
1494      if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1495        SDValue InnerOp = InOp.getNode()->getOperand(0);
1496        EVT InnerVT = InnerOp.getValueType();
1497        unsigned InnerBits = InnerVT.getSizeInBits();
1498        if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1499            isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1500          EVT ShTy = getShiftAmountTy(InnerVT);
1501          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1502            ShTy = InnerVT;
1503          SDValue NarrowShl =
1504            TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1505                            TLO.DAG.getConstant(ShAmt, ShTy));
1506          return
1507            TLO.CombineTo(Op,
1508                          TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1509                                          NarrowShl));
1510        }
1511      }
1512
1513      KnownZero <<= SA->getZExtValue();
1514      KnownOne  <<= SA->getZExtValue();
1515      // low bits known zero.
1516      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1517    }
1518    break;
1519  case ISD::SRL:
1520    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1521      EVT VT = Op.getValueType();
1522      unsigned ShAmt = SA->getZExtValue();
1523      unsigned VTSize = VT.getSizeInBits();
1524      SDValue InOp = Op.getOperand(0);
1525
1526      // If the shift count is an invalid immediate, don't do anything.
1527      if (ShAmt >= BitWidth)
1528        break;
1529
1530      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1531      // single shift.  We can do this if the top bits (which are shifted out)
1532      // are never demanded.
1533      if (InOp.getOpcode() == ISD::SHL &&
1534          isa<ConstantSDNode>(InOp.getOperand(1))) {
1535        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1536          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1537          unsigned Opc = ISD::SRL;
1538          int Diff = ShAmt-C1;
1539          if (Diff < 0) {
1540            Diff = -Diff;
1541            Opc = ISD::SHL;
1542          }
1543
1544          SDValue NewSA =
1545            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1546          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1547                                                   InOp.getOperand(0), NewSA));
1548        }
1549      }
1550
1551      // Compute the new bits that are at the top now.
1552      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1553                               KnownZero, KnownOne, TLO, Depth+1))
1554        return true;
1555      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1556      KnownZero = KnownZero.lshr(ShAmt);
1557      KnownOne  = KnownOne.lshr(ShAmt);
1558
1559      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1560      KnownZero |= HighBits;  // High bits known zero.
1561    }
1562    break;
1563  case ISD::SRA:
1564    // If this is an arithmetic shift right and only the low-bit is set, we can
1565    // always convert this into a logical shr, even if the shift amount is
1566    // variable.  The low bit of the shift cannot be an input sign bit unless
1567    // the shift amount is >= the size of the datatype, which is undefined.
1568    if (NewMask == 1)
1569      return TLO.CombineTo(Op,
1570                           TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1571                                           Op.getOperand(0), Op.getOperand(1)));
1572
1573    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1574      EVT VT = Op.getValueType();
1575      unsigned ShAmt = SA->getZExtValue();
1576
1577      // If the shift count is an invalid immediate, don't do anything.
1578      if (ShAmt >= BitWidth)
1579        break;
1580
1581      APInt InDemandedMask = (NewMask << ShAmt);
1582
1583      // If any of the demanded bits are produced by the sign extension, we also
1584      // demand the input sign bit.
1585      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1586      if (HighBits.intersects(NewMask))
1587        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1588
1589      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1590                               KnownZero, KnownOne, TLO, Depth+1))
1591        return true;
1592      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1593      KnownZero = KnownZero.lshr(ShAmt);
1594      KnownOne  = KnownOne.lshr(ShAmt);
1595
1596      // Handle the sign bit, adjusted to where it is now in the mask.
1597      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1598
1599      // If the input sign bit is known to be zero, or if none of the top bits
1600      // are demanded, turn this into an unsigned shift right.
1601      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1602        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1603                                                 Op.getOperand(0),
1604                                                 Op.getOperand(1)));
1605      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1606        KnownOne |= HighBits;
1607      }
1608    }
1609    break;
1610  case ISD::SIGN_EXTEND_INREG: {
1611    EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1612
1613    APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1614    // If we only care about the highest bit, don't bother shifting right.
1615    if (MsbMask ==  DemandedMask) {
1616      unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1617      SDValue InOp = Op.getOperand(0);
1618      // In this code we may handle vector types. We can't use the
1619      // getShiftAmountTy API because it only works on scalars.
1620      // We use the shift value type because we know that its an integer
1621      // with enough bits.
1622      SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt,
1623                                             Op.getValueType());
1624      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1625                                            Op.getValueType(), InOp, ShiftAmt));
1626    }
1627
1628    // Sign extension.  Compute the demanded bits in the result that are not
1629    // present in the input.
1630    APInt NewBits =
1631      APInt::getHighBitsSet(BitWidth,
1632                            BitWidth - ExVT.getScalarType().getSizeInBits());
1633
1634    // If none of the extended bits are demanded, eliminate the sextinreg.
1635    if ((NewBits & NewMask) == 0)
1636      return TLO.CombineTo(Op, Op.getOperand(0));
1637
1638    APInt InSignBit =
1639      APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1640    APInt InputDemandedBits =
1641      APInt::getLowBitsSet(BitWidth,
1642                           ExVT.getScalarType().getSizeInBits()) &
1643      NewMask;
1644
1645    // Since the sign extended bits are demanded, we know that the sign
1646    // bit is demanded.
1647    InputDemandedBits |= InSignBit;
1648
1649    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1650                             KnownZero, KnownOne, TLO, Depth+1))
1651      return true;
1652    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1653
1654    // If the sign bit of the input is known set or clear, then we know the
1655    // top bits of the result.
1656
1657    // If the input sign bit is known zero, convert this into a zero extension.
1658    if (KnownZero.intersects(InSignBit))
1659      return TLO.CombineTo(Op,
1660                          TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1661
1662    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1663      KnownOne |= NewBits;
1664      KnownZero &= ~NewBits;
1665    } else {                       // Input sign bit unknown
1666      KnownZero &= ~NewBits;
1667      KnownOne &= ~NewBits;
1668    }
1669    break;
1670  }
1671  case ISD::ZERO_EXTEND: {
1672    unsigned OperandBitWidth =
1673      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1674    APInt InMask = NewMask.trunc(OperandBitWidth);
1675
1676    // If none of the top bits are demanded, convert this into an any_extend.
1677    APInt NewBits =
1678      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1679    if (!NewBits.intersects(NewMask))
1680      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1681                                               Op.getValueType(),
1682                                               Op.getOperand(0)));
1683
1684    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1685                             KnownZero, KnownOne, TLO, Depth+1))
1686      return true;
1687    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1688    KnownZero = KnownZero.zext(BitWidth);
1689    KnownOne = KnownOne.zext(BitWidth);
1690    KnownZero |= NewBits;
1691    break;
1692  }
1693  case ISD::SIGN_EXTEND: {
1694    EVT InVT = Op.getOperand(0).getValueType();
1695    unsigned InBits = InVT.getScalarType().getSizeInBits();
1696    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1697    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1698    APInt NewBits   = ~InMask & NewMask;
1699
1700    // If none of the top bits are demanded, convert this into an any_extend.
1701    if (NewBits == 0)
1702      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1703                                              Op.getValueType(),
1704                                              Op.getOperand(0)));
1705
1706    // Since some of the sign extended bits are demanded, we know that the sign
1707    // bit is demanded.
1708    APInt InDemandedBits = InMask & NewMask;
1709    InDemandedBits |= InSignBit;
1710    InDemandedBits = InDemandedBits.trunc(InBits);
1711
1712    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1713                             KnownOne, TLO, Depth+1))
1714      return true;
1715    KnownZero = KnownZero.zext(BitWidth);
1716    KnownOne = KnownOne.zext(BitWidth);
1717
1718    // If the sign bit is known zero, convert this to a zero extend.
1719    if (KnownZero.intersects(InSignBit))
1720      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1721                                               Op.getValueType(),
1722                                               Op.getOperand(0)));
1723
1724    // If the sign bit is known one, the top bits match.
1725    if (KnownOne.intersects(InSignBit)) {
1726      KnownOne  |= NewBits;
1727      KnownZero &= ~NewBits;
1728    } else {   // Otherwise, top bits aren't known.
1729      KnownOne  &= ~NewBits;
1730      KnownZero &= ~NewBits;
1731    }
1732    break;
1733  }
1734  case ISD::ANY_EXTEND: {
1735    unsigned OperandBitWidth =
1736      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1737    APInt InMask = NewMask.trunc(OperandBitWidth);
1738    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1739                             KnownZero, KnownOne, TLO, Depth+1))
1740      return true;
1741    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1742    KnownZero = KnownZero.zext(BitWidth);
1743    KnownOne = KnownOne.zext(BitWidth);
1744    break;
1745  }
1746  case ISD::TRUNCATE: {
1747    // Simplify the input, using demanded bit information, and compute the known
1748    // zero/one bits live out.
1749    unsigned OperandBitWidth =
1750      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1751    APInt TruncMask = NewMask.zext(OperandBitWidth);
1752    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1753                             KnownZero, KnownOne, TLO, Depth+1))
1754      return true;
1755    KnownZero = KnownZero.trunc(BitWidth);
1756    KnownOne = KnownOne.trunc(BitWidth);
1757
1758    // If the input is only used by this truncate, see if we can shrink it based
1759    // on the known demanded bits.
1760    if (Op.getOperand(0).getNode()->hasOneUse()) {
1761      SDValue In = Op.getOperand(0);
1762      switch (In.getOpcode()) {
1763      default: break;
1764      case ISD::SRL:
1765        // Shrink SRL by a constant if none of the high bits shifted in are
1766        // demanded.
1767        if (TLO.LegalTypes() &&
1768            !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1769          // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1770          // undesirable.
1771          break;
1772        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1773        if (!ShAmt)
1774          break;
1775        SDValue Shift = In.getOperand(1);
1776        if (TLO.LegalTypes()) {
1777          uint64_t ShVal = ShAmt->getZExtValue();
1778          Shift =
1779            TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1780        }
1781
1782        APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1783                                               OperandBitWidth - BitWidth);
1784        HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1785
1786        if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1787          // None of the shifted in bits are needed.  Add a truncate of the
1788          // shift input, then shift it.
1789          SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1790                                             Op.getValueType(),
1791                                             In.getOperand(0));
1792          return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1793                                                   Op.getValueType(),
1794                                                   NewTrunc,
1795                                                   Shift));
1796        }
1797        break;
1798      }
1799    }
1800
1801    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1802    break;
1803  }
1804  case ISD::AssertZext: {
1805    // AssertZext demands all of the high bits, plus any of the low bits
1806    // demanded by its users.
1807    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1808    APInt InMask = APInt::getLowBitsSet(BitWidth,
1809                                        VT.getSizeInBits());
1810    if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1811                             KnownZero, KnownOne, TLO, Depth+1))
1812      return true;
1813    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1814
1815    KnownZero |= ~InMask & NewMask;
1816    break;
1817  }
1818  case ISD::BITCAST:
1819    // If this is an FP->Int bitcast and if the sign bit is the only
1820    // thing demanded, turn this into a FGETSIGN.
1821    if (!TLO.LegalOperations() &&
1822        !Op.getValueType().isVector() &&
1823        !Op.getOperand(0).getValueType().isVector() &&
1824        NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1825        Op.getOperand(0).getValueType().isFloatingPoint()) {
1826      bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1827      bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1828      if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1829        EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1830        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1831        // place.  We expect the SHL to be eliminated by other optimizations.
1832        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1833        unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1834        if (!OpVTLegal && OpVTSizeInBits > 32)
1835          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1836        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1837        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1838        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1839                                                 Op.getValueType(),
1840                                                 Sign, ShAmt));
1841      }
1842    }
1843    break;
1844  case ISD::ADD:
1845  case ISD::MUL:
1846  case ISD::SUB: {
1847    // Add, Sub, and Mul don't demand any bits in positions beyond that
1848    // of the highest bit demanded of them.
1849    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1850                                        BitWidth - NewMask.countLeadingZeros());
1851    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1852                             KnownOne2, TLO, Depth+1))
1853      return true;
1854    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1855                             KnownOne2, TLO, Depth+1))
1856      return true;
1857    // See if the operation should be performed at a smaller bit width.
1858    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1859      return true;
1860  }
1861  // FALL THROUGH
1862  default:
1863    // Just use ComputeMaskedBits to compute output bits.
1864    TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1865    break;
1866  }
1867
1868  // If we know the value of all of the demanded bits, return this as a
1869  // constant.
1870  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1871    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1872
1873  return false;
1874}
1875
1876/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1877/// in Mask are known to be either zero or one and return them in the
1878/// KnownZero/KnownOne bitsets.
1879void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1880                                                    const APInt &Mask,
1881                                                    APInt &KnownZero,
1882                                                    APInt &KnownOne,
1883                                                    const SelectionDAG &DAG,
1884                                                    unsigned Depth) const {
1885  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1886          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1887          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1888          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1889         "Should use MaskedValueIsZero if you don't know whether Op"
1890         " is a target node!");
1891  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1892}
1893
1894/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1895/// targets that want to expose additional information about sign bits to the
1896/// DAG Combiner.
1897unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1898                                                         unsigned Depth) const {
1899  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1900          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1901          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1902          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1903         "Should use ComputeNumSignBits if you don't know whether Op"
1904         " is a target node!");
1905  return 1;
1906}
1907
1908/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1909/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1910/// determine which bit is set.
1911///
1912static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1913  // A left-shift of a constant one will have exactly one bit set, because
1914  // shifting the bit off the end is undefined.
1915  if (Val.getOpcode() == ISD::SHL)
1916    if (ConstantSDNode *C =
1917         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1918      if (C->getAPIntValue() == 1)
1919        return true;
1920
1921  // Similarly, a right-shift of a constant sign-bit will have exactly
1922  // one bit set.
1923  if (Val.getOpcode() == ISD::SRL)
1924    if (ConstantSDNode *C =
1925         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1926      if (C->getAPIntValue().isSignBit())
1927        return true;
1928
1929  // More could be done here, though the above checks are enough
1930  // to handle some common cases.
1931
1932  // Fall back to ComputeMaskedBits to catch other known cases.
1933  EVT OpVT = Val.getValueType();
1934  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1935  APInt Mask = APInt::getAllOnesValue(BitWidth);
1936  APInt KnownZero, KnownOne;
1937  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1938  return (KnownZero.countPopulation() == BitWidth - 1) &&
1939         (KnownOne.countPopulation() == 1);
1940}
1941
1942/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1943/// and cc. If it is unable to simplify it, return a null SDValue.
1944SDValue
1945TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1946                              ISD::CondCode Cond, bool foldBooleans,
1947                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1948  SelectionDAG &DAG = DCI.DAG;
1949
1950  // These setcc operations always fold.
1951  switch (Cond) {
1952  default: break;
1953  case ISD::SETFALSE:
1954  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1955  case ISD::SETTRUE:
1956  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1957  }
1958
1959  // Ensure that the constant occurs on the RHS, and fold constant
1960  // comparisons.
1961  if (isa<ConstantSDNode>(N0.getNode()))
1962    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1963
1964  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1965    const APInt &C1 = N1C->getAPIntValue();
1966
1967    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1968    // equality comparison, then we're just comparing whether X itself is
1969    // zero.
1970    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1971        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1972        N0.getOperand(1).getOpcode() == ISD::Constant) {
1973      const APInt &ShAmt
1974        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1975      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1976          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1977        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1978          // (srl (ctlz x), 5) == 0  -> X != 0
1979          // (srl (ctlz x), 5) != 1  -> X != 0
1980          Cond = ISD::SETNE;
1981        } else {
1982          // (srl (ctlz x), 5) != 0  -> X == 0
1983          // (srl (ctlz x), 5) == 1  -> X == 0
1984          Cond = ISD::SETEQ;
1985        }
1986        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1987        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1988                            Zero, Cond);
1989      }
1990    }
1991
1992    SDValue CTPOP = N0;
1993    // Look through truncs that don't change the value of a ctpop.
1994    if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1995      CTPOP = N0.getOperand(0);
1996
1997    if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1998        (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1999                        Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
2000      EVT CTVT = CTPOP.getValueType();
2001      SDValue CTOp = CTPOP.getOperand(0);
2002
2003      // (ctpop x) u< 2 -> (x & x-1) == 0
2004      // (ctpop x) u> 1 -> (x & x-1) != 0
2005      if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2006        SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2007                                  DAG.getConstant(1, CTVT));
2008        SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2009        ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2010        return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2011      }
2012
2013      // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
2014    }
2015
2016    // (zext x) == C --> x == (trunc C)
2017    if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
2018        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2019      unsigned MinBits = N0.getValueSizeInBits();
2020      SDValue PreZExt;
2021      if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2022        // ZExt
2023        MinBits = N0->getOperand(0).getValueSizeInBits();
2024        PreZExt = N0->getOperand(0);
2025      } else if (N0->getOpcode() == ISD::AND) {
2026        // DAGCombine turns costly ZExts into ANDs
2027        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2028          if ((C->getAPIntValue()+1).isPowerOf2()) {
2029            MinBits = C->getAPIntValue().countTrailingOnes();
2030            PreZExt = N0->getOperand(0);
2031          }
2032      } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2033        // ZEXTLOAD
2034        if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2035          MinBits = LN0->getMemoryVT().getSizeInBits();
2036          PreZExt = N0;
2037        }
2038      }
2039
2040      // Make sure we're not loosing bits from the constant.
2041      if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2042        EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2043        if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2044          // Will get folded away.
2045          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2046          SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2047          return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2048        }
2049      }
2050    }
2051
2052    // If the LHS is '(and load, const)', the RHS is 0,
2053    // the test is for equality or unsigned, and all 1 bits of the const are
2054    // in the same partial word, see if we can shorten the load.
2055    if (DCI.isBeforeLegalize() &&
2056        N0.getOpcode() == ISD::AND && C1 == 0 &&
2057        N0.getNode()->hasOneUse() &&
2058        isa<LoadSDNode>(N0.getOperand(0)) &&
2059        N0.getOperand(0).getNode()->hasOneUse() &&
2060        isa<ConstantSDNode>(N0.getOperand(1))) {
2061      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2062      APInt bestMask;
2063      unsigned bestWidth = 0, bestOffset = 0;
2064      if (!Lod->isVolatile() && Lod->isUnindexed()) {
2065        unsigned origWidth = N0.getValueType().getSizeInBits();
2066        unsigned maskWidth = origWidth;
2067        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2068        // 8 bits, but have to be careful...
2069        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2070          origWidth = Lod->getMemoryVT().getSizeInBits();
2071        const APInt &Mask =
2072          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2073        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2074          APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2075          for (unsigned offset=0; offset<origWidth/width; offset++) {
2076            if ((newMask & Mask) == Mask) {
2077              if (!TD->isLittleEndian())
2078                bestOffset = (origWidth/width - offset - 1) * (width/8);
2079              else
2080                bestOffset = (uint64_t)offset * (width/8);
2081              bestMask = Mask.lshr(offset * (width/8) * 8);
2082              bestWidth = width;
2083              break;
2084            }
2085            newMask = newMask << width;
2086          }
2087        }
2088      }
2089      if (bestWidth) {
2090        EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2091        if (newVT.isRound()) {
2092          EVT PtrType = Lod->getOperand(1).getValueType();
2093          SDValue Ptr = Lod->getBasePtr();
2094          if (bestOffset != 0)
2095            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2096                              DAG.getConstant(bestOffset, PtrType));
2097          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2098          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2099                                Lod->getPointerInfo().getWithOffset(bestOffset),
2100                                        false, false, false, NewAlign);
2101          return DAG.getSetCC(dl, VT,
2102                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2103                                      DAG.getConstant(bestMask.trunc(bestWidth),
2104                                                      newVT)),
2105                              DAG.getConstant(0LL, newVT), Cond);
2106        }
2107      }
2108    }
2109
2110    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2111    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2112      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2113
2114      // If the comparison constant has bits in the upper part, the
2115      // zero-extended value could never match.
2116      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2117                                              C1.getBitWidth() - InSize))) {
2118        switch (Cond) {
2119        case ISD::SETUGT:
2120        case ISD::SETUGE:
2121        case ISD::SETEQ: return DAG.getConstant(0, VT);
2122        case ISD::SETULT:
2123        case ISD::SETULE:
2124        case ISD::SETNE: return DAG.getConstant(1, VT);
2125        case ISD::SETGT:
2126        case ISD::SETGE:
2127          // True if the sign bit of C1 is set.
2128          return DAG.getConstant(C1.isNegative(), VT);
2129        case ISD::SETLT:
2130        case ISD::SETLE:
2131          // True if the sign bit of C1 isn't set.
2132          return DAG.getConstant(C1.isNonNegative(), VT);
2133        default:
2134          break;
2135        }
2136      }
2137
2138      // Otherwise, we can perform the comparison with the low bits.
2139      switch (Cond) {
2140      case ISD::SETEQ:
2141      case ISD::SETNE:
2142      case ISD::SETUGT:
2143      case ISD::SETUGE:
2144      case ISD::SETULT:
2145      case ISD::SETULE: {
2146        EVT newVT = N0.getOperand(0).getValueType();
2147        if (DCI.isBeforeLegalizeOps() ||
2148            (isOperationLegal(ISD::SETCC, newVT) &&
2149              getCondCodeAction(Cond, newVT)==Legal))
2150          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2151                              DAG.getConstant(C1.trunc(InSize), newVT),
2152                              Cond);
2153        break;
2154      }
2155      default:
2156        break;   // todo, be more careful with signed comparisons
2157      }
2158    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2159               (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2160      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2161      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2162      EVT ExtDstTy = N0.getValueType();
2163      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2164
2165      // If the constant doesn't fit into the number of bits for the source of
2166      // the sign extension, it is impossible for both sides to be equal.
2167      if (C1.getMinSignedBits() > ExtSrcTyBits)
2168        return DAG.getConstant(Cond == ISD::SETNE, VT);
2169
2170      SDValue ZextOp;
2171      EVT Op0Ty = N0.getOperand(0).getValueType();
2172      if (Op0Ty == ExtSrcTy) {
2173        ZextOp = N0.getOperand(0);
2174      } else {
2175        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2176        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2177                              DAG.getConstant(Imm, Op0Ty));
2178      }
2179      if (!DCI.isCalledByLegalizer())
2180        DCI.AddToWorklist(ZextOp.getNode());
2181      // Otherwise, make this a use of a zext.
2182      return DAG.getSetCC(dl, VT, ZextOp,
2183                          DAG.getConstant(C1 & APInt::getLowBitsSet(
2184                                                              ExtDstTyBits,
2185                                                              ExtSrcTyBits),
2186                                          ExtDstTy),
2187                          Cond);
2188    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2189                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2190      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2191      if (N0.getOpcode() == ISD::SETCC &&
2192          isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2193        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2194        if (TrueWhenTrue)
2195          return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2196        // Invert the condition.
2197        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2198        CC = ISD::getSetCCInverse(CC,
2199                                  N0.getOperand(0).getValueType().isInteger());
2200        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2201      }
2202
2203      if ((N0.getOpcode() == ISD::XOR ||
2204           (N0.getOpcode() == ISD::AND &&
2205            N0.getOperand(0).getOpcode() == ISD::XOR &&
2206            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2207          isa<ConstantSDNode>(N0.getOperand(1)) &&
2208          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2209        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
2210        // can only do this if the top bits are known zero.
2211        unsigned BitWidth = N0.getValueSizeInBits();
2212        if (DAG.MaskedValueIsZero(N0,
2213                                  APInt::getHighBitsSet(BitWidth,
2214                                                        BitWidth-1))) {
2215          // Okay, get the un-inverted input value.
2216          SDValue Val;
2217          if (N0.getOpcode() == ISD::XOR)
2218            Val = N0.getOperand(0);
2219          else {
2220            assert(N0.getOpcode() == ISD::AND &&
2221                    N0.getOperand(0).getOpcode() == ISD::XOR);
2222            // ((X^1)&1)^1 -> X & 1
2223            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2224                              N0.getOperand(0).getOperand(0),
2225                              N0.getOperand(1));
2226          }
2227
2228          return DAG.getSetCC(dl, VT, Val, N1,
2229                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2230        }
2231      } else if (N1C->getAPIntValue() == 1 &&
2232                 (VT == MVT::i1 ||
2233                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2234        SDValue Op0 = N0;
2235        if (Op0.getOpcode() == ISD::TRUNCATE)
2236          Op0 = Op0.getOperand(0);
2237
2238        if ((Op0.getOpcode() == ISD::XOR) &&
2239            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2240            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2241          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2242          Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2243          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2244                              Cond);
2245        } else if (Op0.getOpcode() == ISD::AND &&
2246                isa<ConstantSDNode>(Op0.getOperand(1)) &&
2247                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2248          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2249          if (Op0.getValueType().bitsGT(VT))
2250            Op0 = DAG.getNode(ISD::AND, dl, VT,
2251                          DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2252                          DAG.getConstant(1, VT));
2253          else if (Op0.getValueType().bitsLT(VT))
2254            Op0 = DAG.getNode(ISD::AND, dl, VT,
2255                        DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2256                        DAG.getConstant(1, VT));
2257
2258          return DAG.getSetCC(dl, VT, Op0,
2259                              DAG.getConstant(0, Op0.getValueType()),
2260                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2261        }
2262      }
2263    }
2264
2265    APInt MinVal, MaxVal;
2266    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2267    if (ISD::isSignedIntSetCC(Cond)) {
2268      MinVal = APInt::getSignedMinValue(OperandBitSize);
2269      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2270    } else {
2271      MinVal = APInt::getMinValue(OperandBitSize);
2272      MaxVal = APInt::getMaxValue(OperandBitSize);
2273    }
2274
2275    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2276    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2277      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2278      // X >= C0 --> X > (C0-1)
2279      return DAG.getSetCC(dl, VT, N0,
2280                          DAG.getConstant(C1-1, N1.getValueType()),
2281                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2282    }
2283
2284    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2285      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2286      // X <= C0 --> X < (C0+1)
2287      return DAG.getSetCC(dl, VT, N0,
2288                          DAG.getConstant(C1+1, N1.getValueType()),
2289                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2290    }
2291
2292    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2293      return DAG.getConstant(0, VT);      // X < MIN --> false
2294    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2295      return DAG.getConstant(1, VT);      // X >= MIN --> true
2296    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2297      return DAG.getConstant(0, VT);      // X > MAX --> false
2298    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2299      return DAG.getConstant(1, VT);      // X <= MAX --> true
2300
2301    // Canonicalize setgt X, Min --> setne X, Min
2302    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2303      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2304    // Canonicalize setlt X, Max --> setne X, Max
2305    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2306      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2307
2308    // If we have setult X, 1, turn it into seteq X, 0
2309    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2310      return DAG.getSetCC(dl, VT, N0,
2311                          DAG.getConstant(MinVal, N0.getValueType()),
2312                          ISD::SETEQ);
2313    // If we have setugt X, Max-1, turn it into seteq X, Max
2314    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2315      return DAG.getSetCC(dl, VT, N0,
2316                          DAG.getConstant(MaxVal, N0.getValueType()),
2317                          ISD::SETEQ);
2318
2319    // If we have "setcc X, C0", check to see if we can shrink the immediate
2320    // by changing cc.
2321
2322    // SETUGT X, SINTMAX  -> SETLT X, 0
2323    if (Cond == ISD::SETUGT &&
2324        C1 == APInt::getSignedMaxValue(OperandBitSize))
2325      return DAG.getSetCC(dl, VT, N0,
2326                          DAG.getConstant(0, N1.getValueType()),
2327                          ISD::SETLT);
2328
2329    // SETULT X, SINTMIN  -> SETGT X, -1
2330    if (Cond == ISD::SETULT &&
2331        C1 == APInt::getSignedMinValue(OperandBitSize)) {
2332      SDValue ConstMinusOne =
2333          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2334                          N1.getValueType());
2335      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2336    }
2337
2338    // Fold bit comparisons when we can.
2339    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2340        (VT == N0.getValueType() ||
2341         (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2342        N0.getOpcode() == ISD::AND)
2343      if (ConstantSDNode *AndRHS =
2344                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2345        EVT ShiftTy = DCI.isBeforeLegalize() ?
2346          getPointerTy() : getShiftAmountTy(N0.getValueType());
2347        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2348          // Perform the xform if the AND RHS is a single bit.
2349          if (AndRHS->getAPIntValue().isPowerOf2()) {
2350            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2351                              DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2352                   DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2353          }
2354        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2355          // (X & 8) == 8  -->  (X & 8) >> 3
2356          // Perform the xform if C1 is a single bit.
2357          if (C1.isPowerOf2()) {
2358            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2359                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2360                                      DAG.getConstant(C1.logBase2(), ShiftTy)));
2361          }
2362        }
2363      }
2364  }
2365
2366  if (isa<ConstantFPSDNode>(N0.getNode())) {
2367    // Constant fold or commute setcc.
2368    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2369    if (O.getNode()) return O;
2370  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2371    // If the RHS of an FP comparison is a constant, simplify it away in
2372    // some cases.
2373    if (CFP->getValueAPF().isNaN()) {
2374      // If an operand is known to be a nan, we can fold it.
2375      switch (ISD::getUnorderedFlavor(Cond)) {
2376      default: llvm_unreachable("Unknown flavor!");
2377      case 0:  // Known false.
2378        return DAG.getConstant(0, VT);
2379      case 1:  // Known true.
2380        return DAG.getConstant(1, VT);
2381      case 2:  // Undefined.
2382        return DAG.getUNDEF(VT);
2383      }
2384    }
2385
2386    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
2387    // constant if knowing that the operand is non-nan is enough.  We prefer to
2388    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2389    // materialize 0.0.
2390    if (Cond == ISD::SETO || Cond == ISD::SETUO)
2391      return DAG.getSetCC(dl, VT, N0, N0, Cond);
2392
2393    // If the condition is not legal, see if we can find an equivalent one
2394    // which is legal.
2395    if (!isCondCodeLegal(Cond, N0.getValueType())) {
2396      // If the comparison was an awkward floating-point == or != and one of
2397      // the comparison operands is infinity or negative infinity, convert the
2398      // condition to a less-awkward <= or >=.
2399      if (CFP->getValueAPF().isInfinity()) {
2400        if (CFP->getValueAPF().isNegative()) {
2401          if (Cond == ISD::SETOEQ &&
2402              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2403            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2404          if (Cond == ISD::SETUEQ &&
2405              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2406            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2407          if (Cond == ISD::SETUNE &&
2408              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2409            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2410          if (Cond == ISD::SETONE &&
2411              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2412            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2413        } else {
2414          if (Cond == ISD::SETOEQ &&
2415              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2416            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2417          if (Cond == ISD::SETUEQ &&
2418              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2419            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2420          if (Cond == ISD::SETUNE &&
2421              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2422            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2423          if (Cond == ISD::SETONE &&
2424              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2425            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2426        }
2427      }
2428    }
2429  }
2430
2431  if (N0 == N1) {
2432    // We can always fold X == X for integer setcc's.
2433    if (N0.getValueType().isInteger())
2434      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2435    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2436    if (UOF == 2)   // FP operators that are undefined on NaNs.
2437      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2438    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2439      return DAG.getConstant(UOF, VT);
2440    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2441    // if it is not already.
2442    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2443    if (NewCond != Cond)
2444      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2445  }
2446
2447  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2448      N0.getValueType().isInteger()) {
2449    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2450        N0.getOpcode() == ISD::XOR) {
2451      // Simplify (X+Y) == (X+Z) -->  Y == Z
2452      if (N0.getOpcode() == N1.getOpcode()) {
2453        if (N0.getOperand(0) == N1.getOperand(0))
2454          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2455        if (N0.getOperand(1) == N1.getOperand(1))
2456          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2457        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2458          // If X op Y == Y op X, try other combinations.
2459          if (N0.getOperand(0) == N1.getOperand(1))
2460            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2461                                Cond);
2462          if (N0.getOperand(1) == N1.getOperand(0))
2463            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2464                                Cond);
2465        }
2466      }
2467
2468      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2469        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2470          // Turn (X+C1) == C2 --> X == C2-C1
2471          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2472            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2473                                DAG.getConstant(RHSC->getAPIntValue()-
2474                                                LHSR->getAPIntValue(),
2475                                N0.getValueType()), Cond);
2476          }
2477
2478          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2479          if (N0.getOpcode() == ISD::XOR)
2480            // If we know that all of the inverted bits are zero, don't bother
2481            // performing the inversion.
2482            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2483              return
2484                DAG.getSetCC(dl, VT, N0.getOperand(0),
2485                             DAG.getConstant(LHSR->getAPIntValue() ^
2486                                               RHSC->getAPIntValue(),
2487                                             N0.getValueType()),
2488                             Cond);
2489        }
2490
2491        // Turn (C1-X) == C2 --> X == C1-C2
2492        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2493          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2494            return
2495              DAG.getSetCC(dl, VT, N0.getOperand(1),
2496                           DAG.getConstant(SUBC->getAPIntValue() -
2497                                             RHSC->getAPIntValue(),
2498                                           N0.getValueType()),
2499                           Cond);
2500          }
2501        }
2502      }
2503
2504      // Simplify (X+Z) == X -->  Z == 0
2505      if (N0.getOperand(0) == N1)
2506        return DAG.getSetCC(dl, VT, N0.getOperand(1),
2507                        DAG.getConstant(0, N0.getValueType()), Cond);
2508      if (N0.getOperand(1) == N1) {
2509        if (DAG.isCommutativeBinOp(N0.getOpcode()))
2510          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2511                          DAG.getConstant(0, N0.getValueType()), Cond);
2512        else if (N0.getNode()->hasOneUse()) {
2513          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2514          // (Z-X) == X  --> Z == X<<1
2515          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2516                                     N1,
2517                       DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2518          if (!DCI.isCalledByLegalizer())
2519            DCI.AddToWorklist(SH.getNode());
2520          return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2521        }
2522      }
2523    }
2524
2525    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2526        N1.getOpcode() == ISD::XOR) {
2527      // Simplify  X == (X+Z) -->  Z == 0
2528      if (N1.getOperand(0) == N0) {
2529        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2530                        DAG.getConstant(0, N1.getValueType()), Cond);
2531      } else if (N1.getOperand(1) == N0) {
2532        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2533          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2534                          DAG.getConstant(0, N1.getValueType()), Cond);
2535        } else if (N1.getNode()->hasOneUse()) {
2536          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2537          // X == (Z-X)  --> X<<1 == Z
2538          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2539                       DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2540          if (!DCI.isCalledByLegalizer())
2541            DCI.AddToWorklist(SH.getNode());
2542          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2543        }
2544      }
2545    }
2546
2547    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2548    // Note that where y is variable and is known to have at most
2549    // one bit set (for example, if it is z&1) we cannot do this;
2550    // the expressions are not equivalent when y==0.
2551    if (N0.getOpcode() == ISD::AND)
2552      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2553        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2554          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2555          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2556          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2557        }
2558      }
2559    if (N1.getOpcode() == ISD::AND)
2560      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2561        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2562          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2563          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2564          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2565        }
2566      }
2567  }
2568
2569  // Fold away ALL boolean setcc's.
2570  SDValue Temp;
2571  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2572    switch (Cond) {
2573    default: llvm_unreachable("Unknown integer setcc!");
2574    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2575      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2576      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2577      if (!DCI.isCalledByLegalizer())
2578        DCI.AddToWorklist(Temp.getNode());
2579      break;
2580    case ISD::SETNE:  // X != Y   -->  (X^Y)
2581      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2582      break;
2583    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2584    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2585      Temp = DAG.getNOT(dl, N0, MVT::i1);
2586      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2587      if (!DCI.isCalledByLegalizer())
2588        DCI.AddToWorklist(Temp.getNode());
2589      break;
2590    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2591    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2592      Temp = DAG.getNOT(dl, N1, MVT::i1);
2593      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2594      if (!DCI.isCalledByLegalizer())
2595        DCI.AddToWorklist(Temp.getNode());
2596      break;
2597    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2598    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2599      Temp = DAG.getNOT(dl, N0, MVT::i1);
2600      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2601      if (!DCI.isCalledByLegalizer())
2602        DCI.AddToWorklist(Temp.getNode());
2603      break;
2604    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2605    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2606      Temp = DAG.getNOT(dl, N1, MVT::i1);
2607      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2608      break;
2609    }
2610    if (VT != MVT::i1) {
2611      if (!DCI.isCalledByLegalizer())
2612        DCI.AddToWorklist(N0.getNode());
2613      // FIXME: If running after legalize, we probably can't do this.
2614      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2615    }
2616    return N0;
2617  }
2618
2619  // Could not fold it.
2620  return SDValue();
2621}
2622
2623/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2624/// node is a GlobalAddress + offset.
2625bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2626                                    int64_t &Offset) const {
2627  if (isa<GlobalAddressSDNode>(N)) {
2628    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2629    GA = GASD->getGlobal();
2630    Offset += GASD->getOffset();
2631    return true;
2632  }
2633
2634  if (N->getOpcode() == ISD::ADD) {
2635    SDValue N1 = N->getOperand(0);
2636    SDValue N2 = N->getOperand(1);
2637    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2638      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2639      if (V) {
2640        Offset += V->getSExtValue();
2641        return true;
2642      }
2643    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2644      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2645      if (V) {
2646        Offset += V->getSExtValue();
2647        return true;
2648      }
2649    }
2650  }
2651
2652  return false;
2653}
2654
2655
2656SDValue TargetLowering::
2657PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2658  // Default implementation: no optimization.
2659  return SDValue();
2660}
2661
2662//===----------------------------------------------------------------------===//
2663//  Inline Assembler Implementation Methods
2664//===----------------------------------------------------------------------===//
2665
2666
2667TargetLowering::ConstraintType
2668TargetLowering::getConstraintType(const std::string &Constraint) const {
2669  if (Constraint.size() == 1) {
2670    switch (Constraint[0]) {
2671    default: break;
2672    case 'r': return C_RegisterClass;
2673    case 'm':    // memory
2674    case 'o':    // offsetable
2675    case 'V':    // not offsetable
2676      return C_Memory;
2677    case 'i':    // Simple Integer or Relocatable Constant
2678    case 'n':    // Simple Integer
2679    case 'E':    // Floating Point Constant
2680    case 'F':    // Floating Point Constant
2681    case 's':    // Relocatable Constant
2682    case 'p':    // Address.
2683    case 'X':    // Allow ANY value.
2684    case 'I':    // Target registers.
2685    case 'J':
2686    case 'K':
2687    case 'L':
2688    case 'M':
2689    case 'N':
2690    case 'O':
2691    case 'P':
2692    case '<':
2693    case '>':
2694      return C_Other;
2695    }
2696  }
2697
2698  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2699      Constraint[Constraint.size()-1] == '}')
2700    return C_Register;
2701  return C_Unknown;
2702}
2703
2704/// LowerXConstraint - try to replace an X constraint, which matches anything,
2705/// with another that has more specific requirements based on the type of the
2706/// corresponding operand.
2707const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2708  if (ConstraintVT.isInteger())
2709    return "r";
2710  if (ConstraintVT.isFloatingPoint())
2711    return "f";      // works for many targets
2712  return 0;
2713}
2714
2715/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2716/// vector.  If it is invalid, don't add anything to Ops.
2717void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2718                                                  std::string &Constraint,
2719                                                  std::vector<SDValue> &Ops,
2720                                                  SelectionDAG &DAG) const {
2721
2722  if (Constraint.length() > 1) return;
2723
2724  char ConstraintLetter = Constraint[0];
2725  switch (ConstraintLetter) {
2726  default: break;
2727  case 'X':     // Allows any operand; labels (basic block) use this.
2728    if (Op.getOpcode() == ISD::BasicBlock) {
2729      Ops.push_back(Op);
2730      return;
2731    }
2732    // fall through
2733  case 'i':    // Simple Integer or Relocatable Constant
2734  case 'n':    // Simple Integer
2735  case 's': {  // Relocatable Constant
2736    // These operands are interested in values of the form (GV+C), where C may
2737    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2738    // is possible and fine if either GV or C are missing.
2739    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2740    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2741
2742    // If we have "(add GV, C)", pull out GV/C
2743    if (Op.getOpcode() == ISD::ADD) {
2744      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2745      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2746      if (C == 0 || GA == 0) {
2747        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2748        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2749      }
2750      if (C == 0 || GA == 0)
2751        C = 0, GA = 0;
2752    }
2753
2754    // If we find a valid operand, map to the TargetXXX version so that the
2755    // value itself doesn't get selected.
2756    if (GA) {   // Either &GV   or   &GV+C
2757      if (ConstraintLetter != 'n') {
2758        int64_t Offs = GA->getOffset();
2759        if (C) Offs += C->getZExtValue();
2760        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2761                                                 C ? C->getDebugLoc() : DebugLoc(),
2762                                                 Op.getValueType(), Offs));
2763        return;
2764      }
2765    }
2766    if (C) {   // just C, no GV.
2767      // Simple constants are not allowed for 's'.
2768      if (ConstraintLetter != 's') {
2769        // gcc prints these as sign extended.  Sign extend value to 64 bits
2770        // now; without this it would get ZExt'd later in
2771        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2772        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2773                                            MVT::i64));
2774        return;
2775      }
2776    }
2777    break;
2778  }
2779  }
2780}
2781
2782std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2783getRegForInlineAsmConstraint(const std::string &Constraint,
2784                             EVT VT) const {
2785  if (Constraint[0] != '{')
2786    return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2787  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2788
2789  // Remove the braces from around the name.
2790  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2791
2792  // Figure out which register class contains this reg.
2793  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2794  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2795       E = RI->regclass_end(); RCI != E; ++RCI) {
2796    const TargetRegisterClass *RC = *RCI;
2797
2798    // If none of the value types for this register class are valid, we
2799    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2800    if (!isLegalRC(RC))
2801      continue;
2802
2803    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2804         I != E; ++I) {
2805      if (RegName.equals_lower(RI->getName(*I)))
2806        return std::make_pair(*I, RC);
2807    }
2808  }
2809
2810  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2811}
2812
2813//===----------------------------------------------------------------------===//
2814// Constraint Selection.
2815
2816/// isMatchingInputConstraint - Return true of this is an input operand that is
2817/// a matching constraint like "4".
2818bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2819  assert(!ConstraintCode.empty() && "No known constraint!");
2820  return isdigit(ConstraintCode[0]);
2821}
2822
2823/// getMatchedOperand - If this is an input matching constraint, this method
2824/// returns the output operand it matches.
2825unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2826  assert(!ConstraintCode.empty() && "No known constraint!");
2827  return atoi(ConstraintCode.c_str());
2828}
2829
2830
2831/// ParseConstraints - Split up the constraint string from the inline
2832/// assembly value into the specific constraints and their prefixes,
2833/// and also tie in the associated operand values.
2834/// If this returns an empty vector, and if the constraint string itself
2835/// isn't empty, there was an error parsing.
2836TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2837    ImmutableCallSite CS) const {
2838  /// ConstraintOperands - Information about all of the constraints.
2839  AsmOperandInfoVector ConstraintOperands;
2840  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2841  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2842
2843  // Do a prepass over the constraints, canonicalizing them, and building up the
2844  // ConstraintOperands list.
2845  InlineAsm::ConstraintInfoVector
2846    ConstraintInfos = IA->ParseConstraints();
2847
2848  unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
2849  unsigned ResNo = 0;   // ResNo - The result number of the next output.
2850
2851  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2852    ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2853    AsmOperandInfo &OpInfo = ConstraintOperands.back();
2854
2855    // Update multiple alternative constraint count.
2856    if (OpInfo.multipleAlternatives.size() > maCount)
2857      maCount = OpInfo.multipleAlternatives.size();
2858
2859    OpInfo.ConstraintVT = MVT::Other;
2860
2861    // Compute the value type for each operand.
2862    switch (OpInfo.Type) {
2863    case InlineAsm::isOutput:
2864      // Indirect outputs just consume an argument.
2865      if (OpInfo.isIndirect) {
2866        OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2867        break;
2868      }
2869
2870      // The return value of the call is this value.  As such, there is no
2871      // corresponding argument.
2872      assert(!CS.getType()->isVoidTy() &&
2873             "Bad inline asm!");
2874      if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2875        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2876      } else {
2877        assert(ResNo == 0 && "Asm only has one result!");
2878        OpInfo.ConstraintVT = getValueType(CS.getType());
2879      }
2880      ++ResNo;
2881      break;
2882    case InlineAsm::isInput:
2883      OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2884      break;
2885    case InlineAsm::isClobber:
2886      // Nothing to do.
2887      break;
2888    }
2889
2890    if (OpInfo.CallOperandVal) {
2891      llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2892      if (OpInfo.isIndirect) {
2893        llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2894        if (!PtrTy)
2895          report_fatal_error("Indirect operand for inline asm not a pointer!");
2896        OpTy = PtrTy->getElementType();
2897      }
2898
2899      // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2900      if (StructType *STy = dyn_cast<StructType>(OpTy))
2901        if (STy->getNumElements() == 1)
2902          OpTy = STy->getElementType(0);
2903
2904      // If OpTy is not a single value, it may be a struct/union that we
2905      // can tile with integers.
2906      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2907        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2908        switch (BitSize) {
2909        default: break;
2910        case 1:
2911        case 8:
2912        case 16:
2913        case 32:
2914        case 64:
2915        case 128:
2916          OpInfo.ConstraintVT =
2917              EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2918          break;
2919        }
2920      } else if (dyn_cast<PointerType>(OpTy)) {
2921        OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2922      } else {
2923        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2924      }
2925    }
2926  }
2927
2928  // If we have multiple alternative constraints, select the best alternative.
2929  if (ConstraintInfos.size()) {
2930    if (maCount) {
2931      unsigned bestMAIndex = 0;
2932      int bestWeight = -1;
2933      // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
2934      int weight = -1;
2935      unsigned maIndex;
2936      // Compute the sums of the weights for each alternative, keeping track
2937      // of the best (highest weight) one so far.
2938      for (maIndex = 0; maIndex < maCount; ++maIndex) {
2939        int weightSum = 0;
2940        for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2941            cIndex != eIndex; ++cIndex) {
2942          AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2943          if (OpInfo.Type == InlineAsm::isClobber)
2944            continue;
2945
2946          // If this is an output operand with a matching input operand,
2947          // look up the matching input. If their types mismatch, e.g. one
2948          // is an integer, the other is floating point, or their sizes are
2949          // different, flag it as an maCantMatch.
2950          if (OpInfo.hasMatchingInput()) {
2951            AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2952            if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2953              if ((OpInfo.ConstraintVT.isInteger() !=
2954                   Input.ConstraintVT.isInteger()) ||
2955                  (OpInfo.ConstraintVT.getSizeInBits() !=
2956                   Input.ConstraintVT.getSizeInBits())) {
2957                weightSum = -1;  // Can't match.
2958                break;
2959              }
2960            }
2961          }
2962          weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2963          if (weight == -1) {
2964            weightSum = -1;
2965            break;
2966          }
2967          weightSum += weight;
2968        }
2969        // Update best.
2970        if (weightSum > bestWeight) {
2971          bestWeight = weightSum;
2972          bestMAIndex = maIndex;
2973        }
2974      }
2975
2976      // Now select chosen alternative in each constraint.
2977      for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2978          cIndex != eIndex; ++cIndex) {
2979        AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2980        if (cInfo.Type == InlineAsm::isClobber)
2981          continue;
2982        cInfo.selectAlternative(bestMAIndex);
2983      }
2984    }
2985  }
2986
2987  // Check and hook up tied operands, choose constraint code to use.
2988  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2989      cIndex != eIndex; ++cIndex) {
2990    AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2991
2992    // If this is an output operand with a matching input operand, look up the
2993    // matching input. If their types mismatch, e.g. one is an integer, the
2994    // other is floating point, or their sizes are different, flag it as an
2995    // error.
2996    if (OpInfo.hasMatchingInput()) {
2997      AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2998
2999      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3000	std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3001	  getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
3002	std::pair<unsigned, const TargetRegisterClass*> InputRC =
3003	  getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
3004        if ((OpInfo.ConstraintVT.isInteger() !=
3005             Input.ConstraintVT.isInteger()) ||
3006            (MatchRC.second != InputRC.second)) {
3007          report_fatal_error("Unsupported asm: input constraint"
3008                             " with a matching output constraint of"
3009                             " incompatible type!");
3010        }
3011      }
3012
3013    }
3014  }
3015
3016  return ConstraintOperands;
3017}
3018
3019
3020/// getConstraintGenerality - Return an integer indicating how general CT
3021/// is.
3022static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3023  switch (CT) {
3024  case TargetLowering::C_Other:
3025  case TargetLowering::C_Unknown:
3026    return 0;
3027  case TargetLowering::C_Register:
3028    return 1;
3029  case TargetLowering::C_RegisterClass:
3030    return 2;
3031  case TargetLowering::C_Memory:
3032    return 3;
3033  }
3034  llvm_unreachable("Invalid constraint type");
3035}
3036
3037/// Examine constraint type and operand type and determine a weight value.
3038/// This object must already have been set up with the operand type
3039/// and the current alternative constraint selected.
3040TargetLowering::ConstraintWeight
3041  TargetLowering::getMultipleConstraintMatchWeight(
3042    AsmOperandInfo &info, int maIndex) const {
3043  InlineAsm::ConstraintCodeVector *rCodes;
3044  if (maIndex >= (int)info.multipleAlternatives.size())
3045    rCodes = &info.Codes;
3046  else
3047    rCodes = &info.multipleAlternatives[maIndex].Codes;
3048  ConstraintWeight BestWeight = CW_Invalid;
3049
3050  // Loop over the options, keeping track of the most general one.
3051  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3052    ConstraintWeight weight =
3053      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3054    if (weight > BestWeight)
3055      BestWeight = weight;
3056  }
3057
3058  return BestWeight;
3059}
3060
3061/// Examine constraint type and operand type and determine a weight value.
3062/// This object must already have been set up with the operand type
3063/// and the current alternative constraint selected.
3064TargetLowering::ConstraintWeight
3065  TargetLowering::getSingleConstraintMatchWeight(
3066    AsmOperandInfo &info, const char *constraint) const {
3067  ConstraintWeight weight = CW_Invalid;
3068  Value *CallOperandVal = info.CallOperandVal;
3069    // If we don't have a value, we can't do a match,
3070    // but allow it at the lowest weight.
3071  if (CallOperandVal == NULL)
3072    return CW_Default;
3073  // Look at the constraint type.
3074  switch (*constraint) {
3075    case 'i': // immediate integer.
3076    case 'n': // immediate integer with a known value.
3077      if (isa<ConstantInt>(CallOperandVal))
3078        weight = CW_Constant;
3079      break;
3080    case 's': // non-explicit intregal immediate.
3081      if (isa<GlobalValue>(CallOperandVal))
3082        weight = CW_Constant;
3083      break;
3084    case 'E': // immediate float if host format.
3085    case 'F': // immediate float.
3086      if (isa<ConstantFP>(CallOperandVal))
3087        weight = CW_Constant;
3088      break;
3089    case '<': // memory operand with autodecrement.
3090    case '>': // memory operand with autoincrement.
3091    case 'm': // memory operand.
3092    case 'o': // offsettable memory operand
3093    case 'V': // non-offsettable memory operand
3094      weight = CW_Memory;
3095      break;
3096    case 'r': // general register.
3097    case 'g': // general register, memory operand or immediate integer.
3098              // note: Clang converts "g" to "imr".
3099      if (CallOperandVal->getType()->isIntegerTy())
3100        weight = CW_Register;
3101      break;
3102    case 'X': // any operand.
3103    default:
3104      weight = CW_Default;
3105      break;
3106  }
3107  return weight;
3108}
3109
3110/// ChooseConstraint - If there are multiple different constraints that we
3111/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3112/// This is somewhat tricky: constraints fall into four classes:
3113///    Other         -> immediates and magic values
3114///    Register      -> one specific register
3115///    RegisterClass -> a group of regs
3116///    Memory        -> memory
3117/// Ideally, we would pick the most specific constraint possible: if we have
3118/// something that fits into a register, we would pick it.  The problem here
3119/// is that if we have something that could either be in a register or in
3120/// memory that use of the register could cause selection of *other*
3121/// operands to fail: they might only succeed if we pick memory.  Because of
3122/// this the heuristic we use is:
3123///
3124///  1) If there is an 'other' constraint, and if the operand is valid for
3125///     that constraint, use it.  This makes us take advantage of 'i'
3126///     constraints when available.
3127///  2) Otherwise, pick the most general constraint present.  This prefers
3128///     'm' over 'r', for example.
3129///
3130static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3131                             const TargetLowering &TLI,
3132                             SDValue Op, SelectionDAG *DAG) {
3133  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3134  unsigned BestIdx = 0;
3135  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3136  int BestGenerality = -1;
3137
3138  // Loop over the options, keeping track of the most general one.
3139  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3140    TargetLowering::ConstraintType CType =
3141      TLI.getConstraintType(OpInfo.Codes[i]);
3142
3143    // If this is an 'other' constraint, see if the operand is valid for it.
3144    // For example, on X86 we might have an 'rI' constraint.  If the operand
3145    // is an integer in the range [0..31] we want to use I (saving a load
3146    // of a register), otherwise we must use 'r'.
3147    if (CType == TargetLowering::C_Other && Op.getNode()) {
3148      assert(OpInfo.Codes[i].size() == 1 &&
3149             "Unhandled multi-letter 'other' constraint");
3150      std::vector<SDValue> ResultOps;
3151      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3152                                       ResultOps, *DAG);
3153      if (!ResultOps.empty()) {
3154        BestType = CType;
3155        BestIdx = i;
3156        break;
3157      }
3158    }
3159
3160    // Things with matching constraints can only be registers, per gcc
3161    // documentation.  This mainly affects "g" constraints.
3162    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3163      continue;
3164
3165    // This constraint letter is more general than the previous one, use it.
3166    int Generality = getConstraintGenerality(CType);
3167    if (Generality > BestGenerality) {
3168      BestType = CType;
3169      BestIdx = i;
3170      BestGenerality = Generality;
3171    }
3172  }
3173
3174  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3175  OpInfo.ConstraintType = BestType;
3176}
3177
3178/// ComputeConstraintToUse - Determines the constraint code and constraint
3179/// type to use for the specific AsmOperandInfo, setting
3180/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3181void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3182                                            SDValue Op,
3183                                            SelectionDAG *DAG) const {
3184  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3185
3186  // Single-letter constraints ('r') are very common.
3187  if (OpInfo.Codes.size() == 1) {
3188    OpInfo.ConstraintCode = OpInfo.Codes[0];
3189    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3190  } else {
3191    ChooseConstraint(OpInfo, *this, Op, DAG);
3192  }
3193
3194  // 'X' matches anything.
3195  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3196    // Labels and constants are handled elsewhere ('X' is the only thing
3197    // that matches labels).  For Functions, the type here is the type of
3198    // the result, which is not what we want to look at; leave them alone.
3199    Value *v = OpInfo.CallOperandVal;
3200    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3201      OpInfo.CallOperandVal = v;
3202      return;
3203    }
3204
3205    // Otherwise, try to resolve it to something we know about by looking at
3206    // the actual operand type.
3207    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3208      OpInfo.ConstraintCode = Repl;
3209      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3210    }
3211  }
3212}
3213
3214//===----------------------------------------------------------------------===//
3215//  Loop Strength Reduction hooks
3216//===----------------------------------------------------------------------===//
3217
3218/// isLegalAddressingMode - Return true if the addressing mode represented
3219/// by AM is legal for this target, for a load/store of the specified type.
3220bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3221                                           Type *Ty) const {
3222  // The default implementation of this implements a conservative RISCy, r+r and
3223  // r+i addr mode.
3224
3225  // Allows a sign-extended 16-bit immediate field.
3226  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3227    return false;
3228
3229  // No global is ever allowed as a base.
3230  if (AM.BaseGV)
3231    return false;
3232
3233  // Only support r+r,
3234  switch (AM.Scale) {
3235  case 0:  // "r+i" or just "i", depending on HasBaseReg.
3236    break;
3237  case 1:
3238    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
3239      return false;
3240    // Otherwise we have r+r or r+i.
3241    break;
3242  case 2:
3243    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
3244      return false;
3245    // Allow 2*r as r+r.
3246    break;
3247  }
3248
3249  return true;
3250}
3251
3252/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3253/// with the multiplicative inverse of the constant.
3254SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3255                                       SelectionDAG &DAG) const {
3256  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3257  APInt d = C->getAPIntValue();
3258  assert(d != 0 && "Division by zero!");
3259
3260  // Shift the value upfront if it is even, so the LSB is one.
3261  unsigned ShAmt = d.countTrailingZeros();
3262  if (ShAmt) {
3263    // TODO: For UDIV use SRL instead of SRA.
3264    SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3265    Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3266    d = d.ashr(ShAmt);
3267  }
3268
3269  // Calculate the multiplicative inverse, using Newton's method.
3270  APInt t, xn = d;
3271  while ((t = d*xn) != 1)
3272    xn *= APInt(d.getBitWidth(), 2) - t;
3273
3274  Op2 = DAG.getConstant(xn, Op1.getValueType());
3275  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3276}
3277
3278/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3279/// return a DAG expression to select that will generate the same value by
3280/// multiplying by a magic number.  See:
3281/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3282SDValue TargetLowering::
3283BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3284          std::vector<SDNode*>* Created) const {
3285  EVT VT = N->getValueType(0);
3286  DebugLoc dl= N->getDebugLoc();
3287
3288  // Check to see if we can do this.
3289  // FIXME: We should be more aggressive here.
3290  if (!isTypeLegal(VT))
3291    return SDValue();
3292
3293  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3294  APInt::ms magics = d.magic();
3295
3296  // Multiply the numerator (operand 0) by the magic value
3297  // FIXME: We should support doing a MUL in a wider type
3298  SDValue Q;
3299  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3300                            isOperationLegalOrCustom(ISD::MULHS, VT))
3301    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3302                    DAG.getConstant(magics.m, VT));
3303  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3304                                 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3305    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3306                              N->getOperand(0),
3307                              DAG.getConstant(magics.m, VT)).getNode(), 1);
3308  else
3309    return SDValue();       // No mulhs or equvialent
3310  // If d > 0 and m < 0, add the numerator
3311  if (d.isStrictlyPositive() && magics.m.isNegative()) {
3312    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3313    if (Created)
3314      Created->push_back(Q.getNode());
3315  }
3316  // If d < 0 and m > 0, subtract the numerator.
3317  if (d.isNegative() && magics.m.isStrictlyPositive()) {
3318    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3319    if (Created)
3320      Created->push_back(Q.getNode());
3321  }
3322  // Shift right algebraic if shift value is nonzero
3323  if (magics.s > 0) {
3324    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3325                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3326    if (Created)
3327      Created->push_back(Q.getNode());
3328  }
3329  // Extract the sign bit and add it to the quotient
3330  SDValue T =
3331    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3332                                           getShiftAmountTy(Q.getValueType())));
3333  if (Created)
3334    Created->push_back(T.getNode());
3335  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3336}
3337
3338/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3339/// return a DAG expression to select that will generate the same value by
3340/// multiplying by a magic number.  See:
3341/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3342SDValue TargetLowering::
3343BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3344          std::vector<SDNode*>* Created) const {
3345  EVT VT = N->getValueType(0);
3346  DebugLoc dl = N->getDebugLoc();
3347
3348  // Check to see if we can do this.
3349  // FIXME: We should be more aggressive here.
3350  if (!isTypeLegal(VT))
3351    return SDValue();
3352
3353  // FIXME: We should use a narrower constant when the upper
3354  // bits are known to be zero.
3355  const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3356  APInt::mu magics = N1C.magicu();
3357
3358  SDValue Q = N->getOperand(0);
3359
3360  // If the divisor is even, we can avoid using the expensive fixup by shifting
3361  // the divided value upfront.
3362  if (magics.a != 0 && !N1C[0]) {
3363    unsigned Shift = N1C.countTrailingZeros();
3364    Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3365                    DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3366    if (Created)
3367      Created->push_back(Q.getNode());
3368
3369    // Get magic number for the shifted divisor.
3370    magics = N1C.lshr(Shift).magicu(Shift);
3371    assert(magics.a == 0 && "Should use cheap fixup now");
3372  }
3373
3374  // Multiply the numerator (operand 0) by the magic value
3375  // FIXME: We should support doing a MUL in a wider type
3376  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3377                            isOperationLegalOrCustom(ISD::MULHU, VT))
3378    Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3379  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3380                                 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3381    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3382                            DAG.getConstant(magics.m, VT)).getNode(), 1);
3383  else
3384    return SDValue();       // No mulhu or equvialent
3385  if (Created)
3386    Created->push_back(Q.getNode());
3387
3388  if (magics.a == 0) {
3389    assert(magics.s < N1C.getBitWidth() &&
3390           "We shouldn't generate an undefined shift!");
3391    return DAG.getNode(ISD::SRL, dl, VT, Q,
3392                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3393  } else {
3394    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3395    if (Created)
3396      Created->push_back(NPQ.getNode());
3397    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3398                      DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3399    if (Created)
3400      Created->push_back(NPQ.getNode());
3401    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3402    if (Created)
3403      Created->push_back(NPQ.getNode());
3404    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3405             DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
3406  }
3407}
3408