TargetLowering.cpp revision 92abc62399881ba9c525be80362c134ad836e2d9
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I16] = "__ashli16"; 33 Names[RTLIB::SHL_I32] = "__ashlsi3"; 34 Names[RTLIB::SHL_I64] = "__ashldi3"; 35 Names[RTLIB::SHL_I128] = "__ashlti3"; 36 Names[RTLIB::SRL_I16] = "__lshri16"; 37 Names[RTLIB::SRL_I32] = "__lshrsi3"; 38 Names[RTLIB::SRL_I64] = "__lshrdi3"; 39 Names[RTLIB::SRL_I128] = "__lshrti3"; 40 Names[RTLIB::SRA_I16] = "__ashri16"; 41 Names[RTLIB::SRA_I32] = "__ashrsi3"; 42 Names[RTLIB::SRA_I64] = "__ashrdi3"; 43 Names[RTLIB::SRA_I128] = "__ashrti3"; 44 Names[RTLIB::MUL_I16] = "__muli16"; 45 Names[RTLIB::MUL_I32] = "__mulsi3"; 46 Names[RTLIB::MUL_I64] = "__muldi3"; 47 Names[RTLIB::MUL_I128] = "__multi3"; 48 Names[RTLIB::SDIV_I32] = "__divsi3"; 49 Names[RTLIB::SDIV_I64] = "__divdi3"; 50 Names[RTLIB::SDIV_I128] = "__divti3"; 51 Names[RTLIB::UDIV_I32] = "__udivsi3"; 52 Names[RTLIB::UDIV_I64] = "__udivdi3"; 53 Names[RTLIB::UDIV_I128] = "__udivti3"; 54 Names[RTLIB::SREM_I32] = "__modsi3"; 55 Names[RTLIB::SREM_I64] = "__moddi3"; 56 Names[RTLIB::SREM_I128] = "__modti3"; 57 Names[RTLIB::UREM_I32] = "__umodsi3"; 58 Names[RTLIB::UREM_I64] = "__umoddi3"; 59 Names[RTLIB::UREM_I128] = "__umodti3"; 60 Names[RTLIB::NEG_I32] = "__negsi2"; 61 Names[RTLIB::NEG_I64] = "__negdi2"; 62 Names[RTLIB::ADD_F32] = "__addsf3"; 63 Names[RTLIB::ADD_F64] = "__adddf3"; 64 Names[RTLIB::ADD_F80] = "__addxf3"; 65 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 66 Names[RTLIB::SUB_F32] = "__subsf3"; 67 Names[RTLIB::SUB_F64] = "__subdf3"; 68 Names[RTLIB::SUB_F80] = "__subxf3"; 69 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 70 Names[RTLIB::MUL_F32] = "__mulsf3"; 71 Names[RTLIB::MUL_F64] = "__muldf3"; 72 Names[RTLIB::MUL_F80] = "__mulxf3"; 73 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 74 Names[RTLIB::DIV_F32] = "__divsf3"; 75 Names[RTLIB::DIV_F64] = "__divdf3"; 76 Names[RTLIB::DIV_F80] = "__divxf3"; 77 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 78 Names[RTLIB::REM_F32] = "fmodf"; 79 Names[RTLIB::REM_F64] = "fmod"; 80 Names[RTLIB::REM_F80] = "fmodl"; 81 Names[RTLIB::REM_PPCF128] = "fmodl"; 82 Names[RTLIB::POWI_F32] = "__powisf2"; 83 Names[RTLIB::POWI_F64] = "__powidf2"; 84 Names[RTLIB::POWI_F80] = "__powixf2"; 85 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 86 Names[RTLIB::SQRT_F32] = "sqrtf"; 87 Names[RTLIB::SQRT_F64] = "sqrt"; 88 Names[RTLIB::SQRT_F80] = "sqrtl"; 89 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 90 Names[RTLIB::LOG_F32] = "logf"; 91 Names[RTLIB::LOG_F64] = "log"; 92 Names[RTLIB::LOG_F80] = "logl"; 93 Names[RTLIB::LOG_PPCF128] = "logl"; 94 Names[RTLIB::LOG2_F32] = "log2f"; 95 Names[RTLIB::LOG2_F64] = "log2"; 96 Names[RTLIB::LOG2_F80] = "log2l"; 97 Names[RTLIB::LOG2_PPCF128] = "log2l"; 98 Names[RTLIB::LOG10_F32] = "log10f"; 99 Names[RTLIB::LOG10_F64] = "log10"; 100 Names[RTLIB::LOG10_F80] = "log10l"; 101 Names[RTLIB::LOG10_PPCF128] = "log10l"; 102 Names[RTLIB::EXP_F32] = "expf"; 103 Names[RTLIB::EXP_F64] = "exp"; 104 Names[RTLIB::EXP_F80] = "expl"; 105 Names[RTLIB::EXP_PPCF128] = "expl"; 106 Names[RTLIB::EXP2_F32] = "exp2f"; 107 Names[RTLIB::EXP2_F64] = "exp2"; 108 Names[RTLIB::EXP2_F80] = "exp2l"; 109 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 110 Names[RTLIB::SIN_F32] = "sinf"; 111 Names[RTLIB::SIN_F64] = "sin"; 112 Names[RTLIB::SIN_F80] = "sinl"; 113 Names[RTLIB::SIN_PPCF128] = "sinl"; 114 Names[RTLIB::COS_F32] = "cosf"; 115 Names[RTLIB::COS_F64] = "cos"; 116 Names[RTLIB::COS_F80] = "cosl"; 117 Names[RTLIB::COS_PPCF128] = "cosl"; 118 Names[RTLIB::POW_F32] = "powf"; 119 Names[RTLIB::POW_F64] = "pow"; 120 Names[RTLIB::POW_F80] = "powl"; 121 Names[RTLIB::POW_PPCF128] = "powl"; 122 Names[RTLIB::CEIL_F32] = "ceilf"; 123 Names[RTLIB::CEIL_F64] = "ceil"; 124 Names[RTLIB::CEIL_F80] = "ceill"; 125 Names[RTLIB::CEIL_PPCF128] = "ceill"; 126 Names[RTLIB::TRUNC_F32] = "truncf"; 127 Names[RTLIB::TRUNC_F64] = "trunc"; 128 Names[RTLIB::TRUNC_F80] = "truncl"; 129 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 130 Names[RTLIB::RINT_F32] = "rintf"; 131 Names[RTLIB::RINT_F64] = "rint"; 132 Names[RTLIB::RINT_F80] = "rintl"; 133 Names[RTLIB::RINT_PPCF128] = "rintl"; 134 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 135 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 136 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 137 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 138 Names[RTLIB::FLOOR_F32] = "floorf"; 139 Names[RTLIB::FLOOR_F64] = "floor"; 140 Names[RTLIB::FLOOR_F80] = "floorl"; 141 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 142 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 143 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 144 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 145 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 146 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 147 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 148 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 149 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 150 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 151 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 152 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 153 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 154 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 155 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 156 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 157 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 158 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 159 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 160 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 161 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 162 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 163 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 164 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 165 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 166 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 167 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 168 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 169 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 170 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 171 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 172 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 173 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 174 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 175 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 176 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 177 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 178 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 179 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 180 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 181 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 182 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 183 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 184 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 185 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 186 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 187 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 188 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 189 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 190 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 191 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 192 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 193 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 194 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 195 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 196 Names[RTLIB::OEQ_F32] = "__eqsf2"; 197 Names[RTLIB::OEQ_F64] = "__eqdf2"; 198 Names[RTLIB::UNE_F32] = "__nesf2"; 199 Names[RTLIB::UNE_F64] = "__nedf2"; 200 Names[RTLIB::OGE_F32] = "__gesf2"; 201 Names[RTLIB::OGE_F64] = "__gedf2"; 202 Names[RTLIB::OLT_F32] = "__ltsf2"; 203 Names[RTLIB::OLT_F64] = "__ltdf2"; 204 Names[RTLIB::OLE_F32] = "__lesf2"; 205 Names[RTLIB::OLE_F64] = "__ledf2"; 206 Names[RTLIB::OGT_F32] = "__gtsf2"; 207 Names[RTLIB::OGT_F64] = "__gtdf2"; 208 Names[RTLIB::UO_F32] = "__unordsf2"; 209 Names[RTLIB::UO_F64] = "__unorddf2"; 210 Names[RTLIB::O_F32] = "__unordsf2"; 211 Names[RTLIB::O_F64] = "__unorddf2"; 212} 213 214/// getFPEXT - Return the FPEXT_*_* value for the given types, or 215/// UNKNOWN_LIBCALL if there is none. 216RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 217 if (OpVT == MVT::f32) { 218 if (RetVT == MVT::f64) 219 return FPEXT_F32_F64; 220 } 221 return UNKNOWN_LIBCALL; 222} 223 224/// getFPROUND - Return the FPROUND_*_* value for the given types, or 225/// UNKNOWN_LIBCALL if there is none. 226RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 227 if (RetVT == MVT::f32) { 228 if (OpVT == MVT::f64) 229 return FPROUND_F64_F32; 230 if (OpVT == MVT::f80) 231 return FPROUND_F80_F32; 232 if (OpVT == MVT::ppcf128) 233 return FPROUND_PPCF128_F32; 234 } else if (RetVT == MVT::f64) { 235 if (OpVT == MVT::f80) 236 return FPROUND_F80_F64; 237 if (OpVT == MVT::ppcf128) 238 return FPROUND_PPCF128_F64; 239 } 240 return UNKNOWN_LIBCALL; 241} 242 243/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 244/// UNKNOWN_LIBCALL if there is none. 245RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 246 if (OpVT == MVT::f32) { 247 if (RetVT == MVT::i32) 248 return FPTOSINT_F32_I32; 249 if (RetVT == MVT::i64) 250 return FPTOSINT_F32_I64; 251 if (RetVT == MVT::i128) 252 return FPTOSINT_F32_I128; 253 } else if (OpVT == MVT::f64) { 254 if (RetVT == MVT::i32) 255 return FPTOSINT_F64_I32; 256 if (RetVT == MVT::i64) 257 return FPTOSINT_F64_I64; 258 if (RetVT == MVT::i128) 259 return FPTOSINT_F64_I128; 260 } else if (OpVT == MVT::f80) { 261 if (RetVT == MVT::i32) 262 return FPTOSINT_F80_I32; 263 if (RetVT == MVT::i64) 264 return FPTOSINT_F80_I64; 265 if (RetVT == MVT::i128) 266 return FPTOSINT_F80_I128; 267 } else if (OpVT == MVT::ppcf128) { 268 if (RetVT == MVT::i32) 269 return FPTOSINT_PPCF128_I32; 270 if (RetVT == MVT::i64) 271 return FPTOSINT_PPCF128_I64; 272 if (RetVT == MVT::i128) 273 return FPTOSINT_PPCF128_I128; 274 } 275 return UNKNOWN_LIBCALL; 276} 277 278/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 279/// UNKNOWN_LIBCALL if there is none. 280RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 281 if (OpVT == MVT::f32) { 282 if (RetVT == MVT::i32) 283 return FPTOUINT_F32_I32; 284 if (RetVT == MVT::i64) 285 return FPTOUINT_F32_I64; 286 if (RetVT == MVT::i128) 287 return FPTOUINT_F32_I128; 288 } else if (OpVT == MVT::f64) { 289 if (RetVT == MVT::i32) 290 return FPTOUINT_F64_I32; 291 if (RetVT == MVT::i64) 292 return FPTOUINT_F64_I64; 293 if (RetVT == MVT::i128) 294 return FPTOUINT_F64_I128; 295 } else if (OpVT == MVT::f80) { 296 if (RetVT == MVT::i32) 297 return FPTOUINT_F80_I32; 298 if (RetVT == MVT::i64) 299 return FPTOUINT_F80_I64; 300 if (RetVT == MVT::i128) 301 return FPTOUINT_F80_I128; 302 } else if (OpVT == MVT::ppcf128) { 303 if (RetVT == MVT::i32) 304 return FPTOUINT_PPCF128_I32; 305 if (RetVT == MVT::i64) 306 return FPTOUINT_PPCF128_I64; 307 if (RetVT == MVT::i128) 308 return FPTOUINT_PPCF128_I128; 309 } 310 return UNKNOWN_LIBCALL; 311} 312 313/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 314/// UNKNOWN_LIBCALL if there is none. 315RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 316 if (OpVT == MVT::i32) { 317 if (RetVT == MVT::f32) 318 return SINTTOFP_I32_F32; 319 else if (RetVT == MVT::f64) 320 return SINTTOFP_I32_F64; 321 else if (RetVT == MVT::f80) 322 return SINTTOFP_I32_F80; 323 else if (RetVT == MVT::ppcf128) 324 return SINTTOFP_I32_PPCF128; 325 } else if (OpVT == MVT::i64) { 326 if (RetVT == MVT::f32) 327 return SINTTOFP_I64_F32; 328 else if (RetVT == MVT::f64) 329 return SINTTOFP_I64_F64; 330 else if (RetVT == MVT::f80) 331 return SINTTOFP_I64_F80; 332 else if (RetVT == MVT::ppcf128) 333 return SINTTOFP_I64_PPCF128; 334 } else if (OpVT == MVT::i128) { 335 if (RetVT == MVT::f32) 336 return SINTTOFP_I128_F32; 337 else if (RetVT == MVT::f64) 338 return SINTTOFP_I128_F64; 339 else if (RetVT == MVT::f80) 340 return SINTTOFP_I128_F80; 341 else if (RetVT == MVT::ppcf128) 342 return SINTTOFP_I128_PPCF128; 343 } 344 return UNKNOWN_LIBCALL; 345} 346 347/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 348/// UNKNOWN_LIBCALL if there is none. 349RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 350 if (OpVT == MVT::i32) { 351 if (RetVT == MVT::f32) 352 return UINTTOFP_I32_F32; 353 else if (RetVT == MVT::f64) 354 return UINTTOFP_I32_F64; 355 else if (RetVT == MVT::f80) 356 return UINTTOFP_I32_F80; 357 else if (RetVT == MVT::ppcf128) 358 return UINTTOFP_I32_PPCF128; 359 } else if (OpVT == MVT::i64) { 360 if (RetVT == MVT::f32) 361 return UINTTOFP_I64_F32; 362 else if (RetVT == MVT::f64) 363 return UINTTOFP_I64_F64; 364 else if (RetVT == MVT::f80) 365 return UINTTOFP_I64_F80; 366 else if (RetVT == MVT::ppcf128) 367 return UINTTOFP_I64_PPCF128; 368 } else if (OpVT == MVT::i128) { 369 if (RetVT == MVT::f32) 370 return UINTTOFP_I128_F32; 371 else if (RetVT == MVT::f64) 372 return UINTTOFP_I128_F64; 373 else if (RetVT == MVT::f80) 374 return UINTTOFP_I128_F80; 375 else if (RetVT == MVT::ppcf128) 376 return UINTTOFP_I128_PPCF128; 377 } 378 return UNKNOWN_LIBCALL; 379} 380 381/// InitCmpLibcallCCs - Set default comparison libcall CC. 382/// 383static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 384 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 385 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 386 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 387 CCs[RTLIB::UNE_F32] = ISD::SETNE; 388 CCs[RTLIB::UNE_F64] = ISD::SETNE; 389 CCs[RTLIB::OGE_F32] = ISD::SETGE; 390 CCs[RTLIB::OGE_F64] = ISD::SETGE; 391 CCs[RTLIB::OLT_F32] = ISD::SETLT; 392 CCs[RTLIB::OLT_F64] = ISD::SETLT; 393 CCs[RTLIB::OLE_F32] = ISD::SETLE; 394 CCs[RTLIB::OLE_F64] = ISD::SETLE; 395 CCs[RTLIB::OGT_F32] = ISD::SETGT; 396 CCs[RTLIB::OGT_F64] = ISD::SETGT; 397 CCs[RTLIB::UO_F32] = ISD::SETNE; 398 CCs[RTLIB::UO_F64] = ISD::SETNE; 399 CCs[RTLIB::O_F32] = ISD::SETEQ; 400 CCs[RTLIB::O_F64] = ISD::SETEQ; 401} 402 403TargetLowering::TargetLowering(TargetMachine &tm) 404 : TM(tm), TD(TM.getTargetData()) { 405 // All operations default to being supported. 406 memset(OpActions, 0, sizeof(OpActions)); 407 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 408 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 409 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 410 memset(ConvertActions, 0, sizeof(ConvertActions)); 411 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 412 413 // Set default actions for various operations. 414 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 415 // Default all indexed load / store to expand. 416 for (unsigned IM = (unsigned)ISD::PRE_INC; 417 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 418 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 419 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 420 } 421 422 // These operations default to expand. 423 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 424 } 425 426 // Most targets ignore the @llvm.prefetch intrinsic. 427 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 428 429 // ConstantFP nodes default to expand. Targets can either change this to 430 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 431 // to optimize expansions for certain constants. 432 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 433 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 434 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 435 436 // These library functions default to expand. 437 setOperationAction(ISD::FLOG , MVT::f64, Expand); 438 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 439 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 440 setOperationAction(ISD::FEXP , MVT::f64, Expand); 441 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 442 setOperationAction(ISD::FLOG , MVT::f32, Expand); 443 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 444 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 445 setOperationAction(ISD::FEXP , MVT::f32, Expand); 446 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 447 448 // Default ISD::TRAP to expand (which turns it into abort). 449 setOperationAction(ISD::TRAP, MVT::Other, Expand); 450 451 IsLittleEndian = TD->isLittleEndian(); 452 UsesGlobalOffsetTable = false; 453 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 454 ShiftAmtHandling = Undefined; 455 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 456 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 457 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 458 allowUnalignedMemoryAccesses = false; 459 UseUnderscoreSetJmp = false; 460 UseUnderscoreLongJmp = false; 461 SelectIsExpensive = false; 462 IntDivIsCheap = false; 463 Pow2DivIsCheap = false; 464 StackPointerRegisterToSaveRestore = 0; 465 ExceptionPointerRegister = 0; 466 ExceptionSelectorRegister = 0; 467 BooleanContents = UndefinedBooleanContent; 468 SchedPreferenceInfo = SchedulingForLatency; 469 JumpBufSize = 0; 470 JumpBufAlignment = 0; 471 IfCvtBlockSizeLimit = 2; 472 IfCvtDupBlockSizeLimit = 0; 473 PrefLoopAlignment = 0; 474 475 InitLibcallNames(LibcallRoutineNames); 476 InitCmpLibcallCCs(CmpLibcallCCs); 477 478 // Tell Legalize whether the assembler supports DEBUG_LOC. 479 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 480 if (!TASM || !TASM->hasDotLocAndDotFile()) 481 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 482} 483 484TargetLowering::~TargetLowering() {} 485 486/// computeRegisterProperties - Once all of the register classes are added, 487/// this allows us to compute derived properties we expose. 488void TargetLowering::computeRegisterProperties() { 489 assert(MVT::LAST_VALUETYPE <= 32 && 490 "Too many value types for ValueTypeActions to hold!"); 491 492 // Everything defaults to needing one register. 493 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 494 NumRegistersForVT[i] = 1; 495 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 496 } 497 // ...except isVoid, which doesn't need any registers. 498 NumRegistersForVT[MVT::isVoid] = 0; 499 500 // Find the largest integer register class. 501 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 502 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 503 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 504 505 // Every integer value type larger than this largest register takes twice as 506 // many registers to represent as the previous ValueType. 507 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 508 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 509 if (!EVT.isInteger()) 510 break; 511 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 512 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 513 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 514 ValueTypeActions.setTypeAction(EVT, Expand); 515 } 516 517 // Inspect all of the ValueType's smaller than the largest integer 518 // register to see which ones need promotion. 519 unsigned LegalIntReg = LargestIntReg; 520 for (unsigned IntReg = LargestIntReg - 1; 521 IntReg >= (unsigned)MVT::i1; --IntReg) { 522 MVT IVT = (MVT::SimpleValueType)IntReg; 523 if (isTypeLegal(IVT)) { 524 LegalIntReg = IntReg; 525 } else { 526 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 527 (MVT::SimpleValueType)LegalIntReg; 528 ValueTypeActions.setTypeAction(IVT, Promote); 529 } 530 } 531 532 // ppcf128 type is really two f64's. 533 if (!isTypeLegal(MVT::ppcf128)) { 534 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 535 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 536 TransformToType[MVT::ppcf128] = MVT::f64; 537 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 538 } 539 540 // Decide how to handle f64. If the target does not have native f64 support, 541 // expand it to i64 and we will be generating soft float library calls. 542 if (!isTypeLegal(MVT::f64)) { 543 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 544 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 545 TransformToType[MVT::f64] = MVT::i64; 546 ValueTypeActions.setTypeAction(MVT::f64, Expand); 547 } 548 549 // Decide how to handle f32. If the target does not have native support for 550 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 551 if (!isTypeLegal(MVT::f32)) { 552 if (isTypeLegal(MVT::f64)) { 553 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 554 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 555 TransformToType[MVT::f32] = MVT::f64; 556 ValueTypeActions.setTypeAction(MVT::f32, Promote); 557 } else { 558 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 559 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 560 TransformToType[MVT::f32] = MVT::i32; 561 ValueTypeActions.setTypeAction(MVT::f32, Expand); 562 } 563 } 564 565 // Loop over all of the vector value types to see which need transformations. 566 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 567 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 568 MVT VT = (MVT::SimpleValueType)i; 569 if (!isTypeLegal(VT)) { 570 MVT IntermediateVT, RegisterVT; 571 unsigned NumIntermediates; 572 NumRegistersForVT[i] = 573 getVectorTypeBreakdown(VT, 574 IntermediateVT, NumIntermediates, 575 RegisterVT); 576 RegisterTypeForVT[i] = RegisterVT; 577 578 // Determine if there is a legal wider type. 579 bool IsLegalWiderType = false; 580 MVT EltVT = VT.getVectorElementType(); 581 unsigned NElts = VT.getVectorNumElements(); 582 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 583 MVT SVT = (MVT::SimpleValueType)nVT; 584 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 585 SVT.getVectorNumElements() > NElts) { 586 TransformToType[i] = SVT; 587 ValueTypeActions.setTypeAction(VT, Promote); 588 IsLegalWiderType = true; 589 break; 590 } 591 } 592 if (!IsLegalWiderType) { 593 MVT NVT = VT.getPow2VectorType(); 594 if (NVT == VT) { 595 // Type is already a power of 2. The default action is to split. 596 TransformToType[i] = MVT::Other; 597 ValueTypeActions.setTypeAction(VT, Expand); 598 } else { 599 TransformToType[i] = NVT; 600 ValueTypeActions.setTypeAction(VT, Promote); 601 } 602 } 603 } 604 } 605} 606 607const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 608 return NULL; 609} 610 611 612MVT TargetLowering::getSetCCResultType(MVT VT) const { 613 return getValueType(TD->getIntPtrType()); 614} 615 616 617/// getVectorTypeBreakdown - Vector types are broken down into some number of 618/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 619/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 620/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 621/// 622/// This method returns the number of registers needed, and the VT for each 623/// register. It also returns the VT and quantity of the intermediate values 624/// before they are promoted/expanded. 625/// 626unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 627 MVT &IntermediateVT, 628 unsigned &NumIntermediates, 629 MVT &RegisterVT) const { 630 // Figure out the right, legal destination reg to copy into. 631 unsigned NumElts = VT.getVectorNumElements(); 632 MVT EltTy = VT.getVectorElementType(); 633 634 unsigned NumVectorRegs = 1; 635 636 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 637 // could break down into LHS/RHS like LegalizeDAG does. 638 if (!isPowerOf2_32(NumElts)) { 639 NumVectorRegs = NumElts; 640 NumElts = 1; 641 } 642 643 // Divide the input until we get to a supported size. This will always 644 // end with a scalar if the target doesn't support vectors. 645 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 646 NumElts >>= 1; 647 NumVectorRegs <<= 1; 648 } 649 650 NumIntermediates = NumVectorRegs; 651 652 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 653 if (!isTypeLegal(NewVT)) 654 NewVT = EltTy; 655 IntermediateVT = NewVT; 656 657 MVT DestVT = getTypeToTransformTo(NewVT); 658 RegisterVT = DestVT; 659 if (DestVT.bitsLT(NewVT)) { 660 // Value is expanded, e.g. i64 -> i16. 661 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 662 } else { 663 // Otherwise, promotion or legal types use the same number of registers as 664 // the vector decimated to the appropriate level. 665 return NumVectorRegs; 666 } 667 668 return 1; 669} 670 671/// getWidenVectorType: given a vector type, returns the type to widen to 672/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 673/// If there is no vector type that we want to widen to, returns MVT::Other 674/// When and where to widen is target dependent based on the cost of 675/// scalarizing vs using the wider vector type. 676MVT TargetLowering::getWidenVectorType(MVT VT) const { 677 assert(VT.isVector()); 678 if (isTypeLegal(VT)) 679 return VT; 680 681 // Default is not to widen until moved to LegalizeTypes 682 return MVT::Other; 683} 684 685/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 686/// function arguments in the caller parameter area. This is the actual 687/// alignment, not its logarithm. 688unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 689 return TD->getCallFrameTypeAlignment(Ty); 690} 691 692SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 693 SelectionDAG &DAG) const { 694 if (usesGlobalOffsetTable()) 695 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 696 return Table; 697} 698 699bool 700TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 701 // Assume that everything is safe in static mode. 702 if (getTargetMachine().getRelocationModel() == Reloc::Static) 703 return true; 704 705 // In dynamic-no-pic mode, assume that known defined values are safe. 706 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 707 GA && 708 !GA->getGlobal()->isDeclaration() && 709 !GA->getGlobal()->mayBeOverridden()) 710 return true; 711 712 // Otherwise assume nothing is safe. 713 return false; 714} 715 716//===----------------------------------------------------------------------===// 717// Optimization Methods 718//===----------------------------------------------------------------------===// 719 720/// ShrinkDemandedConstant - Check to see if the specified operand of the 721/// specified instruction is a constant integer. If so, check to see if there 722/// are any bits set in the constant that are not demanded. If so, shrink the 723/// constant and return true. 724bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 725 const APInt &Demanded) { 726 // FIXME: ISD::SELECT, ISD::SELECT_CC 727 switch (Op.getOpcode()) { 728 default: break; 729 case ISD::AND: 730 case ISD::OR: 731 case ISD::XOR: 732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 733 if (C->getAPIntValue().intersects(~Demanded)) { 734 MVT VT = Op.getValueType(); 735 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 736 DAG.getConstant(Demanded & 737 C->getAPIntValue(), 738 VT)); 739 return CombineTo(Op, New); 740 } 741 break; 742 } 743 return false; 744} 745 746/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 747/// DemandedMask bits of the result of Op are ever used downstream. If we can 748/// use this information to simplify Op, create a new simplified DAG node and 749/// return true, returning the original and new nodes in Old and New. Otherwise, 750/// analyze the expression and return a mask of KnownOne and KnownZero bits for 751/// the expression (used to simplify the caller). The KnownZero/One bits may 752/// only be accurate for those bits in the DemandedMask. 753bool TargetLowering::SimplifyDemandedBits(SDValue Op, 754 const APInt &DemandedMask, 755 APInt &KnownZero, 756 APInt &KnownOne, 757 TargetLoweringOpt &TLO, 758 unsigned Depth) const { 759 unsigned BitWidth = DemandedMask.getBitWidth(); 760 assert(Op.getValueSizeInBits() == BitWidth && 761 "Mask size mismatches value type size!"); 762 APInt NewMask = DemandedMask; 763 764 // Don't know anything. 765 KnownZero = KnownOne = APInt(BitWidth, 0); 766 767 // Other users may use these bits. 768 if (!Op.getNode()->hasOneUse()) { 769 if (Depth != 0) { 770 // If not at the root, Just compute the KnownZero/KnownOne bits to 771 // simplify things downstream. 772 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 773 return false; 774 } 775 // If this is the root being simplified, allow it to have multiple uses, 776 // just set the NewMask to all bits. 777 NewMask = APInt::getAllOnesValue(BitWidth); 778 } else if (DemandedMask == 0) { 779 // Not demanding any bits from Op. 780 if (Op.getOpcode() != ISD::UNDEF) 781 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 782 return false; 783 } else if (Depth == 6) { // Limit search depth. 784 return false; 785 } 786 787 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 788 switch (Op.getOpcode()) { 789 case ISD::Constant: 790 // We know all of the bits for a constant! 791 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 792 KnownZero = ~KnownOne & NewMask; 793 return false; // Don't fall through, will infinitely loop. 794 case ISD::AND: 795 // If the RHS is a constant, check to see if the LHS would be zero without 796 // using the bits from the RHS. Below, we use knowledge about the RHS to 797 // simplify the LHS, here we're using information from the LHS to simplify 798 // the RHS. 799 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 800 APInt LHSZero, LHSOne; 801 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 802 LHSZero, LHSOne, Depth+1); 803 // If the LHS already has zeros where RHSC does, this and is dead. 804 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 805 return TLO.CombineTo(Op, Op.getOperand(0)); 806 // If any of the set bits in the RHS are known zero on the LHS, shrink 807 // the constant. 808 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 809 return true; 810 } 811 812 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 813 KnownOne, TLO, Depth+1)) 814 return true; 815 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 816 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 817 KnownZero2, KnownOne2, TLO, Depth+1)) 818 return true; 819 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 820 821 // If all of the demanded bits are known one on one side, return the other. 822 // These bits cannot contribute to the result of the 'and'. 823 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 824 return TLO.CombineTo(Op, Op.getOperand(0)); 825 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 826 return TLO.CombineTo(Op, Op.getOperand(1)); 827 // If all of the demanded bits in the inputs are known zeros, return zero. 828 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 829 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 830 // If the RHS is a constant, see if we can simplify it. 831 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 832 return true; 833 834 // Output known-1 bits are only known if set in both the LHS & RHS. 835 KnownOne &= KnownOne2; 836 // Output known-0 are known to be clear if zero in either the LHS | RHS. 837 KnownZero |= KnownZero2; 838 break; 839 case ISD::OR: 840 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 841 KnownOne, TLO, Depth+1)) 842 return true; 843 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 844 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 845 KnownZero2, KnownOne2, TLO, Depth+1)) 846 return true; 847 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 848 849 // If all of the demanded bits are known zero on one side, return the other. 850 // These bits cannot contribute to the result of the 'or'. 851 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 852 return TLO.CombineTo(Op, Op.getOperand(0)); 853 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 854 return TLO.CombineTo(Op, Op.getOperand(1)); 855 // If all of the potentially set bits on one side are known to be set on 856 // the other side, just use the 'other' side. 857 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 858 return TLO.CombineTo(Op, Op.getOperand(0)); 859 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 860 return TLO.CombineTo(Op, Op.getOperand(1)); 861 // If the RHS is a constant, see if we can simplify it. 862 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 863 return true; 864 865 // Output known-0 bits are only known if clear in both the LHS & RHS. 866 KnownZero &= KnownZero2; 867 // Output known-1 are known to be set if set in either the LHS | RHS. 868 KnownOne |= KnownOne2; 869 break; 870 case ISD::XOR: 871 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 872 KnownOne, TLO, Depth+1)) 873 return true; 874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 875 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 876 KnownOne2, TLO, Depth+1)) 877 return true; 878 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 879 880 // If all of the demanded bits are known zero on one side, return the other. 881 // These bits cannot contribute to the result of the 'xor'. 882 if ((KnownZero & NewMask) == NewMask) 883 return TLO.CombineTo(Op, Op.getOperand(0)); 884 if ((KnownZero2 & NewMask) == NewMask) 885 return TLO.CombineTo(Op, Op.getOperand(1)); 886 887 // If all of the unknown bits are known to be zero on one side or the other 888 // (but not both) turn this into an *inclusive* or. 889 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 890 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 891 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 892 Op.getOperand(0), 893 Op.getOperand(1))); 894 895 // Output known-0 bits are known if clear or set in both the LHS & RHS. 896 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 897 // Output known-1 are known to be set if set in only one of the LHS, RHS. 898 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 899 900 // If all of the demanded bits on one side are known, and all of the set 901 // bits on that side are also known to be set on the other side, turn this 902 // into an AND, as we know the bits will be cleared. 903 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 904 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 905 if ((KnownOne & KnownOne2) == KnownOne) { 906 MVT VT = Op.getValueType(); 907 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 908 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 909 ANDC)); 910 } 911 } 912 913 // If the RHS is a constant, see if we can simplify it. 914 // for XOR, we prefer to force bits to 1 if they will make a -1. 915 // if we can't force bits, try to shrink constant 916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 917 APInt Expanded = C->getAPIntValue() | (~NewMask); 918 // if we can expand it to have all bits set, do it 919 if (Expanded.isAllOnesValue()) { 920 if (Expanded != C->getAPIntValue()) { 921 MVT VT = Op.getValueType(); 922 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 923 TLO.DAG.getConstant(Expanded, VT)); 924 return TLO.CombineTo(Op, New); 925 } 926 // if it already has all the bits set, nothing to change 927 // but don't shrink either! 928 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 929 return true; 930 } 931 } 932 933 KnownZero = KnownZeroOut; 934 KnownOne = KnownOneOut; 935 break; 936 case ISD::SELECT: 937 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 938 KnownOne, TLO, Depth+1)) 939 return true; 940 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 941 KnownOne2, TLO, Depth+1)) 942 return true; 943 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 944 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 945 946 // If the operands are constants, see if we can simplify them. 947 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 948 return true; 949 950 // Only known if known in both the LHS and RHS. 951 KnownOne &= KnownOne2; 952 KnownZero &= KnownZero2; 953 break; 954 case ISD::SELECT_CC: 955 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 956 KnownOne, TLO, Depth+1)) 957 return true; 958 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 959 KnownOne2, TLO, Depth+1)) 960 return true; 961 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 962 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 963 964 // If the operands are constants, see if we can simplify them. 965 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 966 return true; 967 968 // Only known if known in both the LHS and RHS. 969 KnownOne &= KnownOne2; 970 KnownZero &= KnownZero2; 971 break; 972 case ISD::SHL: 973 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 974 unsigned ShAmt = SA->getZExtValue(); 975 SDValue InOp = Op.getOperand(0); 976 977 // If the shift count is an invalid immediate, don't do anything. 978 if (ShAmt >= BitWidth) 979 break; 980 981 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 982 // single shift. We can do this if the bottom bits (which are shifted 983 // out) are never demanded. 984 if (InOp.getOpcode() == ISD::SRL && 985 isa<ConstantSDNode>(InOp.getOperand(1))) { 986 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 987 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 988 unsigned Opc = ISD::SHL; 989 int Diff = ShAmt-C1; 990 if (Diff < 0) { 991 Diff = -Diff; 992 Opc = ISD::SRL; 993 } 994 995 SDValue NewSA = 996 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 997 MVT VT = Op.getValueType(); 998 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 999 InOp.getOperand(0), NewSA)); 1000 } 1001 } 1002 1003 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1004 KnownZero, KnownOne, TLO, Depth+1)) 1005 return true; 1006 KnownZero <<= SA->getZExtValue(); 1007 KnownOne <<= SA->getZExtValue(); 1008 // low bits known zero. 1009 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1010 } 1011 break; 1012 case ISD::SRL: 1013 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1014 MVT VT = Op.getValueType(); 1015 unsigned ShAmt = SA->getZExtValue(); 1016 unsigned VTSize = VT.getSizeInBits(); 1017 SDValue InOp = Op.getOperand(0); 1018 1019 // If the shift count is an invalid immediate, don't do anything. 1020 if (ShAmt >= BitWidth) 1021 break; 1022 1023 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1024 // single shift. We can do this if the top bits (which are shifted out) 1025 // are never demanded. 1026 if (InOp.getOpcode() == ISD::SHL && 1027 isa<ConstantSDNode>(InOp.getOperand(1))) { 1028 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1029 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1030 unsigned Opc = ISD::SRL; 1031 int Diff = ShAmt-C1; 1032 if (Diff < 0) { 1033 Diff = -Diff; 1034 Opc = ISD::SHL; 1035 } 1036 1037 SDValue NewSA = 1038 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1039 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 1040 InOp.getOperand(0), NewSA)); 1041 } 1042 } 1043 1044 // Compute the new bits that are at the top now. 1045 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1046 KnownZero, KnownOne, TLO, Depth+1)) 1047 return true; 1048 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1049 KnownZero = KnownZero.lshr(ShAmt); 1050 KnownOne = KnownOne.lshr(ShAmt); 1051 1052 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1053 KnownZero |= HighBits; // High bits known zero. 1054 } 1055 break; 1056 case ISD::SRA: 1057 // If this is an arithmetic shift right and only the low-bit is set, we can 1058 // always convert this into a logical shr, even if the shift amount is 1059 // variable. The low bit of the shift cannot be an input sign bit unless 1060 // the shift amount is >= the size of the datatype, which is undefined. 1061 if (DemandedMask == 1) 1062 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(), 1063 Op.getOperand(0), Op.getOperand(1))); 1064 1065 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1066 MVT VT = Op.getValueType(); 1067 unsigned ShAmt = SA->getZExtValue(); 1068 1069 // If the shift count is an invalid immediate, don't do anything. 1070 if (ShAmt >= BitWidth) 1071 break; 1072 1073 APInt InDemandedMask = (NewMask << ShAmt); 1074 1075 // If any of the demanded bits are produced by the sign extension, we also 1076 // demand the input sign bit. 1077 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1078 if (HighBits.intersects(NewMask)) 1079 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1080 1081 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1082 KnownZero, KnownOne, TLO, Depth+1)) 1083 return true; 1084 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1085 KnownZero = KnownZero.lshr(ShAmt); 1086 KnownOne = KnownOne.lshr(ShAmt); 1087 1088 // Handle the sign bit, adjusted to where it is now in the mask. 1089 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1090 1091 // If the input sign bit is known to be zero, or if none of the top bits 1092 // are demanded, turn this into an unsigned shift right. 1093 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1094 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 1095 Op.getOperand(1))); 1096 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1097 KnownOne |= HighBits; 1098 } 1099 } 1100 break; 1101 case ISD::SIGN_EXTEND_INREG: { 1102 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1103 1104 // Sign extension. Compute the demanded bits in the result that are not 1105 // present in the input. 1106 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1107 BitWidth - EVT.getSizeInBits()) & 1108 NewMask; 1109 1110 // If none of the extended bits are demanded, eliminate the sextinreg. 1111 if (NewBits == 0) 1112 return TLO.CombineTo(Op, Op.getOperand(0)); 1113 1114 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1115 InSignBit.zext(BitWidth); 1116 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1117 EVT.getSizeInBits()) & 1118 NewMask; 1119 1120 // Since the sign extended bits are demanded, we know that the sign 1121 // bit is demanded. 1122 InputDemandedBits |= InSignBit; 1123 1124 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1125 KnownZero, KnownOne, TLO, Depth+1)) 1126 return true; 1127 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1128 1129 // If the sign bit of the input is known set or clear, then we know the 1130 // top bits of the result. 1131 1132 // If the input sign bit is known zero, convert this into a zero extension. 1133 if (KnownZero.intersects(InSignBit)) 1134 return TLO.CombineTo(Op, 1135 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1136 1137 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1138 KnownOne |= NewBits; 1139 KnownZero &= ~NewBits; 1140 } else { // Input sign bit unknown 1141 KnownZero &= ~NewBits; 1142 KnownOne &= ~NewBits; 1143 } 1144 break; 1145 } 1146 case ISD::ZERO_EXTEND: { 1147 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1148 APInt InMask = NewMask; 1149 InMask.trunc(OperandBitWidth); 1150 1151 // If none of the top bits are demanded, convert this into an any_extend. 1152 APInt NewBits = 1153 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1154 if (!NewBits.intersects(NewMask)) 1155 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1156 Op.getValueType(), 1157 Op.getOperand(0))); 1158 1159 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1160 KnownZero, KnownOne, TLO, Depth+1)) 1161 return true; 1162 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1163 KnownZero.zext(BitWidth); 1164 KnownOne.zext(BitWidth); 1165 KnownZero |= NewBits; 1166 break; 1167 } 1168 case ISD::SIGN_EXTEND: { 1169 MVT InVT = Op.getOperand(0).getValueType(); 1170 unsigned InBits = InVT.getSizeInBits(); 1171 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1172 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1173 APInt NewBits = ~InMask & NewMask; 1174 1175 // If none of the top bits are demanded, convert this into an any_extend. 1176 if (NewBits == 0) 1177 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1178 Op.getOperand(0))); 1179 1180 // Since some of the sign extended bits are demanded, we know that the sign 1181 // bit is demanded. 1182 APInt InDemandedBits = InMask & NewMask; 1183 InDemandedBits |= InSignBit; 1184 InDemandedBits.trunc(InBits); 1185 1186 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1187 KnownOne, TLO, Depth+1)) 1188 return true; 1189 KnownZero.zext(BitWidth); 1190 KnownOne.zext(BitWidth); 1191 1192 // If the sign bit is known zero, convert this to a zero extend. 1193 if (KnownZero.intersects(InSignBit)) 1194 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1195 Op.getValueType(), 1196 Op.getOperand(0))); 1197 1198 // If the sign bit is known one, the top bits match. 1199 if (KnownOne.intersects(InSignBit)) { 1200 KnownOne |= NewBits; 1201 KnownZero &= ~NewBits; 1202 } else { // Otherwise, top bits aren't known. 1203 KnownOne &= ~NewBits; 1204 KnownZero &= ~NewBits; 1205 } 1206 break; 1207 } 1208 case ISD::ANY_EXTEND: { 1209 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1210 APInt InMask = NewMask; 1211 InMask.trunc(OperandBitWidth); 1212 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1213 KnownZero, KnownOne, TLO, Depth+1)) 1214 return true; 1215 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1216 KnownZero.zext(BitWidth); 1217 KnownOne.zext(BitWidth); 1218 break; 1219 } 1220 case ISD::TRUNCATE: { 1221 // Simplify the input, using demanded bit information, and compute the known 1222 // zero/one bits live out. 1223 APInt TruncMask = NewMask; 1224 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1225 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1226 KnownZero, KnownOne, TLO, Depth+1)) 1227 return true; 1228 KnownZero.trunc(BitWidth); 1229 KnownOne.trunc(BitWidth); 1230 1231 // If the input is only used by this truncate, see if we can shrink it based 1232 // on the known demanded bits. 1233 if (Op.getOperand(0).getNode()->hasOneUse()) { 1234 SDValue In = Op.getOperand(0); 1235 unsigned InBitWidth = In.getValueSizeInBits(); 1236 switch (In.getOpcode()) { 1237 default: break; 1238 case ISD::SRL: 1239 // Shrink SRL by a constant if none of the high bits shifted in are 1240 // demanded. 1241 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1242 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1243 InBitWidth - BitWidth); 1244 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1245 HighBits.trunc(BitWidth); 1246 1247 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1248 // None of the shifted in bits are needed. Add a truncate of the 1249 // shift input, then shift it. 1250 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1251 Op.getValueType(), 1252 In.getOperand(0)); 1253 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1254 NewTrunc, In.getOperand(1))); 1255 } 1256 } 1257 break; 1258 } 1259 } 1260 1261 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1262 break; 1263 } 1264 case ISD::AssertZext: { 1265 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1266 APInt InMask = APInt::getLowBitsSet(BitWidth, 1267 VT.getSizeInBits()); 1268 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1269 KnownZero, KnownOne, TLO, Depth+1)) 1270 return true; 1271 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1272 KnownZero |= ~InMask & NewMask; 1273 break; 1274 } 1275 case ISD::BIT_CONVERT: 1276#if 0 1277 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1278 // is demanded, turn this into a FGETSIGN. 1279 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1280 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1281 !MVT::isVector(Op.getOperand(0).getValueType())) { 1282 // Only do this xform if FGETSIGN is valid or if before legalize. 1283 if (!TLO.AfterLegalize || 1284 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1285 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1286 // place. We expect the SHL to be eliminated by other optimizations. 1287 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1288 Op.getOperand(0)); 1289 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1290 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1291 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1292 Sign, ShAmt)); 1293 } 1294 } 1295#endif 1296 break; 1297 default: 1298 // Just use ComputeMaskedBits to compute output bits. 1299 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1300 break; 1301 } 1302 1303 // If we know the value of all of the demanded bits, return this as a 1304 // constant. 1305 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1306 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1307 1308 return false; 1309} 1310 1311/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1312/// in Mask are known to be either zero or one and return them in the 1313/// KnownZero/KnownOne bitsets. 1314void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1315 const APInt &Mask, 1316 APInt &KnownZero, 1317 APInt &KnownOne, 1318 const SelectionDAG &DAG, 1319 unsigned Depth) const { 1320 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1321 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1322 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1323 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1324 "Should use MaskedValueIsZero if you don't know whether Op" 1325 " is a target node!"); 1326 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1327} 1328 1329/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1330/// targets that want to expose additional information about sign bits to the 1331/// DAG Combiner. 1332unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1333 unsigned Depth) const { 1334 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1335 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1336 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1337 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1338 "Should use ComputeNumSignBits if you don't know whether Op" 1339 " is a target node!"); 1340 return 1; 1341} 1342 1343static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1344 // Logical shift right or left won't ever introduce new set bits. 1345 // We check for this case because we don't care which bits are 1346 // set, but ComputeMaskedBits won't know anything unless it can 1347 // determine which specific bits may be set. 1348 if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL) 1349 return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG); 1350 1351 MVT OpVT = Val.getValueType(); 1352 unsigned BitWidth = OpVT.getSizeInBits(); 1353 APInt Mask = APInt::getAllOnesValue(BitWidth); 1354 APInt KnownZero, KnownOne; 1355 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1356 return KnownZero.countPopulation() == BitWidth - 1; 1357} 1358 1359/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1360/// and cc. If it is unable to simplify it, return a null SDValue. 1361SDValue 1362TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1363 ISD::CondCode Cond, bool foldBooleans, 1364 DAGCombinerInfo &DCI) const { 1365 SelectionDAG &DAG = DCI.DAG; 1366 1367 // These setcc operations always fold. 1368 switch (Cond) { 1369 default: break; 1370 case ISD::SETFALSE: 1371 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1372 case ISD::SETTRUE: 1373 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1374 } 1375 1376 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1377 const APInt &C1 = N1C->getAPIntValue(); 1378 if (isa<ConstantSDNode>(N0.getNode())) { 1379 return DAG.FoldSetCC(VT, N0, N1, Cond); 1380 } else { 1381 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1382 // equality comparison, then we're just comparing whether X itself is 1383 // zero. 1384 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1385 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1386 N0.getOperand(1).getOpcode() == ISD::Constant) { 1387 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1388 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1389 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1390 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1391 // (srl (ctlz x), 5) == 0 -> X != 0 1392 // (srl (ctlz x), 5) != 1 -> X != 0 1393 Cond = ISD::SETNE; 1394 } else { 1395 // (srl (ctlz x), 5) != 0 -> X == 0 1396 // (srl (ctlz x), 5) == 1 -> X == 0 1397 Cond = ISD::SETEQ; 1398 } 1399 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1400 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1401 Zero, Cond); 1402 } 1403 } 1404 1405 // If the LHS is '(and load, const)', the RHS is 0, 1406 // the test is for equality or unsigned, and all 1 bits of the const are 1407 // in the same partial word, see if we can shorten the load. 1408 if (DCI.isBeforeLegalize() && 1409 N0.getOpcode() == ISD::AND && C1 == 0 && 1410 isa<LoadSDNode>(N0.getOperand(0)) && 1411 N0.getOperand(0).getNode()->hasOneUse() && 1412 isa<ConstantSDNode>(N0.getOperand(1))) { 1413 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1414 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1415 uint64_t bestMask = 0; 1416 unsigned bestWidth = 0, bestOffset = 0; 1417 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1418 unsigned origWidth = N0.getValueType().getSizeInBits(); 1419 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1420 // 8 bits, but have to be careful... 1421 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1422 origWidth = Lod->getMemoryVT().getSizeInBits(); 1423 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1424 uint64_t newMask = (1ULL << width) - 1; 1425 for (unsigned offset=0; offset<origWidth/width; offset++) { 1426 if ((newMask & Mask)==Mask) { 1427 if (!TD->isLittleEndian()) 1428 bestOffset = (origWidth/width - offset - 1) * (width/8); 1429 else 1430 bestOffset = (uint64_t)offset * (width/8); 1431 bestMask = Mask >> (offset * (width/8) * 8); 1432 bestWidth = width; 1433 break; 1434 } 1435 newMask = newMask << width; 1436 } 1437 } 1438 } 1439 if (bestWidth) { 1440 MVT newVT = MVT::getIntegerVT(bestWidth); 1441 if (newVT.isRound()) { 1442 MVT PtrType = Lod->getOperand(1).getValueType(); 1443 SDValue Ptr = Lod->getBasePtr(); 1444 if (bestOffset != 0) 1445 Ptr = DAG.getNode(ISD::ADD, PtrType, Lod->getBasePtr(), 1446 DAG.getConstant(bestOffset, PtrType)); 1447 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1448 SDValue NewLoad = DAG.getLoad(newVT, Lod->getChain(), Ptr, 1449 Lod->getSrcValue(), 1450 Lod->getSrcValueOffset() + bestOffset, 1451 false, NewAlign); 1452 return DAG.getSetCC(VT, DAG.getNode(ISD::AND, newVT, NewLoad, 1453 DAG.getConstant(bestMask, newVT)), 1454 DAG.getConstant(0LL, newVT), Cond); 1455 } 1456 } 1457 } 1458 1459 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1460 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1461 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1462 1463 // If the comparison constant has bits in the upper part, the 1464 // zero-extended value could never match. 1465 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1466 C1.getBitWidth() - InSize))) { 1467 switch (Cond) { 1468 case ISD::SETUGT: 1469 case ISD::SETUGE: 1470 case ISD::SETEQ: return DAG.getConstant(0, VT); 1471 case ISD::SETULT: 1472 case ISD::SETULE: 1473 case ISD::SETNE: return DAG.getConstant(1, VT); 1474 case ISD::SETGT: 1475 case ISD::SETGE: 1476 // True if the sign bit of C1 is set. 1477 return DAG.getConstant(C1.isNegative(), VT); 1478 case ISD::SETLT: 1479 case ISD::SETLE: 1480 // True if the sign bit of C1 isn't set. 1481 return DAG.getConstant(C1.isNonNegative(), VT); 1482 default: 1483 break; 1484 } 1485 } 1486 1487 // Otherwise, we can perform the comparison with the low bits. 1488 switch (Cond) { 1489 case ISD::SETEQ: 1490 case ISD::SETNE: 1491 case ISD::SETUGT: 1492 case ISD::SETUGE: 1493 case ISD::SETULT: 1494 case ISD::SETULE: 1495 return DAG.getSetCC(VT, N0.getOperand(0), 1496 DAG.getConstant(APInt(C1).trunc(InSize), 1497 N0.getOperand(0).getValueType()), 1498 Cond); 1499 default: 1500 break; // todo, be more careful with signed comparisons 1501 } 1502 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1503 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1504 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1505 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1506 MVT ExtDstTy = N0.getValueType(); 1507 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1508 1509 // If the extended part has any inconsistent bits, it cannot ever 1510 // compare equal. In other words, they have to be all ones or all 1511 // zeros. 1512 APInt ExtBits = 1513 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1514 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1515 return DAG.getConstant(Cond == ISD::SETNE, VT); 1516 1517 SDValue ZextOp; 1518 MVT Op0Ty = N0.getOperand(0).getValueType(); 1519 if (Op0Ty == ExtSrcTy) { 1520 ZextOp = N0.getOperand(0); 1521 } else { 1522 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1523 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1524 DAG.getConstant(Imm, Op0Ty)); 1525 } 1526 if (!DCI.isCalledByLegalizer()) 1527 DCI.AddToWorklist(ZextOp.getNode()); 1528 // Otherwise, make this a use of a zext. 1529 return DAG.getSetCC(VT, ZextOp, 1530 DAG.getConstant(C1 & APInt::getLowBitsSet( 1531 ExtDstTyBits, 1532 ExtSrcTyBits), 1533 ExtDstTy), 1534 Cond); 1535 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1536 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1537 1538 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1539 if (N0.getOpcode() == ISD::SETCC) { 1540 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1541 if (TrueWhenTrue) 1542 return N0; 1543 1544 // Invert the condition. 1545 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1546 CC = ISD::getSetCCInverse(CC, 1547 N0.getOperand(0).getValueType().isInteger()); 1548 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1549 } 1550 1551 if ((N0.getOpcode() == ISD::XOR || 1552 (N0.getOpcode() == ISD::AND && 1553 N0.getOperand(0).getOpcode() == ISD::XOR && 1554 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1555 isa<ConstantSDNode>(N0.getOperand(1)) && 1556 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1557 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1558 // can only do this if the top bits are known zero. 1559 unsigned BitWidth = N0.getValueSizeInBits(); 1560 if (DAG.MaskedValueIsZero(N0, 1561 APInt::getHighBitsSet(BitWidth, 1562 BitWidth-1))) { 1563 // Okay, get the un-inverted input value. 1564 SDValue Val; 1565 if (N0.getOpcode() == ISD::XOR) 1566 Val = N0.getOperand(0); 1567 else { 1568 assert(N0.getOpcode() == ISD::AND && 1569 N0.getOperand(0).getOpcode() == ISD::XOR); 1570 // ((X^1)&1)^1 -> X & 1 1571 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1572 N0.getOperand(0).getOperand(0), 1573 N0.getOperand(1)); 1574 } 1575 return DAG.getSetCC(VT, Val, N1, 1576 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1577 } 1578 } 1579 } 1580 1581 APInt MinVal, MaxVal; 1582 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1583 if (ISD::isSignedIntSetCC(Cond)) { 1584 MinVal = APInt::getSignedMinValue(OperandBitSize); 1585 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1586 } else { 1587 MinVal = APInt::getMinValue(OperandBitSize); 1588 MaxVal = APInt::getMaxValue(OperandBitSize); 1589 } 1590 1591 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1592 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1593 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1594 // X >= C0 --> X > (C0-1) 1595 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1596 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1597 } 1598 1599 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1600 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1601 // X <= C0 --> X < (C0+1) 1602 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1603 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1604 } 1605 1606 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1607 return DAG.getConstant(0, VT); // X < MIN --> false 1608 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1609 return DAG.getConstant(1, VT); // X >= MIN --> true 1610 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1611 return DAG.getConstant(0, VT); // X > MAX --> false 1612 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1613 return DAG.getConstant(1, VT); // X <= MAX --> true 1614 1615 // Canonicalize setgt X, Min --> setne X, Min 1616 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1617 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1618 // Canonicalize setlt X, Max --> setne X, Max 1619 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1620 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1621 1622 // If we have setult X, 1, turn it into seteq X, 0 1623 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1624 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1625 ISD::SETEQ); 1626 // If we have setugt X, Max-1, turn it into seteq X, Max 1627 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1628 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1629 ISD::SETEQ); 1630 1631 // If we have "setcc X, C0", check to see if we can shrink the immediate 1632 // by changing cc. 1633 1634 // SETUGT X, SINTMAX -> SETLT X, 0 1635 if (Cond == ISD::SETUGT && 1636 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1637 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1638 ISD::SETLT); 1639 1640 // SETULT X, SINTMIN -> SETGT X, -1 1641 if (Cond == ISD::SETULT && 1642 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1643 SDValue ConstMinusOne = 1644 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1645 N1.getValueType()); 1646 return DAG.getSetCC(VT, N0, ConstMinusOne, ISD::SETGT); 1647 } 1648 1649 // Fold bit comparisons when we can. 1650 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1651 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1652 if (ConstantSDNode *AndRHS = 1653 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1654 MVT ShiftTy = DCI.isBeforeLegalize() ? 1655 getPointerTy() : getShiftAmountTy(); 1656 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1657 // Perform the xform if the AND RHS is a single bit. 1658 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1659 return DAG.getNode(ISD::SRL, VT, N0, 1660 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1661 ShiftTy)); 1662 } 1663 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1664 // (X & 8) == 8 --> (X & 8) >> 3 1665 // Perform the xform if C1 is a single bit. 1666 if (C1.isPowerOf2()) { 1667 return DAG.getNode(ISD::SRL, VT, N0, 1668 DAG.getConstant(C1.logBase2(), ShiftTy)); 1669 } 1670 } 1671 } 1672 } 1673 } else if (isa<ConstantSDNode>(N0.getNode())) { 1674 // Ensure that the constant occurs on the RHS. 1675 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1676 } 1677 1678 if (isa<ConstantFPSDNode>(N0.getNode())) { 1679 // Constant fold or commute setcc. 1680 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1681 if (O.getNode()) return O; 1682 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1683 // If the RHS of an FP comparison is a constant, simplify it away in 1684 // some cases. 1685 if (CFP->getValueAPF().isNaN()) { 1686 // If an operand is known to be a nan, we can fold it. 1687 switch (ISD::getUnorderedFlavor(Cond)) { 1688 default: assert(0 && "Unknown flavor!"); 1689 case 0: // Known false. 1690 return DAG.getConstant(0, VT); 1691 case 1: // Known true. 1692 return DAG.getConstant(1, VT); 1693 case 2: // Undefined. 1694 return DAG.getNode(ISD::UNDEF, VT); 1695 } 1696 } 1697 1698 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1699 // constant if knowing that the operand is non-nan is enough. We prefer to 1700 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1701 // materialize 0.0. 1702 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1703 return DAG.getSetCC(VT, N0, N0, Cond); 1704 } 1705 1706 if (N0 == N1) { 1707 // We can always fold X == X for integer setcc's. 1708 if (N0.getValueType().isInteger()) 1709 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1710 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1711 if (UOF == 2) // FP operators that are undefined on NaNs. 1712 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1713 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1714 return DAG.getConstant(UOF, VT); 1715 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1716 // if it is not already. 1717 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1718 if (NewCond != Cond) 1719 return DAG.getSetCC(VT, N0, N1, NewCond); 1720 } 1721 1722 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1723 N0.getValueType().isInteger()) { 1724 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1725 N0.getOpcode() == ISD::XOR) { 1726 // Simplify (X+Y) == (X+Z) --> Y == Z 1727 if (N0.getOpcode() == N1.getOpcode()) { 1728 if (N0.getOperand(0) == N1.getOperand(0)) 1729 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1730 if (N0.getOperand(1) == N1.getOperand(1)) 1731 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1732 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1733 // If X op Y == Y op X, try other combinations. 1734 if (N0.getOperand(0) == N1.getOperand(1)) 1735 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1736 if (N0.getOperand(1) == N1.getOperand(0)) 1737 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1738 } 1739 } 1740 1741 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1742 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1743 // Turn (X+C1) == C2 --> X == C2-C1 1744 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1745 return DAG.getSetCC(VT, N0.getOperand(0), 1746 DAG.getConstant(RHSC->getAPIntValue()- 1747 LHSR->getAPIntValue(), 1748 N0.getValueType()), Cond); 1749 } 1750 1751 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1752 if (N0.getOpcode() == ISD::XOR) 1753 // If we know that all of the inverted bits are zero, don't bother 1754 // performing the inversion. 1755 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1756 return 1757 DAG.getSetCC(VT, N0.getOperand(0), 1758 DAG.getConstant(LHSR->getAPIntValue() ^ 1759 RHSC->getAPIntValue(), 1760 N0.getValueType()), 1761 Cond); 1762 } 1763 1764 // Turn (C1-X) == C2 --> X == C1-C2 1765 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1766 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1767 return 1768 DAG.getSetCC(VT, N0.getOperand(1), 1769 DAG.getConstant(SUBC->getAPIntValue() - 1770 RHSC->getAPIntValue(), 1771 N0.getValueType()), 1772 Cond); 1773 } 1774 } 1775 } 1776 1777 // Simplify (X+Z) == X --> Z == 0 1778 if (N0.getOperand(0) == N1) 1779 return DAG.getSetCC(VT, N0.getOperand(1), 1780 DAG.getConstant(0, N0.getValueType()), Cond); 1781 if (N0.getOperand(1) == N1) { 1782 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1783 return DAG.getSetCC(VT, N0.getOperand(0), 1784 DAG.getConstant(0, N0.getValueType()), Cond); 1785 else if (N0.getNode()->hasOneUse()) { 1786 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1787 // (Z-X) == X --> Z == X<<1 1788 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1789 N1, 1790 DAG.getConstant(1, getShiftAmountTy())); 1791 if (!DCI.isCalledByLegalizer()) 1792 DCI.AddToWorklist(SH.getNode()); 1793 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1794 } 1795 } 1796 } 1797 1798 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1799 N1.getOpcode() == ISD::XOR) { 1800 // Simplify X == (X+Z) --> Z == 0 1801 if (N1.getOperand(0) == N0) { 1802 return DAG.getSetCC(VT, N1.getOperand(1), 1803 DAG.getConstant(0, N1.getValueType()), Cond); 1804 } else if (N1.getOperand(1) == N0) { 1805 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1806 return DAG.getSetCC(VT, N1.getOperand(0), 1807 DAG.getConstant(0, N1.getValueType()), Cond); 1808 } else if (N1.getNode()->hasOneUse()) { 1809 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1810 // X == (Z-X) --> X<<1 == Z 1811 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1812 DAG.getConstant(1, getShiftAmountTy())); 1813 if (!DCI.isCalledByLegalizer()) 1814 DCI.AddToWorklist(SH.getNode()); 1815 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1816 } 1817 } 1818 } 1819 1820 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1821 if (N0.getOpcode() == ISD::AND) 1822 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1823 if (ValueHasAtMostOneBitSet(N1, DAG)) { 1824 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1825 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1826 return DAG.getSetCC(VT, N0, Zero, Cond); 1827 } 1828 } 1829 if (N1.getOpcode() == ISD::AND) 1830 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1831 if (ValueHasAtMostOneBitSet(N0, DAG)) { 1832 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1833 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1834 return DAG.getSetCC(VT, N1, Zero, Cond); 1835 } 1836 } 1837 } 1838 1839 // Fold away ALL boolean setcc's. 1840 SDValue Temp; 1841 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1842 switch (Cond) { 1843 default: assert(0 && "Unknown integer setcc!"); 1844 case ISD::SETEQ: // X == Y -> ~(X^Y) 1845 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1846 N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1); 1847 if (!DCI.isCalledByLegalizer()) 1848 DCI.AddToWorklist(Temp.getNode()); 1849 break; 1850 case ISD::SETNE: // X != Y --> (X^Y) 1851 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1852 break; 1853 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1854 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1855 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); 1856 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1857 if (!DCI.isCalledByLegalizer()) 1858 DCI.AddToWorklist(Temp.getNode()); 1859 break; 1860 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1861 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1862 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); 1863 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1864 if (!DCI.isCalledByLegalizer()) 1865 DCI.AddToWorklist(Temp.getNode()); 1866 break; 1867 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1868 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1869 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); 1870 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1871 if (!DCI.isCalledByLegalizer()) 1872 DCI.AddToWorklist(Temp.getNode()); 1873 break; 1874 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1875 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1876 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); 1877 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1878 break; 1879 } 1880 if (VT != MVT::i1) { 1881 if (!DCI.isCalledByLegalizer()) 1882 DCI.AddToWorklist(N0.getNode()); 1883 // FIXME: If running after legalize, we probably can't do this. 1884 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1885 } 1886 return N0; 1887 } 1888 1889 // Could not fold it. 1890 return SDValue(); 1891} 1892 1893/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1894/// node is a GlobalAddress + offset. 1895bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1896 int64_t &Offset) const { 1897 if (isa<GlobalAddressSDNode>(N)) { 1898 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1899 GA = GASD->getGlobal(); 1900 Offset += GASD->getOffset(); 1901 return true; 1902 } 1903 1904 if (N->getOpcode() == ISD::ADD) { 1905 SDValue N1 = N->getOperand(0); 1906 SDValue N2 = N->getOperand(1); 1907 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1908 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1909 if (V) { 1910 Offset += V->getSExtValue(); 1911 return true; 1912 } 1913 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1914 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1915 if (V) { 1916 Offset += V->getSExtValue(); 1917 return true; 1918 } 1919 } 1920 } 1921 return false; 1922} 1923 1924 1925/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1926/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1927/// location that the 'Base' load is loading from. 1928bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1929 unsigned Bytes, int Dist, 1930 const MachineFrameInfo *MFI) const { 1931 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1932 return false; 1933 MVT VT = LD->getValueType(0); 1934 if (VT.getSizeInBits() / 8 != Bytes) 1935 return false; 1936 1937 SDValue Loc = LD->getOperand(1); 1938 SDValue BaseLoc = Base->getOperand(1); 1939 if (Loc.getOpcode() == ISD::FrameIndex) { 1940 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1941 return false; 1942 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1943 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1944 int FS = MFI->getObjectSize(FI); 1945 int BFS = MFI->getObjectSize(BFI); 1946 if (FS != BFS || FS != (int)Bytes) return false; 1947 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1948 } 1949 1950 GlobalValue *GV1 = NULL; 1951 GlobalValue *GV2 = NULL; 1952 int64_t Offset1 = 0; 1953 int64_t Offset2 = 0; 1954 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1955 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1956 if (isGA1 && isGA2 && GV1 == GV2) 1957 return Offset1 == (Offset2 + Dist*Bytes); 1958 return false; 1959} 1960 1961 1962SDValue TargetLowering:: 1963PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1964 // Default implementation: no optimization. 1965 return SDValue(); 1966} 1967 1968//===----------------------------------------------------------------------===// 1969// Inline Assembler Implementation Methods 1970//===----------------------------------------------------------------------===// 1971 1972 1973TargetLowering::ConstraintType 1974TargetLowering::getConstraintType(const std::string &Constraint) const { 1975 // FIXME: lots more standard ones to handle. 1976 if (Constraint.size() == 1) { 1977 switch (Constraint[0]) { 1978 default: break; 1979 case 'r': return C_RegisterClass; 1980 case 'm': // memory 1981 case 'o': // offsetable 1982 case 'V': // not offsetable 1983 return C_Memory; 1984 case 'i': // Simple Integer or Relocatable Constant 1985 case 'n': // Simple Integer 1986 case 's': // Relocatable Constant 1987 case 'X': // Allow ANY value. 1988 case 'I': // Target registers. 1989 case 'J': 1990 case 'K': 1991 case 'L': 1992 case 'M': 1993 case 'N': 1994 case 'O': 1995 case 'P': 1996 return C_Other; 1997 } 1998 } 1999 2000 if (Constraint.size() > 1 && Constraint[0] == '{' && 2001 Constraint[Constraint.size()-1] == '}') 2002 return C_Register; 2003 return C_Unknown; 2004} 2005 2006/// LowerXConstraint - try to replace an X constraint, which matches anything, 2007/// with another that has more specific requirements based on the type of the 2008/// corresponding operand. 2009const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2010 if (ConstraintVT.isInteger()) 2011 return "r"; 2012 if (ConstraintVT.isFloatingPoint()) 2013 return "f"; // works for many targets 2014 return 0; 2015} 2016 2017/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2018/// vector. If it is invalid, don't add anything to Ops. 2019void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2020 char ConstraintLetter, 2021 bool hasMemory, 2022 std::vector<SDValue> &Ops, 2023 SelectionDAG &DAG) const { 2024 switch (ConstraintLetter) { 2025 default: break; 2026 case 'X': // Allows any operand; labels (basic block) use this. 2027 if (Op.getOpcode() == ISD::BasicBlock) { 2028 Ops.push_back(Op); 2029 return; 2030 } 2031 // fall through 2032 case 'i': // Simple Integer or Relocatable Constant 2033 case 'n': // Simple Integer 2034 case 's': { // Relocatable Constant 2035 // These operands are interested in values of the form (GV+C), where C may 2036 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2037 // is possible and fine if either GV or C are missing. 2038 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2039 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2040 2041 // If we have "(add GV, C)", pull out GV/C 2042 if (Op.getOpcode() == ISD::ADD) { 2043 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2044 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2045 if (C == 0 || GA == 0) { 2046 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2047 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2048 } 2049 if (C == 0 || GA == 0) 2050 C = 0, GA = 0; 2051 } 2052 2053 // If we find a valid operand, map to the TargetXXX version so that the 2054 // value itself doesn't get selected. 2055 if (GA) { // Either &GV or &GV+C 2056 if (ConstraintLetter != 'n') { 2057 int64_t Offs = GA->getOffset(); 2058 if (C) Offs += C->getZExtValue(); 2059 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2060 Op.getValueType(), Offs)); 2061 return; 2062 } 2063 } 2064 if (C) { // just C, no GV. 2065 // Simple constants are not allowed for 's'. 2066 if (ConstraintLetter != 's') { 2067 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), 2068 Op.getValueType())); 2069 return; 2070 } 2071 } 2072 break; 2073 } 2074 } 2075} 2076 2077std::vector<unsigned> TargetLowering:: 2078getRegClassForInlineAsmConstraint(const std::string &Constraint, 2079 MVT VT) const { 2080 return std::vector<unsigned>(); 2081} 2082 2083 2084std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2085getRegForInlineAsmConstraint(const std::string &Constraint, 2086 MVT VT) const { 2087 if (Constraint[0] != '{') 2088 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2089 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2090 2091 // Remove the braces from around the name. 2092 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2093 2094 // Figure out which register class contains this reg. 2095 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2096 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2097 E = RI->regclass_end(); RCI != E; ++RCI) { 2098 const TargetRegisterClass *RC = *RCI; 2099 2100 // If none of the the value types for this register class are valid, we 2101 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2102 bool isLegal = false; 2103 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2104 I != E; ++I) { 2105 if (isTypeLegal(*I)) { 2106 isLegal = true; 2107 break; 2108 } 2109 } 2110 2111 if (!isLegal) continue; 2112 2113 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2114 I != E; ++I) { 2115 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2116 return std::make_pair(*I, RC); 2117 } 2118 } 2119 2120 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2121} 2122 2123//===----------------------------------------------------------------------===// 2124// Constraint Selection. 2125 2126/// isMatchingInputConstraint - Return true of this is an input operand that is 2127/// a matching constraint like "4". 2128bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2129 assert(!ConstraintCode.empty() && "No known constraint!"); 2130 return isdigit(ConstraintCode[0]); 2131} 2132 2133/// getMatchedOperand - If this is an input matching constraint, this method 2134/// returns the output operand it matches. 2135unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2136 assert(!ConstraintCode.empty() && "No known constraint!"); 2137 return atoi(ConstraintCode.c_str()); 2138} 2139 2140 2141/// getConstraintGenerality - Return an integer indicating how general CT 2142/// is. 2143static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2144 switch (CT) { 2145 default: assert(0 && "Unknown constraint type!"); 2146 case TargetLowering::C_Other: 2147 case TargetLowering::C_Unknown: 2148 return 0; 2149 case TargetLowering::C_Register: 2150 return 1; 2151 case TargetLowering::C_RegisterClass: 2152 return 2; 2153 case TargetLowering::C_Memory: 2154 return 3; 2155 } 2156} 2157 2158/// ChooseConstraint - If there are multiple different constraints that we 2159/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2160/// This is somewhat tricky: constraints fall into four classes: 2161/// Other -> immediates and magic values 2162/// Register -> one specific register 2163/// RegisterClass -> a group of regs 2164/// Memory -> memory 2165/// Ideally, we would pick the most specific constraint possible: if we have 2166/// something that fits into a register, we would pick it. The problem here 2167/// is that if we have something that could either be in a register or in 2168/// memory that use of the register could cause selection of *other* 2169/// operands to fail: they might only succeed if we pick memory. Because of 2170/// this the heuristic we use is: 2171/// 2172/// 1) If there is an 'other' constraint, and if the operand is valid for 2173/// that constraint, use it. This makes us take advantage of 'i' 2174/// constraints when available. 2175/// 2) Otherwise, pick the most general constraint present. This prefers 2176/// 'm' over 'r', for example. 2177/// 2178static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2179 bool hasMemory, const TargetLowering &TLI, 2180 SDValue Op, SelectionDAG *DAG) { 2181 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2182 unsigned BestIdx = 0; 2183 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2184 int BestGenerality = -1; 2185 2186 // Loop over the options, keeping track of the most general one. 2187 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2188 TargetLowering::ConstraintType CType = 2189 TLI.getConstraintType(OpInfo.Codes[i]); 2190 2191 // If this is an 'other' constraint, see if the operand is valid for it. 2192 // For example, on X86 we might have an 'rI' constraint. If the operand 2193 // is an integer in the range [0..31] we want to use I (saving a load 2194 // of a register), otherwise we must use 'r'. 2195 if (CType == TargetLowering::C_Other && Op.getNode()) { 2196 assert(OpInfo.Codes[i].size() == 1 && 2197 "Unhandled multi-letter 'other' constraint"); 2198 std::vector<SDValue> ResultOps; 2199 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2200 ResultOps, *DAG); 2201 if (!ResultOps.empty()) { 2202 BestType = CType; 2203 BestIdx = i; 2204 break; 2205 } 2206 } 2207 2208 // This constraint letter is more general than the previous one, use it. 2209 int Generality = getConstraintGenerality(CType); 2210 if (Generality > BestGenerality) { 2211 BestType = CType; 2212 BestIdx = i; 2213 BestGenerality = Generality; 2214 } 2215 } 2216 2217 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2218 OpInfo.ConstraintType = BestType; 2219} 2220 2221/// ComputeConstraintToUse - Determines the constraint code and constraint 2222/// type to use for the specific AsmOperandInfo, setting 2223/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2224void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2225 SDValue Op, 2226 bool hasMemory, 2227 SelectionDAG *DAG) const { 2228 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2229 2230 // Single-letter constraints ('r') are very common. 2231 if (OpInfo.Codes.size() == 1) { 2232 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2233 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2234 } else { 2235 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2236 } 2237 2238 // 'X' matches anything. 2239 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2240 // Labels and constants are handled elsewhere ('X' is the only thing 2241 // that matches labels). 2242 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2243 isa<ConstantInt>(OpInfo.CallOperandVal)) 2244 return; 2245 2246 // Otherwise, try to resolve it to something we know about by looking at 2247 // the actual operand type. 2248 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2249 OpInfo.ConstraintCode = Repl; 2250 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2251 } 2252 } 2253} 2254 2255//===----------------------------------------------------------------------===// 2256// Loop Strength Reduction hooks 2257//===----------------------------------------------------------------------===// 2258 2259/// isLegalAddressingMode - Return true if the addressing mode represented 2260/// by AM is legal for this target, for a load/store of the specified type. 2261bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2262 const Type *Ty) const { 2263 // The default implementation of this implements a conservative RISCy, r+r and 2264 // r+i addr mode. 2265 2266 // Allows a sign-extended 16-bit immediate field. 2267 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2268 return false; 2269 2270 // No global is ever allowed as a base. 2271 if (AM.BaseGV) 2272 return false; 2273 2274 // Only support r+r, 2275 switch (AM.Scale) { 2276 case 0: // "r+i" or just "i", depending on HasBaseReg. 2277 break; 2278 case 1: 2279 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2280 return false; 2281 // Otherwise we have r+r or r+i. 2282 break; 2283 case 2: 2284 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2285 return false; 2286 // Allow 2*r as r+r. 2287 break; 2288 } 2289 2290 return true; 2291} 2292 2293struct mu { 2294 APInt m; // magic number 2295 bool a; // add indicator 2296 unsigned s; // shift amount 2297}; 2298 2299/// magicu - calculate the magic numbers required to codegen an integer udiv as 2300/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2301static mu magicu(const APInt& d) { 2302 unsigned p; 2303 APInt nc, delta, q1, r1, q2, r2; 2304 struct mu magu; 2305 magu.a = 0; // initialize "add" indicator 2306 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2307 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2308 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2309 2310 nc = allOnes - (-d).urem(d); 2311 p = d.getBitWidth() - 1; // initialize p 2312 q1 = signedMin.udiv(nc); // initialize q1 = 2p/nc 2313 r1 = signedMin - q1*nc; // initialize r1 = rem(2p,nc) 2314 q2 = signedMax.udiv(d); // initialize q2 = (2p-1)/d 2315 r2 = signedMax - q2*d; // initialize r2 = rem((2p-1),d) 2316 do { 2317 p = p + 1; 2318 if (r1.uge(nc - r1)) { 2319 q1 = q1 + q1 + 1; // update q1 2320 r1 = r1 + r1 - nc; // update r1 2321 } 2322 else { 2323 q1 = q1+q1; // update q1 2324 r1 = r1+r1; // update r1 2325 } 2326 if ((r2 + 1).uge(d - r2)) { 2327 if (q2.uge(signedMax)) magu.a = 1; 2328 q2 = q2+q2 + 1; // update q2 2329 r2 = r2+r2 + 1 - d; // update r2 2330 } 2331 else { 2332 if (q2.uge(signedMin)) magu.a = 1; 2333 q2 = q2+q2; // update q2 2334 r2 = r2+r2 + 1; // update r2 2335 } 2336 delta = d - 1 - r2; 2337 } while (p < d.getBitWidth()*2 && 2338 (q1.ult(delta) || (q1 == delta && r1 == 0))); 2339 magu.m = q2 + 1; // resulting magic number 2340 magu.s = p - d.getBitWidth(); // resulting shift 2341 return magu; 2342} 2343 2344// Magic for divide replacement 2345struct ms { 2346 APInt m; // magic number 2347 unsigned s; // shift amount 2348}; 2349 2350/// magic - calculate the magic numbers required to codegen an integer sdiv as 2351/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2352/// or -1. 2353static ms magic(const APInt& d) { 2354 unsigned p; 2355 APInt ad, anc, delta, q1, r1, q2, r2, t; 2356 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2357 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2358 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2359 struct ms mag; 2360 2361 ad = d.abs(); 2362 t = signedMin + (d.lshr(d.getBitWidth() - 1)); 2363 anc = t - 1 - t.urem(ad); // absolute value of nc 2364 p = d.getBitWidth() - 1; // initialize p 2365 q1 = signedMin.udiv(anc); // initialize q1 = 2p/abs(nc) 2366 r1 = signedMin - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2367 q2 = signedMin.udiv(ad); // initialize q2 = 2p/abs(d) 2368 r2 = signedMin - q2*ad; // initialize r2 = rem(2p,abs(d)) 2369 do { 2370 p = p + 1; 2371 q1 = q1<<1; // update q1 = 2p/abs(nc) 2372 r1 = r1<<1; // update r1 = rem(2p/abs(nc)) 2373 if (r1.uge(anc)) { // must be unsigned comparison 2374 q1 = q1 + 1; 2375 r1 = r1 - anc; 2376 } 2377 q2 = q2<<1; // update q2 = 2p/abs(d) 2378 r2 = r2<<1; // update r2 = rem(2p/abs(d)) 2379 if (r2.uge(ad)) { // must be unsigned comparison 2380 q2 = q2 + 1; 2381 r2 = r2 - ad; 2382 } 2383 delta = ad - r2; 2384 } while (q1.ule(delta) || (q1 == delta && r1 == 0)); 2385 2386 mag.m = q2 + 1; 2387 if (d.isNegative()) mag.m = -mag.m; // resulting magic number 2388 mag.s = p - d.getBitWidth(); // resulting shift 2389 return mag; 2390} 2391 2392/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2393/// return a DAG expression to select that will generate the same value by 2394/// multiplying by a magic number. See: 2395/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2396SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2397 std::vector<SDNode*>* Created) const { 2398 MVT VT = N->getValueType(0); 2399 2400 // Check to see if we can do this. 2401 // FIXME: We should be more aggressive here. 2402 if (!isTypeLegal(VT)) 2403 return SDValue(); 2404 2405 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2406 ms magics = magic(d); 2407 2408 // Multiply the numerator (operand 0) by the magic value 2409 // FIXME: We should support doing a MUL in a wider type 2410 SDValue Q; 2411 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2412 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2413 DAG.getConstant(magics.m, VT)); 2414 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2415 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2416 N->getOperand(0), 2417 DAG.getConstant(magics.m, VT)).getNode(), 1); 2418 else 2419 return SDValue(); // No mulhs or equvialent 2420 // If d > 0 and m < 0, add the numerator 2421 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2422 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2423 if (Created) 2424 Created->push_back(Q.getNode()); 2425 } 2426 // If d < 0 and m > 0, subtract the numerator. 2427 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2428 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2429 if (Created) 2430 Created->push_back(Q.getNode()); 2431 } 2432 // Shift right algebraic if shift value is nonzero 2433 if (magics.s > 0) { 2434 Q = DAG.getNode(ISD::SRA, VT, Q, 2435 DAG.getConstant(magics.s, getShiftAmountTy())); 2436 if (Created) 2437 Created->push_back(Q.getNode()); 2438 } 2439 // Extract the sign bit and add it to the quotient 2440 SDValue T = 2441 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2442 getShiftAmountTy())); 2443 if (Created) 2444 Created->push_back(T.getNode()); 2445 return DAG.getNode(ISD::ADD, VT, Q, T); 2446} 2447 2448/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2449/// return a DAG expression to select that will generate the same value by 2450/// multiplying by a magic number. See: 2451/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2452SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2453 std::vector<SDNode*>* Created) const { 2454 MVT VT = N->getValueType(0); 2455 2456 // Check to see if we can do this. 2457 // FIXME: We should be more aggressive here. 2458 if (!isTypeLegal(VT)) 2459 return SDValue(); 2460 2461 // FIXME: We should use a narrower constant when the upper 2462 // bits are known to be zero. 2463 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2464 mu magics = magicu(N1C->getAPIntValue()); 2465 2466 // Multiply the numerator (operand 0) by the magic value 2467 // FIXME: We should support doing a MUL in a wider type 2468 SDValue Q; 2469 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2470 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2471 DAG.getConstant(magics.m, VT)); 2472 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2473 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2474 N->getOperand(0), 2475 DAG.getConstant(magics.m, VT)).getNode(), 1); 2476 else 2477 return SDValue(); // No mulhu or equvialent 2478 if (Created) 2479 Created->push_back(Q.getNode()); 2480 2481 if (magics.a == 0) { 2482 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2483 "We shouldn't generate an undefined shift!"); 2484 return DAG.getNode(ISD::SRL, VT, Q, 2485 DAG.getConstant(magics.s, getShiftAmountTy())); 2486 } else { 2487 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2488 if (Created) 2489 Created->push_back(NPQ.getNode()); 2490 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2491 DAG.getConstant(1, getShiftAmountTy())); 2492 if (Created) 2493 Created->push_back(NPQ.getNode()); 2494 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2495 if (Created) 2496 Created->push_back(NPQ.getNode()); 2497 return DAG.getNode(ISD::SRL, VT, NPQ, 2498 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2499 } 2500} 2501