TargetLowering.cpp revision b6b17ffbc61025c6b3233787ccce2e6335d60b49
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetMachine.h" 16#include "llvm/Target/MRegisterInfo.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/ADT/StringExtras.h" 19#include "llvm/Support/MathExtras.h" 20using namespace llvm; 21 22TargetLowering::TargetLowering(TargetMachine &tm) 23 : TM(tm), TD(TM.getTargetData()) { 24 assert(ISD::BUILTIN_OP_END <= 156 && 25 "Fixed size array in TargetLowering is not large enough!"); 26 // All operations default to being supported. 27 memset(OpActions, 0, sizeof(OpActions)); 28 29 IsLittleEndian = TD.isLittleEndian(); 30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); 31 ShiftAmtHandling = Undefined; 32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 33 memset(TargetDAGCombineArray, 0, 34 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0])); 35 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 36 allowUnalignedMemoryAccesses = false; 37 UseUnderscoreSetJmpLongJmp = false; 38 IntDivIsCheap = false; 39 Pow2DivIsCheap = false; 40 StackPointerRegisterToSaveRestore = 0; 41 SchedPreferenceInfo = SchedulingForLatency; 42} 43 44TargetLowering::~TargetLowering() {} 45 46/// setValueTypeAction - Set the action for a particular value type. This 47/// assumes an action has not already been set for this value type. 48static void SetValueTypeAction(MVT::ValueType VT, 49 TargetLowering::LegalizeAction Action, 50 TargetLowering &TLI, 51 MVT::ValueType *TransformToType, 52 TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 53 ValueTypeActions.setTypeAction(VT, Action); 54 if (Action == TargetLowering::Promote) { 55 MVT::ValueType PromoteTo; 56 if (VT == MVT::f32) 57 PromoteTo = MVT::f64; 58 else { 59 unsigned LargerReg = VT+1; 60 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 61 ++LargerReg; 62 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 63 "Nothing to promote to??"); 64 } 65 PromoteTo = (MVT::ValueType)LargerReg; 66 } 67 68 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 69 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 70 "Can only promote from int->int or fp->fp!"); 71 assert(VT < PromoteTo && "Must promote to a larger type!"); 72 TransformToType[VT] = PromoteTo; 73 } else if (Action == TargetLowering::Expand) { 74 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 75 "Cannot expand this type: target must support SOME integer reg!"); 76 // Expand to the next smaller integer type! 77 TransformToType[VT] = (MVT::ValueType)(VT-1); 78 } 79} 80 81 82/// computeRegisterProperties - Once all of the register classes are added, 83/// this allows us to compute derived properties we expose. 84void TargetLowering::computeRegisterProperties() { 85 assert(MVT::LAST_VALUETYPE <= 32 && 86 "Too many value types for ValueTypeActions to hold!"); 87 88 // Everything defaults to one. 89 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 90 NumElementsForVT[i] = 1; 91 92 // Find the largest integer register class. 93 unsigned LargestIntReg = MVT::i128; 94 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 95 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 96 97 // Every integer value type larger than this largest register takes twice as 98 // many registers to represent as the previous ValueType. 99 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 100 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 101 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 102 103 // Inspect all of the ValueType's possible, deciding how to process them. 104 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 105 // If we are expanding this type, expand it! 106 if (getNumElements((MVT::ValueType)IntReg) != 1) 107 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 108 ValueTypeActions); 109 else if (!isTypeLegal((MVT::ValueType)IntReg)) 110 // Otherwise, if we don't have native support, we must promote to a 111 // larger type. 112 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 113 TransformToType, ValueTypeActions); 114 else 115 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 116 117 // If the target does not have native support for F32, promote it to F64. 118 if (!isTypeLegal(MVT::f32)) 119 SetValueTypeAction(MVT::f32, Promote, *this, 120 TransformToType, ValueTypeActions); 121 else 122 TransformToType[MVT::f32] = MVT::f32; 123 124 // Set MVT::Vector to always be Expanded 125 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 126 ValueTypeActions); 127 128 assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); 129 TransformToType[MVT::f64] = MVT::f64; 130} 131 132const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 133 return NULL; 134} 135 136//===----------------------------------------------------------------------===// 137// Optimization Methods 138//===----------------------------------------------------------------------===// 139 140/// ShrinkDemandedConstant - Check to see if the specified operand of the 141/// specified instruction is a constant integer. If so, check to see if there 142/// are any bits set in the constant that are not demanded. If so, shrink the 143/// constant and return true. 144bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 145 uint64_t Demanded) { 146 // FIXME: ISD::SELECT, ISD::SELECT_CC 147 switch(Op.getOpcode()) { 148 default: break; 149 case ISD::AND: 150 case ISD::OR: 151 case ISD::XOR: 152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 153 if ((~Demanded & C->getValue()) != 0) { 154 MVT::ValueType VT = Op.getValueType(); 155 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 156 DAG.getConstant(Demanded & C->getValue(), 157 VT)); 158 return CombineTo(Op, New); 159 } 160 break; 161 } 162 return false; 163} 164 165/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 166/// DemandedMask bits of the result of Op are ever used downstream. If we can 167/// use this information to simplify Op, create a new simplified DAG node and 168/// return true, returning the original and new nodes in Old and New. Otherwise, 169/// analyze the expression and return a mask of KnownOne and KnownZero bits for 170/// the expression (used to simplify the caller). The KnownZero/One bits may 171/// only be accurate for those bits in the DemandedMask. 172bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 173 uint64_t &KnownZero, 174 uint64_t &KnownOne, 175 TargetLoweringOpt &TLO, 176 unsigned Depth) const { 177 KnownZero = KnownOne = 0; // Don't know anything. 178 // Other users may use these bits. 179 if (!Op.Val->hasOneUse()) { 180 if (Depth != 0) { 181 // If not at the root, Just compute the KnownZero/KnownOne bits to 182 // simplify things downstream. 183 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 184 return false; 185 } 186 // If this is the root being simplified, allow it to have multiple uses, 187 // just set the DemandedMask to all bits. 188 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 189 } else if (DemandedMask == 0) { 190 // Not demanding any bits from Op. 191 if (Op.getOpcode() != ISD::UNDEF) 192 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 193 return false; 194 } else if (Depth == 6) { // Limit search depth. 195 return false; 196 } 197 198 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 199 switch (Op.getOpcode()) { 200 case ISD::Constant: 201 // We know all of the bits for a constant! 202 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 203 KnownZero = ~KnownOne & DemandedMask; 204 return false; // Don't fall through, will infinitely loop. 205 case ISD::AND: 206 // If the RHS is a constant, check to see if the LHS would be zero without 207 // using the bits from the RHS. Below, we use knowledge about the RHS to 208 // simplify the LHS, here we're using information from the LHS to simplify 209 // the RHS. 210 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 211 uint64_t LHSZero, LHSOne; 212 ComputeMaskedBits(Op.getOperand(0), DemandedMask, 213 LHSZero, LHSOne, Depth+1); 214 // If the LHS already has zeros where RHSC does, this and is dead. 215 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 216 return TLO.CombineTo(Op, Op.getOperand(0)); 217 // If any of the set bits in the RHS are known zero on the LHS, shrink 218 // the constant. 219 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 220 return true; 221 } 222 223 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 224 KnownOne, TLO, Depth+1)) 225 return true; 226 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 227 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 228 KnownZero2, KnownOne2, TLO, Depth+1)) 229 return true; 230 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 231 232 // If all of the demanded bits are known one on one side, return the other. 233 // These bits cannot contribute to the result of the 'and'. 234 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 235 return TLO.CombineTo(Op, Op.getOperand(0)); 236 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 237 return TLO.CombineTo(Op, Op.getOperand(1)); 238 // If all of the demanded bits in the inputs are known zeros, return zero. 239 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 240 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 241 // If the RHS is a constant, see if we can simplify it. 242 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 243 return true; 244 245 // Output known-1 bits are only known if set in both the LHS & RHS. 246 KnownOne &= KnownOne2; 247 // Output known-0 are known to be clear if zero in either the LHS | RHS. 248 KnownZero |= KnownZero2; 249 break; 250 case ISD::OR: 251 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 252 KnownOne, TLO, Depth+1)) 253 return true; 254 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 255 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 256 KnownZero2, KnownOne2, TLO, Depth+1)) 257 return true; 258 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 259 260 // If all of the demanded bits are known zero on one side, return the other. 261 // These bits cannot contribute to the result of the 'or'. 262 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 263 return TLO.CombineTo(Op, Op.getOperand(0)); 264 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 265 return TLO.CombineTo(Op, Op.getOperand(1)); 266 // If all of the potentially set bits on one side are known to be set on 267 // the other side, just use the 'other' side. 268 if ((DemandedMask & (~KnownZero) & KnownOne2) == 269 (DemandedMask & (~KnownZero))) 270 return TLO.CombineTo(Op, Op.getOperand(0)); 271 if ((DemandedMask & (~KnownZero2) & KnownOne) == 272 (DemandedMask & (~KnownZero2))) 273 return TLO.CombineTo(Op, Op.getOperand(1)); 274 // If the RHS is a constant, see if we can simplify it. 275 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 276 return true; 277 278 // Output known-0 bits are only known if clear in both the LHS & RHS. 279 KnownZero &= KnownZero2; 280 // Output known-1 are known to be set if set in either the LHS | RHS. 281 KnownOne |= KnownOne2; 282 break; 283 case ISD::XOR: 284 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 285 KnownOne, TLO, Depth+1)) 286 return true; 287 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 288 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 289 KnownOne2, TLO, Depth+1)) 290 return true; 291 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 292 293 // If all of the demanded bits are known zero on one side, return the other. 294 // These bits cannot contribute to the result of the 'xor'. 295 if ((DemandedMask & KnownZero) == DemandedMask) 296 return TLO.CombineTo(Op, Op.getOperand(0)); 297 if ((DemandedMask & KnownZero2) == DemandedMask) 298 return TLO.CombineTo(Op, Op.getOperand(1)); 299 300 // Output known-0 bits are known if clear or set in both the LHS & RHS. 301 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 302 // Output known-1 are known to be set if set in only one of the LHS, RHS. 303 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 304 305 // If all of the unknown bits are known to be zero on one side or the other 306 // (but not both) turn this into an *inclusive* or. 307 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 308 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut)) 309 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits) 310 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 311 Op.getOperand(0), 312 Op.getOperand(1))); 313 // If all of the demanded bits on one side are known, and all of the set 314 // bits on that side are also known to be set on the other side, turn this 315 // into an AND, as we know the bits will be cleared. 316 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 317 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 318 if ((KnownOne & KnownOne2) == KnownOne) { 319 MVT::ValueType VT = Op.getValueType(); 320 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 321 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 322 ANDC)); 323 } 324 } 325 326 // If the RHS is a constant, see if we can simplify it. 327 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 328 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 329 return true; 330 331 KnownZero = KnownZeroOut; 332 KnownOne = KnownOneOut; 333 break; 334 case ISD::SETCC: 335 // If we know the result of a setcc has the top bits zero, use this info. 336 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 337 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 338 break; 339 case ISD::SELECT: 340 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 341 KnownOne, TLO, Depth+1)) 342 return true; 343 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 344 KnownOne2, TLO, Depth+1)) 345 return true; 346 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 347 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 348 349 // If the operands are constants, see if we can simplify them. 350 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 351 return true; 352 353 // Only known if known in both the LHS and RHS. 354 KnownOne &= KnownOne2; 355 KnownZero &= KnownZero2; 356 break; 357 case ISD::SELECT_CC: 358 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 359 KnownOne, TLO, Depth+1)) 360 return true; 361 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 362 KnownOne2, TLO, Depth+1)) 363 return true; 364 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 365 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 366 367 // If the operands are constants, see if we can simplify them. 368 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 369 return true; 370 371 // Only known if known in both the LHS and RHS. 372 KnownOne &= KnownOne2; 373 KnownZero &= KnownZero2; 374 break; 375 case ISD::SHL: 376 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 377 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 378 KnownZero, KnownOne, TLO, Depth+1)) 379 return true; 380 KnownZero <<= SA->getValue(); 381 KnownOne <<= SA->getValue(); 382 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 383 } 384 break; 385 case ISD::SRL: 386 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 387 MVT::ValueType VT = Op.getValueType(); 388 unsigned ShAmt = SA->getValue(); 389 390 // Compute the new bits that are at the top now. 391 uint64_t HighBits = (1ULL << ShAmt)-1; 392 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 393 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 394 395 if (SimplifyDemandedBits(Op.getOperand(0), 396 (DemandedMask << ShAmt) & TypeMask, 397 KnownZero, KnownOne, TLO, Depth+1)) 398 return true; 399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 400 KnownZero &= TypeMask; 401 KnownOne &= TypeMask; 402 KnownZero >>= ShAmt; 403 KnownOne >>= ShAmt; 404 KnownZero |= HighBits; // high bits known zero. 405 } 406 break; 407 case ISD::SRA: 408 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 409 MVT::ValueType VT = Op.getValueType(); 410 unsigned ShAmt = SA->getValue(); 411 412 // Compute the new bits that are at the top now. 413 uint64_t HighBits = (1ULL << ShAmt)-1; 414 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 415 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 416 417 if (SimplifyDemandedBits(Op.getOperand(0), 418 (DemandedMask << ShAmt) & TypeMask, 419 KnownZero, KnownOne, TLO, Depth+1)) 420 return true; 421 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 422 KnownZero &= TypeMask; 423 KnownOne &= TypeMask; 424 KnownZero >>= SA->getValue(); 425 KnownOne >>= SA->getValue(); 426 427 // Handle the sign bits. 428 uint64_t SignBit = MVT::getIntVTSignBit(VT); 429 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 430 431 // If the input sign bit is known to be zero, or if none of the top bits 432 // are demanded, turn this into an unsigned shift right. 433 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 434 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 435 Op.getOperand(1))); 436 } else if (KnownOne & SignBit) { // New bits are known one. 437 KnownOne |= HighBits; 438 } 439 } 440 break; 441 case ISD::SIGN_EXTEND_INREG: { 442 MVT::ValueType VT = Op.getValueType(); 443 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 444 445 // Sign extension. Compute the demanded bits in the result that are not 446 // present in the input. 447 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 448 449 // If none of the extended bits are demanded, eliminate the sextinreg. 450 if (NewBits == 0) 451 return TLO.CombineTo(Op, Op.getOperand(0)); 452 453 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 454 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 455 456 // Since the sign extended bits are demanded, we know that the sign 457 // bit is demanded. 458 InputDemandedBits |= InSignBit; 459 460 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 461 KnownZero, KnownOne, TLO, Depth+1)) 462 return true; 463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 464 465 // If the sign bit of the input is known set or clear, then we know the 466 // top bits of the result. 467 468 // If the input sign bit is known zero, convert this into a zero extension. 469 if (KnownZero & InSignBit) 470 return TLO.CombineTo(Op, 471 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 472 473 if (KnownOne & InSignBit) { // Input sign bit known set 474 KnownOne |= NewBits; 475 KnownZero &= ~NewBits; 476 } else { // Input sign bit unknown 477 KnownZero &= ~NewBits; 478 KnownOne &= ~NewBits; 479 } 480 break; 481 } 482 case ISD::CTTZ: 483 case ISD::CTLZ: 484 case ISD::CTPOP: { 485 MVT::ValueType VT = Op.getValueType(); 486 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 487 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 488 KnownOne = 0; 489 break; 490 } 491 case ISD::ZEXTLOAD: { 492 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 493 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 494 break; 495 } 496 case ISD::ZERO_EXTEND: { 497 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 498 499 // If none of the top bits are demanded, convert this into an any_extend. 500 uint64_t NewBits = (~InMask) & DemandedMask; 501 if (NewBits == 0) 502 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 503 Op.getValueType(), 504 Op.getOperand(0))); 505 506 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 507 KnownZero, KnownOne, TLO, Depth+1)) 508 return true; 509 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 510 KnownZero |= NewBits; 511 break; 512 } 513 case ISD::SIGN_EXTEND: { 514 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 515 uint64_t InMask = MVT::getIntVTBitMask(InVT); 516 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 517 uint64_t NewBits = (~InMask) & DemandedMask; 518 519 // If none of the top bits are demanded, convert this into an any_extend. 520 if (NewBits == 0) 521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 522 Op.getOperand(0))); 523 524 // Since some of the sign extended bits are demanded, we know that the sign 525 // bit is demanded. 526 uint64_t InDemandedBits = DemandedMask & InMask; 527 InDemandedBits |= InSignBit; 528 529 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 530 KnownOne, TLO, Depth+1)) 531 return true; 532 533 // If the sign bit is known zero, convert this to a zero extend. 534 if (KnownZero & InSignBit) 535 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 536 Op.getValueType(), 537 Op.getOperand(0))); 538 539 // If the sign bit is known one, the top bits match. 540 if (KnownOne & InSignBit) { 541 KnownOne |= NewBits; 542 KnownZero &= ~NewBits; 543 } else { // Otherwise, top bits aren't known. 544 KnownOne &= ~NewBits; 545 KnownZero &= ~NewBits; 546 } 547 break; 548 } 549 case ISD::ANY_EXTEND: { 550 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 551 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 552 KnownZero, KnownOne, TLO, Depth+1)) 553 return true; 554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 555 break; 556 } 557 case ISD::AssertZext: { 558 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 559 uint64_t InMask = MVT::getIntVTBitMask(VT); 560 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 561 KnownZero, KnownOne, TLO, Depth+1)) 562 return true; 563 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 564 KnownZero |= ~InMask & DemandedMask; 565 break; 566 } 567 case ISD::ADD: 568 case ISD::SUB: 569 // Just use ComputeMaskedBits to compute output bits, there are no 570 // simplifications that can be done here, and sub always demands all input 571 // bits. 572 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 573 break; 574 } 575 576 // If we know the value of all of the demanded bits, return this as a 577 // constant. 578 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 579 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 580 581 return false; 582} 583 584/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 585/// this predicate to simplify operations downstream. Mask is known to be zero 586/// for bits that V cannot have. 587bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 588 unsigned Depth) const { 589 uint64_t KnownZero, KnownOne; 590 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 592 return (KnownZero & Mask) == Mask; 593} 594 595/// ComputeMaskedBits - Determine which of the bits specified in Mask are 596/// known to be either zero or one and return them in the KnownZero/KnownOne 597/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 598/// processing. 599void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 600 uint64_t &KnownZero, uint64_t &KnownOne, 601 unsigned Depth) const { 602 KnownZero = KnownOne = 0; // Don't know anything. 603 if (Depth == 6 || Mask == 0) 604 return; // Limit search depth. 605 606 uint64_t KnownZero2, KnownOne2; 607 608 switch (Op.getOpcode()) { 609 case ISD::Constant: 610 // We know all of the bits for a constant! 611 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 612 KnownZero = ~KnownOne & Mask; 613 return; 614 case ISD::AND: 615 // If either the LHS or the RHS are Zero, the result is zero. 616 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 617 Mask &= ~KnownZero; 618 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 619 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 620 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 621 622 // Output known-1 bits are only known if set in both the LHS & RHS. 623 KnownOne &= KnownOne2; 624 // Output known-0 are known to be clear if zero in either the LHS | RHS. 625 KnownZero |= KnownZero2; 626 return; 627 case ISD::OR: 628 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 629 Mask &= ~KnownOne; 630 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 631 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 632 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 633 634 // Output known-0 bits are only known if clear in both the LHS & RHS. 635 KnownZero &= KnownZero2; 636 // Output known-1 are known to be set if set in either the LHS | RHS. 637 KnownOne |= KnownOne2; 638 return; 639 case ISD::XOR: { 640 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 641 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 642 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 643 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 644 645 // Output known-0 bits are known if clear or set in both the LHS & RHS. 646 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 647 // Output known-1 are known to be set if set in only one of the LHS, RHS. 648 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 649 KnownZero = KnownZeroOut; 650 return; 651 } 652 case ISD::SELECT: 653 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 654 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 655 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 656 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 657 658 // Only known if known in both the LHS and RHS. 659 KnownOne &= KnownOne2; 660 KnownZero &= KnownZero2; 661 return; 662 case ISD::SELECT_CC: 663 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 664 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 665 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 666 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 667 668 // Only known if known in both the LHS and RHS. 669 KnownOne &= KnownOne2; 670 KnownZero &= KnownZero2; 671 return; 672 case ISD::SETCC: 673 // If we know the result of a setcc has the top bits zero, use this info. 674 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 675 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 676 return; 677 case ISD::SHL: 678 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 679 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 680 Mask >>= SA->getValue(); 681 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 683 KnownZero <<= SA->getValue(); 684 KnownOne <<= SA->getValue(); 685 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 686 } 687 return; 688 case ISD::SRL: 689 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 690 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 691 uint64_t HighBits = (1ULL << SA->getValue())-1; 692 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 693 Mask <<= SA->getValue(); 694 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 695 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 696 KnownZero >>= SA->getValue(); 697 KnownOne >>= SA->getValue(); 698 KnownZero |= HighBits; // high bits known zero. 699 } 700 return; 701 case ISD::SRA: 702 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 703 uint64_t HighBits = (1ULL << SA->getValue())-1; 704 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 705 Mask <<= SA->getValue(); 706 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 707 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 708 KnownZero >>= SA->getValue(); 709 KnownOne >>= SA->getValue(); 710 711 // Handle the sign bits. 712 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1); 713 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 714 715 if (KnownZero & SignBit) { // New bits are known zero. 716 KnownZero |= HighBits; 717 } else if (KnownOne & SignBit) { // New bits are known one. 718 KnownOne |= HighBits; 719 } 720 } 721 return; 722 case ISD::SIGN_EXTEND_INREG: { 723 MVT::ValueType VT = Op.getValueType(); 724 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 725 726 // Sign extension. Compute the demanded bits in the result that are not 727 // present in the input. 728 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; 729 730 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 731 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); 732 733 // If the sign extended bits are demanded, we know that the sign 734 // bit is demanded. 735 if (NewBits) 736 InputDemandedBits |= InSignBit; 737 738 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 739 KnownZero, KnownOne, Depth+1); 740 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 741 742 // If the sign bit of the input is known set or clear, then we know the 743 // top bits of the result. 744 if (KnownZero & InSignBit) { // Input sign bit known clear 745 KnownZero |= NewBits; 746 KnownOne &= ~NewBits; 747 } else if (KnownOne & InSignBit) { // Input sign bit known set 748 KnownOne |= NewBits; 749 KnownZero &= ~NewBits; 750 } else { // Input sign bit unknown 751 KnownZero &= ~NewBits; 752 KnownOne &= ~NewBits; 753 } 754 return; 755 } 756 case ISD::CTTZ: 757 case ISD::CTLZ: 758 case ISD::CTPOP: { 759 MVT::ValueType VT = Op.getValueType(); 760 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 761 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 762 KnownOne = 0; 763 return; 764 } 765 case ISD::ZEXTLOAD: { 766 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 767 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; 768 return; 769 } 770 case ISD::ZERO_EXTEND: { 771 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 772 uint64_t NewBits = (~InMask) & Mask; 773 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 774 KnownOne, Depth+1); 775 KnownZero |= NewBits & Mask; 776 KnownOne &= ~NewBits; 777 return; 778 } 779 case ISD::SIGN_EXTEND: { 780 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 781 unsigned InBits = MVT::getSizeInBits(InVT); 782 uint64_t InMask = MVT::getIntVTBitMask(InVT); 783 uint64_t InSignBit = 1ULL << (InBits-1); 784 uint64_t NewBits = (~InMask) & Mask; 785 uint64_t InDemandedBits = Mask & InMask; 786 787 // If any of the sign extended bits are demanded, we know that the sign 788 // bit is demanded. 789 if (NewBits & Mask) 790 InDemandedBits |= InSignBit; 791 792 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, 793 KnownOne, Depth+1); 794 // If the sign bit is known zero or one, the top bits match. 795 if (KnownZero & InSignBit) { 796 KnownZero |= NewBits; 797 KnownOne &= ~NewBits; 798 } else if (KnownOne & InSignBit) { 799 KnownOne |= NewBits; 800 KnownZero &= ~NewBits; 801 } else { // Otherwise, top bits aren't known. 802 KnownOne &= ~NewBits; 803 KnownZero &= ~NewBits; 804 } 805 return; 806 } 807 case ISD::ANY_EXTEND: { 808 MVT::ValueType VT = Op.getOperand(0).getValueType(); 809 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), 810 KnownZero, KnownOne, Depth+1); 811 return; 812 } 813 case ISD::AssertZext: { 814 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 815 uint64_t InMask = MVT::getIntVTBitMask(VT); 816 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 817 KnownOne, Depth+1); 818 KnownZero |= (~InMask) & Mask; 819 return; 820 } 821 case ISD::ADD: { 822 // If either the LHS or the RHS are Zero, the result is zero. 823 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 824 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 825 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 826 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 827 828 // Output known-0 bits are known if clear or set in both the low clear bits 829 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 830 // low 3 bits clear. 831 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 832 CountTrailingZeros_64(~KnownZero2)); 833 834 KnownZero = (1ULL << KnownZeroOut) - 1; 835 KnownOne = 0; 836 return; 837 } 838 case ISD::SUB: { 839 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 840 if (!CLHS) return; 841 842 // We know that the top bits of C-X are clear if X contains less bits 843 // than C (i.e. no wrap-around can happen). For example, 20-X is 844 // positive if we can prove that X is >= 0 and < 16. 845 MVT::ValueType VT = CLHS->getValueType(0); 846 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear 847 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 848 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit 849 MaskV = ~MaskV & MVT::getIntVTBitMask(VT); 850 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); 851 852 // If all of the MaskV bits are known to be zero, then we know the output 853 // top bits are zero, because we now know that the output is from [0-C]. 854 if ((KnownZero & MaskV) == MaskV) { 855 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 856 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. 857 KnownOne = 0; // No one bits known. 858 } else { 859 KnownOne = KnownOne = 0; // Otherwise, nothing known. 860 } 861 } 862 return; 863 } 864 default: 865 // Allow the target to implement this method for its nodes. 866 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) 867 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 868 return; 869 } 870} 871 872/// computeMaskedBitsForTargetNode - Determine which of the bits specified 873/// in Mask are known to be either zero or one and return them in the 874/// KnownZero/KnownOne bitsets. 875void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 876 uint64_t Mask, 877 uint64_t &KnownZero, 878 uint64_t &KnownOne, 879 unsigned Depth) const { 880 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END && 881 "Should use MaskedValueIsZero if you don't know whether Op" 882 " is a target node!"); 883 KnownZero = 0; 884 KnownOne = 0; 885} 886 887SDOperand TargetLowering:: 888PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 889 // Default implementation: no optimization. 890 return SDOperand(); 891} 892 893//===----------------------------------------------------------------------===// 894// Inline Assembler Implementation Methods 895//===----------------------------------------------------------------------===// 896 897TargetLowering::ConstraintType 898TargetLowering::getConstraintType(char ConstraintLetter) const { 899 // FIXME: lots more standard ones to handle. 900 switch (ConstraintLetter) { 901 default: return C_Unknown; 902 case 'r': return C_RegisterClass; 903 case 'm': // memory 904 case 'o': // offsetable 905 case 'V': // not offsetable 906 return C_Memory; 907 case 'i': // Simple Integer or Relocatable Constant 908 case 'n': // Simple Integer 909 case 's': // Relocatable Constant 910 case 'I': // Target registers. 911 case 'J': 912 case 'K': 913 case 'L': 914 case 'M': 915 case 'N': 916 case 'O': 917 case 'P': 918 return C_Other; 919 } 920} 921 922bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 923 char ConstraintLetter) { 924 switch (ConstraintLetter) { 925 default: return false; 926 case 'i': // Simple Integer or Relocatable Constant 927 case 'n': // Simple Integer 928 case 's': // Relocatable Constant 929 return true; // FIXME: not right. 930 } 931} 932 933 934std::vector<unsigned> TargetLowering:: 935getRegClassForInlineAsmConstraint(const std::string &Constraint, 936 MVT::ValueType VT) const { 937 return std::vector<unsigned>(); 938} 939 940 941std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 942getRegForInlineAsmConstraint(const std::string &Constraint, 943 MVT::ValueType VT) const { 944 if (Constraint[0] != '{') 945 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 946 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 947 948 // Remove the braces from around the name. 949 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 950 951 // Figure out which register class contains this reg. 952 const MRegisterInfo *RI = TM.getRegisterInfo(); 953 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 954 E = RI->regclass_end(); RCI != E; ++RCI) { 955 const TargetRegisterClass *RC = *RCI; 956 957 // If none of the the value types for this register class are valid, we 958 // can't use it. For example, 64-bit reg classes on 32-bit targets. 959 bool isLegal = false; 960 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 961 I != E; ++I) { 962 if (isTypeLegal(*I)) { 963 isLegal = true; 964 break; 965 } 966 } 967 968 if (!isLegal) continue; 969 970 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 971 I != E; ++I) { 972 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 973 return std::make_pair(*I, RC); 974 } 975 } 976 977 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 978} 979