TargetLowering.cpp revision d385fd62cb43435b3ad70d789198d34bf148e579
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetData.h" 16#include "llvm/Target/TargetMachine.h" 17#include "llvm/Target/MRegisterInfo.h" 18#include "llvm/DerivedTypes.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/Support/MathExtras.h" 22using namespace llvm; 23 24/// InitLibcallNames - Set default libcall names. 25/// 26static void InitLibcallNames(const char **Names) { 27 Names[RTLIB::SHL_I32] = "__ashlsi3"; 28 Names[RTLIB::SHL_I64] = "__ashldi3"; 29 Names[RTLIB::SRL_I32] = "__lshrsi3"; 30 Names[RTLIB::SRL_I64] = "__lshrdi3"; 31 Names[RTLIB::SRA_I32] = "__ashrsi3"; 32 Names[RTLIB::SRA_I64] = "__ashrdi3"; 33 Names[RTLIB::MUL_I32] = "__mulsi3"; 34 Names[RTLIB::MUL_I64] = "__muldi3"; 35 Names[RTLIB::SDIV_I32] = "__divsi3"; 36 Names[RTLIB::SDIV_I64] = "__divdi3"; 37 Names[RTLIB::UDIV_I32] = "__udivsi3"; 38 Names[RTLIB::UDIV_I64] = "__udivdi3"; 39 Names[RTLIB::SREM_I32] = "__modsi3"; 40 Names[RTLIB::SREM_I64] = "__moddi3"; 41 Names[RTLIB::UREM_I32] = "__umodsi3"; 42 Names[RTLIB::UREM_I64] = "__umoddi3"; 43 Names[RTLIB::NEG_I32] = "__negsi2"; 44 Names[RTLIB::NEG_I64] = "__negdi2"; 45 Names[RTLIB::ADD_F32] = "__addsf3"; 46 Names[RTLIB::ADD_F64] = "__adddf3"; 47 Names[RTLIB::SUB_F32] = "__subsf3"; 48 Names[RTLIB::SUB_F64] = "__subdf3"; 49 Names[RTLIB::MUL_F32] = "__mulsf3"; 50 Names[RTLIB::MUL_F64] = "__muldf3"; 51 Names[RTLIB::DIV_F32] = "__divsf3"; 52 Names[RTLIB::DIV_F64] = "__divdf3"; 53 Names[RTLIB::REM_F32] = "fmodf"; 54 Names[RTLIB::REM_F64] = "fmod"; 55 Names[RTLIB::NEG_F32] = "__negsf2"; 56 Names[RTLIB::NEG_F64] = "__negdf2"; 57 Names[RTLIB::POWI_F32] = "__powisf2"; 58 Names[RTLIB::POWI_F64] = "__powidf2"; 59 Names[RTLIB::SQRT_F32] = "sqrtf"; 60 Names[RTLIB::SQRT_F64] = "sqrt"; 61 Names[RTLIB::SIN_F32] = "sinf"; 62 Names[RTLIB::SIN_F64] = "sin"; 63 Names[RTLIB::COS_F32] = "cosf"; 64 Names[RTLIB::COS_F64] = "cos"; 65 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 66 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 67 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 68 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 69 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 70 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 71 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 72 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 73 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 74 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 75 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 76 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 77 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 78 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 79 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 80 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 81 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 82 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 83 Names[RTLIB::OEQ_F32] = "__eqsf2"; 84 Names[RTLIB::OEQ_F64] = "__eqdf2"; 85 Names[RTLIB::UNE_F32] = "__nesf2"; 86 Names[RTLIB::UNE_F64] = "__nedf2"; 87 Names[RTLIB::OGE_F32] = "__gesf2"; 88 Names[RTLIB::OGE_F64] = "__gedf2"; 89 Names[RTLIB::OLT_F32] = "__ltsf2"; 90 Names[RTLIB::OLT_F64] = "__ltdf2"; 91 Names[RTLIB::OLE_F32] = "__lesf2"; 92 Names[RTLIB::OLE_F64] = "__ledf2"; 93 Names[RTLIB::OGT_F32] = "__gtsf2"; 94 Names[RTLIB::OGT_F64] = "__gtdf2"; 95 Names[RTLIB::UO_F32] = "__unordsf2"; 96 Names[RTLIB::UO_F64] = "__unorddf2"; 97 Names[RTLIB::O_F32] = "__unordsf2"; 98 Names[RTLIB::O_F64] = "__unorddf2"; 99} 100 101/// InitCmpLibcallCCs - Set default comparison libcall CC. 102/// 103static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 104 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 105 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 106 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 107 CCs[RTLIB::UNE_F32] = ISD::SETNE; 108 CCs[RTLIB::UNE_F64] = ISD::SETNE; 109 CCs[RTLIB::OGE_F32] = ISD::SETGE; 110 CCs[RTLIB::OGE_F64] = ISD::SETGE; 111 CCs[RTLIB::OLT_F32] = ISD::SETLT; 112 CCs[RTLIB::OLT_F64] = ISD::SETLT; 113 CCs[RTLIB::OLE_F32] = ISD::SETLE; 114 CCs[RTLIB::OLE_F64] = ISD::SETLE; 115 CCs[RTLIB::OGT_F32] = ISD::SETGT; 116 CCs[RTLIB::OGT_F64] = ISD::SETGT; 117 CCs[RTLIB::UO_F32] = ISD::SETNE; 118 CCs[RTLIB::UO_F64] = ISD::SETNE; 119 CCs[RTLIB::O_F32] = ISD::SETEQ; 120 CCs[RTLIB::O_F64] = ISD::SETEQ; 121} 122 123TargetLowering::TargetLowering(TargetMachine &tm) 124 : TM(tm), TD(TM.getTargetData()) { 125 assert(ISD::BUILTIN_OP_END <= 156 && 126 "Fixed size array in TargetLowering is not large enough!"); 127 // All operations default to being supported. 128 memset(OpActions, 0, sizeof(OpActions)); 129 memset(LoadXActions, 0, sizeof(LoadXActions)); 130 memset(&StoreXActions, 0, sizeof(StoreXActions)); 131 // Initialize all indexed load / store to expand. 132 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 133 for (unsigned IM = (unsigned)ISD::PRE_INC; 134 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 135 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 136 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 137 } 138 } 139 140 IsLittleEndian = TD->isLittleEndian(); 141 UsesGlobalOffsetTable = false; 142 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 143 ShiftAmtHandling = Undefined; 144 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 145 memset(TargetDAGCombineArray, 0, 146 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0])); 147 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 148 allowUnalignedMemoryAccesses = false; 149 UseUnderscoreSetJmp = false; 150 UseUnderscoreLongJmp = false; 151 IntDivIsCheap = false; 152 Pow2DivIsCheap = false; 153 StackPointerRegisterToSaveRestore = 0; 154 SchedPreferenceInfo = SchedulingForLatency; 155 JumpBufSize = 0; 156 JumpBufAlignment = 0; 157 158 InitLibcallNames(LibcallRoutineNames); 159 InitCmpLibcallCCs(CmpLibcallCCs); 160} 161 162TargetLowering::~TargetLowering() {} 163 164/// setValueTypeAction - Set the action for a particular value type. This 165/// assumes an action has not already been set for this value type. 166static void SetValueTypeAction(MVT::ValueType VT, 167 TargetLowering::LegalizeAction Action, 168 TargetLowering &TLI, 169 MVT::ValueType *TransformToType, 170 TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 171 ValueTypeActions.setTypeAction(VT, Action); 172 if (Action == TargetLowering::Promote) { 173 MVT::ValueType PromoteTo; 174 if (VT == MVT::f32) 175 PromoteTo = MVT::f64; 176 else { 177 unsigned LargerReg = VT+1; 178 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 179 ++LargerReg; 180 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 181 "Nothing to promote to??"); 182 } 183 PromoteTo = (MVT::ValueType)LargerReg; 184 } 185 186 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 187 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 188 "Can only promote from int->int or fp->fp!"); 189 assert(VT < PromoteTo && "Must promote to a larger type!"); 190 TransformToType[VT] = PromoteTo; 191 } else if (Action == TargetLowering::Expand) { 192 // f32 and f64 is each expanded to corresponding integer type of same size. 193 if (VT == MVT::f32) 194 TransformToType[VT] = MVT::i32; 195 else if (VT == MVT::f64) 196 TransformToType[VT] = MVT::i64; 197 else { 198 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 199 "Cannot expand this type: target must support SOME integer reg!"); 200 // Expand to the next smaller integer type! 201 TransformToType[VT] = (MVT::ValueType)(VT-1); 202 } 203 } 204} 205 206 207/// computeRegisterProperties - Once all of the register classes are added, 208/// this allows us to compute derived properties we expose. 209void TargetLowering::computeRegisterProperties() { 210 assert(MVT::LAST_VALUETYPE <= 32 && 211 "Too many value types for ValueTypeActions to hold!"); 212 213 // Everything defaults to one. 214 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 215 NumElementsForVT[i] = 1; 216 217 // Find the largest integer register class. 218 unsigned LargestIntReg = MVT::i128; 219 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 220 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 221 222 // Every integer value type larger than this largest register takes twice as 223 // many registers to represent as the previous ValueType. 224 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 225 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 226 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 227 228 // Inspect all of the ValueType's possible, deciding how to process them. 229 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 230 // If we are expanding this type, expand it! 231 if (getNumElements((MVT::ValueType)IntReg) != 1) 232 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 233 ValueTypeActions); 234 else if (!isTypeLegal((MVT::ValueType)IntReg)) 235 // Otherwise, if we don't have native support, we must promote to a 236 // larger type. 237 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 238 TransformToType, ValueTypeActions); 239 else 240 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 241 242 // If the target does not have native F64 support, expand it to I64. We will 243 // be generating soft float library calls. If the target does not have native 244 // support for F32, promote it to F64 if it is legal. Otherwise, expand it to 245 // I32. 246 if (isTypeLegal(MVT::f64)) 247 TransformToType[MVT::f64] = MVT::f64; 248 else { 249 NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64]; 250 SetValueTypeAction(MVT::f64, Expand, *this, TransformToType, 251 ValueTypeActions); 252 } 253 if (isTypeLegal(MVT::f32)) 254 TransformToType[MVT::f32] = MVT::f32; 255 else if (isTypeLegal(MVT::f64)) 256 SetValueTypeAction(MVT::f32, Promote, *this, TransformToType, 257 ValueTypeActions); 258 else { 259 NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32]; 260 SetValueTypeAction(MVT::f32, Expand, *this, TransformToType, 261 ValueTypeActions); 262 } 263 264 // Set MVT::Vector to always be Expanded 265 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 266 ValueTypeActions); 267 268 // Loop over all of the legal vector value types, specifying an identity type 269 // transformation. 270 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 271 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 272 if (isTypeLegal((MVT::ValueType)i)) 273 TransformToType[i] = (MVT::ValueType)i; 274 } 275} 276 277const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 278 return NULL; 279} 280 281/// getPackedTypeBreakdown - Packed types are broken down into some number of 282/// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 283/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 284/// 285/// This method returns the number and type of the resultant breakdown. 286/// 287unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 288 MVT::ValueType &PTyElementVT, 289 MVT::ValueType &PTyLegalElementVT) const { 290 // Figure out the right, legal destination reg to copy into. 291 unsigned NumElts = PTy->getNumElements(); 292 MVT::ValueType EltTy = getValueType(PTy->getElementType()); 293 294 unsigned NumVectorRegs = 1; 295 296 // Divide the input until we get to a supported size. This will always 297 // end with a scalar if the target doesn't support vectors. 298 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) { 299 NumElts >>= 1; 300 NumVectorRegs <<= 1; 301 } 302 303 MVT::ValueType VT; 304 if (NumElts == 1) { 305 VT = EltTy; 306 } else { 307 VT = getVectorType(EltTy, NumElts); 308 } 309 PTyElementVT = VT; 310 311 MVT::ValueType DestVT = getTypeToTransformTo(VT); 312 PTyLegalElementVT = DestVT; 313 if (DestVT < VT) { 314 // Value is expanded, e.g. i64 -> i16. 315 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT)); 316 } else { 317 // Otherwise, promotion or legal types use the same number of registers as 318 // the vector decimated to the appropriate level. 319 return NumVectorRegs; 320 } 321 322 return 1; 323} 324 325//===----------------------------------------------------------------------===// 326// Optimization Methods 327//===----------------------------------------------------------------------===// 328 329/// ShrinkDemandedConstant - Check to see if the specified operand of the 330/// specified instruction is a constant integer. If so, check to see if there 331/// are any bits set in the constant that are not demanded. If so, shrink the 332/// constant and return true. 333bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 334 uint64_t Demanded) { 335 // FIXME: ISD::SELECT, ISD::SELECT_CC 336 switch(Op.getOpcode()) { 337 default: break; 338 case ISD::AND: 339 case ISD::OR: 340 case ISD::XOR: 341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 342 if ((~Demanded & C->getValue()) != 0) { 343 MVT::ValueType VT = Op.getValueType(); 344 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 345 DAG.getConstant(Demanded & C->getValue(), 346 VT)); 347 return CombineTo(Op, New); 348 } 349 break; 350 } 351 return false; 352} 353 354/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 355/// DemandedMask bits of the result of Op are ever used downstream. If we can 356/// use this information to simplify Op, create a new simplified DAG node and 357/// return true, returning the original and new nodes in Old and New. Otherwise, 358/// analyze the expression and return a mask of KnownOne and KnownZero bits for 359/// the expression (used to simplify the caller). The KnownZero/One bits may 360/// only be accurate for those bits in the DemandedMask. 361bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 362 uint64_t &KnownZero, 363 uint64_t &KnownOne, 364 TargetLoweringOpt &TLO, 365 unsigned Depth) const { 366 KnownZero = KnownOne = 0; // Don't know anything. 367 // Other users may use these bits. 368 if (!Op.Val->hasOneUse()) { 369 if (Depth != 0) { 370 // If not at the root, Just compute the KnownZero/KnownOne bits to 371 // simplify things downstream. 372 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 373 return false; 374 } 375 // If this is the root being simplified, allow it to have multiple uses, 376 // just set the DemandedMask to all bits. 377 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 378 } else if (DemandedMask == 0) { 379 // Not demanding any bits from Op. 380 if (Op.getOpcode() != ISD::UNDEF) 381 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 382 return false; 383 } else if (Depth == 6) { // Limit search depth. 384 return false; 385 } 386 387 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 388 switch (Op.getOpcode()) { 389 case ISD::Constant: 390 // We know all of the bits for a constant! 391 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 392 KnownZero = ~KnownOne & DemandedMask; 393 return false; // Don't fall through, will infinitely loop. 394 case ISD::AND: 395 // If the RHS is a constant, check to see if the LHS would be zero without 396 // using the bits from the RHS. Below, we use knowledge about the RHS to 397 // simplify the LHS, here we're using information from the LHS to simplify 398 // the RHS. 399 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 400 uint64_t LHSZero, LHSOne; 401 ComputeMaskedBits(Op.getOperand(0), DemandedMask, 402 LHSZero, LHSOne, Depth+1); 403 // If the LHS already has zeros where RHSC does, this and is dead. 404 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 405 return TLO.CombineTo(Op, Op.getOperand(0)); 406 // If any of the set bits in the RHS are known zero on the LHS, shrink 407 // the constant. 408 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 409 return true; 410 } 411 412 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 413 KnownOne, TLO, Depth+1)) 414 return true; 415 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 416 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 417 KnownZero2, KnownOne2, TLO, Depth+1)) 418 return true; 419 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 420 421 // If all of the demanded bits are known one on one side, return the other. 422 // These bits cannot contribute to the result of the 'and'. 423 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 424 return TLO.CombineTo(Op, Op.getOperand(0)); 425 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 426 return TLO.CombineTo(Op, Op.getOperand(1)); 427 // If all of the demanded bits in the inputs are known zeros, return zero. 428 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 429 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 430 // If the RHS is a constant, see if we can simplify it. 431 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 432 return true; 433 434 // Output known-1 bits are only known if set in both the LHS & RHS. 435 KnownOne &= KnownOne2; 436 // Output known-0 are known to be clear if zero in either the LHS | RHS. 437 KnownZero |= KnownZero2; 438 break; 439 case ISD::OR: 440 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 441 KnownOne, TLO, Depth+1)) 442 return true; 443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 444 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 445 KnownZero2, KnownOne2, TLO, Depth+1)) 446 return true; 447 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 448 449 // If all of the demanded bits are known zero on one side, return the other. 450 // These bits cannot contribute to the result of the 'or'. 451 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 452 return TLO.CombineTo(Op, Op.getOperand(0)); 453 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 454 return TLO.CombineTo(Op, Op.getOperand(1)); 455 // If all of the potentially set bits on one side are known to be set on 456 // the other side, just use the 'other' side. 457 if ((DemandedMask & (~KnownZero) & KnownOne2) == 458 (DemandedMask & (~KnownZero))) 459 return TLO.CombineTo(Op, Op.getOperand(0)); 460 if ((DemandedMask & (~KnownZero2) & KnownOne) == 461 (DemandedMask & (~KnownZero2))) 462 return TLO.CombineTo(Op, Op.getOperand(1)); 463 // If the RHS is a constant, see if we can simplify it. 464 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 465 return true; 466 467 // Output known-0 bits are only known if clear in both the LHS & RHS. 468 KnownZero &= KnownZero2; 469 // Output known-1 are known to be set if set in either the LHS | RHS. 470 KnownOne |= KnownOne2; 471 break; 472 case ISD::XOR: 473 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 474 KnownOne, TLO, Depth+1)) 475 return true; 476 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 477 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 478 KnownOne2, TLO, Depth+1)) 479 return true; 480 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 481 482 // If all of the demanded bits are known zero on one side, return the other. 483 // These bits cannot contribute to the result of the 'xor'. 484 if ((DemandedMask & KnownZero) == DemandedMask) 485 return TLO.CombineTo(Op, Op.getOperand(0)); 486 if ((DemandedMask & KnownZero2) == DemandedMask) 487 return TLO.CombineTo(Op, Op.getOperand(1)); 488 489 // If all of the unknown bits are known to be zero on one side or the other 490 // (but not both) turn this into an *inclusive* or. 491 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 492 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 493 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 494 Op.getOperand(0), 495 Op.getOperand(1))); 496 497 // Output known-0 bits are known if clear or set in both the LHS & RHS. 498 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 499 // Output known-1 are known to be set if set in only one of the LHS, RHS. 500 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 501 502 // If all of the demanded bits on one side are known, and all of the set 503 // bits on that side are also known to be set on the other side, turn this 504 // into an AND, as we know the bits will be cleared. 505 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 506 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 507 if ((KnownOne & KnownOne2) == KnownOne) { 508 MVT::ValueType VT = Op.getValueType(); 509 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 510 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 511 ANDC)); 512 } 513 } 514 515 // If the RHS is a constant, see if we can simplify it. 516 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 517 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 518 return true; 519 520 KnownZero = KnownZeroOut; 521 KnownOne = KnownOneOut; 522 break; 523 case ISD::SETCC: 524 // If we know the result of a setcc has the top bits zero, use this info. 525 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 526 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 527 break; 528 case ISD::SELECT: 529 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 530 KnownOne, TLO, Depth+1)) 531 return true; 532 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 533 KnownOne2, TLO, Depth+1)) 534 return true; 535 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 536 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 537 538 // If the operands are constants, see if we can simplify them. 539 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 540 return true; 541 542 // Only known if known in both the LHS and RHS. 543 KnownOne &= KnownOne2; 544 KnownZero &= KnownZero2; 545 break; 546 case ISD::SELECT_CC: 547 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 548 KnownOne, TLO, Depth+1)) 549 return true; 550 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 551 KnownOne2, TLO, Depth+1)) 552 return true; 553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 554 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 555 556 // If the operands are constants, see if we can simplify them. 557 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 558 return true; 559 560 // Only known if known in both the LHS and RHS. 561 KnownOne &= KnownOne2; 562 KnownZero &= KnownZero2; 563 break; 564 case ISD::SHL: 565 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 566 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 567 KnownZero, KnownOne, TLO, Depth+1)) 568 return true; 569 KnownZero <<= SA->getValue(); 570 KnownOne <<= SA->getValue(); 571 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 572 } 573 break; 574 case ISD::SRL: 575 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 576 MVT::ValueType VT = Op.getValueType(); 577 unsigned ShAmt = SA->getValue(); 578 579 // Compute the new bits that are at the top now. 580 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 581 if (SimplifyDemandedBits(Op.getOperand(0), 582 (DemandedMask << ShAmt) & TypeMask, 583 KnownZero, KnownOne, TLO, Depth+1)) 584 return true; 585 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 586 KnownZero &= TypeMask; 587 KnownOne &= TypeMask; 588 KnownZero >>= ShAmt; 589 KnownOne >>= ShAmt; 590 591 uint64_t HighBits = (1ULL << ShAmt)-1; 592 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 593 KnownZero |= HighBits; // High bits known zero. 594 } 595 break; 596 case ISD::SRA: 597 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 598 MVT::ValueType VT = Op.getValueType(); 599 unsigned ShAmt = SA->getValue(); 600 601 // Compute the new bits that are at the top now. 602 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 603 604 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 605 606 // If any of the demanded bits are produced by the sign extension, we also 607 // demand the input sign bit. 608 uint64_t HighBits = (1ULL << ShAmt)-1; 609 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 610 if (HighBits & DemandedMask) 611 InDemandedMask |= MVT::getIntVTSignBit(VT); 612 613 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 614 KnownZero, KnownOne, TLO, Depth+1)) 615 return true; 616 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 617 KnownZero &= TypeMask; 618 KnownOne &= TypeMask; 619 KnownZero >>= ShAmt; 620 KnownOne >>= ShAmt; 621 622 // Handle the sign bits. 623 uint64_t SignBit = MVT::getIntVTSignBit(VT); 624 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 625 626 // If the input sign bit is known to be zero, or if none of the top bits 627 // are demanded, turn this into an unsigned shift right. 628 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 629 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 630 Op.getOperand(1))); 631 } else if (KnownOne & SignBit) { // New bits are known one. 632 KnownOne |= HighBits; 633 } 634 } 635 break; 636 case ISD::SIGN_EXTEND_INREG: { 637 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 638 639 // Sign extension. Compute the demanded bits in the result that are not 640 // present in the input. 641 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 642 643 // If none of the extended bits are demanded, eliminate the sextinreg. 644 if (NewBits == 0) 645 return TLO.CombineTo(Op, Op.getOperand(0)); 646 647 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 648 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 649 650 // Since the sign extended bits are demanded, we know that the sign 651 // bit is demanded. 652 InputDemandedBits |= InSignBit; 653 654 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 655 KnownZero, KnownOne, TLO, Depth+1)) 656 return true; 657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 658 659 // If the sign bit of the input is known set or clear, then we know the 660 // top bits of the result. 661 662 // If the input sign bit is known zero, convert this into a zero extension. 663 if (KnownZero & InSignBit) 664 return TLO.CombineTo(Op, 665 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 666 667 if (KnownOne & InSignBit) { // Input sign bit known set 668 KnownOne |= NewBits; 669 KnownZero &= ~NewBits; 670 } else { // Input sign bit unknown 671 KnownZero &= ~NewBits; 672 KnownOne &= ~NewBits; 673 } 674 break; 675 } 676 case ISD::CTTZ: 677 case ISD::CTLZ: 678 case ISD::CTPOP: { 679 MVT::ValueType VT = Op.getValueType(); 680 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 681 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 682 KnownOne = 0; 683 break; 684 } 685 case ISD::LOAD: { 686 if (ISD::isZEXTLoad(Op.Val)) { 687 LoadSDNode *LD = cast<LoadSDNode>(Op); 688 MVT::ValueType VT = LD->getLoadedVT(); 689 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 690 } 691 break; 692 } 693 case ISD::ZERO_EXTEND: { 694 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 695 696 // If none of the top bits are demanded, convert this into an any_extend. 697 uint64_t NewBits = (~InMask) & DemandedMask; 698 if (NewBits == 0) 699 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 700 Op.getValueType(), 701 Op.getOperand(0))); 702 703 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 704 KnownZero, KnownOne, TLO, Depth+1)) 705 return true; 706 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 707 KnownZero |= NewBits; 708 break; 709 } 710 case ISD::SIGN_EXTEND: { 711 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 712 uint64_t InMask = MVT::getIntVTBitMask(InVT); 713 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 714 uint64_t NewBits = (~InMask) & DemandedMask; 715 716 // If none of the top bits are demanded, convert this into an any_extend. 717 if (NewBits == 0) 718 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 719 Op.getOperand(0))); 720 721 // Since some of the sign extended bits are demanded, we know that the sign 722 // bit is demanded. 723 uint64_t InDemandedBits = DemandedMask & InMask; 724 InDemandedBits |= InSignBit; 725 726 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 727 KnownOne, TLO, Depth+1)) 728 return true; 729 730 // If the sign bit is known zero, convert this to a zero extend. 731 if (KnownZero & InSignBit) 732 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 733 Op.getValueType(), 734 Op.getOperand(0))); 735 736 // If the sign bit is known one, the top bits match. 737 if (KnownOne & InSignBit) { 738 KnownOne |= NewBits; 739 KnownZero &= ~NewBits; 740 } else { // Otherwise, top bits aren't known. 741 KnownOne &= ~NewBits; 742 KnownZero &= ~NewBits; 743 } 744 break; 745 } 746 case ISD::ANY_EXTEND: { 747 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 748 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 749 KnownZero, KnownOne, TLO, Depth+1)) 750 return true; 751 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 752 break; 753 } 754 case ISD::TRUNCATE: { 755 // Simplify the input, using demanded bit information, and compute the known 756 // zero/one bits live out. 757 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 758 KnownZero, KnownOne, TLO, Depth+1)) 759 return true; 760 761 // If the input is only used by this truncate, see if we can shrink it based 762 // on the known demanded bits. 763 if (Op.getOperand(0).Val->hasOneUse()) { 764 SDOperand In = Op.getOperand(0); 765 switch (In.getOpcode()) { 766 default: break; 767 case ISD::SRL: 768 // Shrink SRL by a constant if none of the high bits shifted in are 769 // demanded. 770 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 771 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 772 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 773 HighBits >>= ShAmt->getValue(); 774 775 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 776 (DemandedMask & HighBits) == 0) { 777 // None of the shifted in bits are needed. Add a truncate of the 778 // shift input, then shift it. 779 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 780 Op.getValueType(), 781 In.getOperand(0)); 782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 783 NewTrunc, In.getOperand(1))); 784 } 785 } 786 break; 787 } 788 } 789 790 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 791 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 792 KnownZero &= OutMask; 793 KnownOne &= OutMask; 794 break; 795 } 796 case ISD::AssertZext: { 797 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 798 uint64_t InMask = MVT::getIntVTBitMask(VT); 799 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 800 KnownZero, KnownOne, TLO, Depth+1)) 801 return true; 802 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 803 KnownZero |= ~InMask & DemandedMask; 804 break; 805 } 806 case ISD::ADD: 807 case ISD::SUB: 808 case ISD::INTRINSIC_WO_CHAIN: 809 case ISD::INTRINSIC_W_CHAIN: 810 case ISD::INTRINSIC_VOID: 811 // Just use ComputeMaskedBits to compute output bits. 812 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 813 break; 814 } 815 816 // If we know the value of all of the demanded bits, return this as a 817 // constant. 818 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 819 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 820 821 return false; 822} 823 824/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 825/// this predicate to simplify operations downstream. Mask is known to be zero 826/// for bits that V cannot have. 827bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 828 unsigned Depth) const { 829 uint64_t KnownZero, KnownOne; 830 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 831 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 832 return (KnownZero & Mask) == Mask; 833} 834 835/// ComputeMaskedBits - Determine which of the bits specified in Mask are 836/// known to be either zero or one and return them in the KnownZero/KnownOne 837/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 838/// processing. 839void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 840 uint64_t &KnownZero, uint64_t &KnownOne, 841 unsigned Depth) const { 842 KnownZero = KnownOne = 0; // Don't know anything. 843 if (Depth == 6 || Mask == 0) 844 return; // Limit search depth. 845 846 uint64_t KnownZero2, KnownOne2; 847 848 switch (Op.getOpcode()) { 849 case ISD::Constant: 850 // We know all of the bits for a constant! 851 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 852 KnownZero = ~KnownOne & Mask; 853 return; 854 case ISD::AND: 855 // If either the LHS or the RHS are Zero, the result is zero. 856 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 857 Mask &= ~KnownZero; 858 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 859 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 860 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 861 862 // Output known-1 bits are only known if set in both the LHS & RHS. 863 KnownOne &= KnownOne2; 864 // Output known-0 are known to be clear if zero in either the LHS | RHS. 865 KnownZero |= KnownZero2; 866 return; 867 case ISD::OR: 868 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 869 Mask &= ~KnownOne; 870 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 871 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 872 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 873 874 // Output known-0 bits are only known if clear in both the LHS & RHS. 875 KnownZero &= KnownZero2; 876 // Output known-1 are known to be set if set in either the LHS | RHS. 877 KnownOne |= KnownOne2; 878 return; 879 case ISD::XOR: { 880 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 881 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 882 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 883 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 884 885 // Output known-0 bits are known if clear or set in both the LHS & RHS. 886 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 887 // Output known-1 are known to be set if set in only one of the LHS, RHS. 888 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 889 KnownZero = KnownZeroOut; 890 return; 891 } 892 case ISD::SELECT: 893 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 894 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 895 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 896 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 897 898 // Only known if known in both the LHS and RHS. 899 KnownOne &= KnownOne2; 900 KnownZero &= KnownZero2; 901 return; 902 case ISD::SELECT_CC: 903 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 904 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 905 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 906 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 907 908 // Only known if known in both the LHS and RHS. 909 KnownOne &= KnownOne2; 910 KnownZero &= KnownZero2; 911 return; 912 case ISD::SETCC: 913 // If we know the result of a setcc has the top bits zero, use this info. 914 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 915 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 916 return; 917 case ISD::SHL: 918 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 919 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 920 ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(), 921 KnownZero, KnownOne, Depth+1); 922 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 923 KnownZero <<= SA->getValue(); 924 KnownOne <<= SA->getValue(); 925 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 926 } 927 return; 928 case ISD::SRL: 929 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 930 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 931 MVT::ValueType VT = Op.getValueType(); 932 unsigned ShAmt = SA->getValue(); 933 934 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 935 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask, 936 KnownZero, KnownOne, Depth+1); 937 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 938 KnownZero &= TypeMask; 939 KnownOne &= TypeMask; 940 KnownZero >>= ShAmt; 941 KnownOne >>= ShAmt; 942 943 uint64_t HighBits = (1ULL << ShAmt)-1; 944 HighBits <<= MVT::getSizeInBits(VT)-ShAmt; 945 KnownZero |= HighBits; // High bits known zero. 946 } 947 return; 948 case ISD::SRA: 949 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 950 MVT::ValueType VT = Op.getValueType(); 951 unsigned ShAmt = SA->getValue(); 952 953 // Compute the new bits that are at the top now. 954 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 955 956 uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask; 957 // If any of the demanded bits are produced by the sign extension, we also 958 // demand the input sign bit. 959 uint64_t HighBits = (1ULL << ShAmt)-1; 960 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 961 if (HighBits & Mask) 962 InDemandedMask |= MVT::getIntVTSignBit(VT); 963 964 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 965 Depth+1); 966 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 967 KnownZero &= TypeMask; 968 KnownOne &= TypeMask; 969 KnownZero >>= ShAmt; 970 KnownOne >>= ShAmt; 971 972 // Handle the sign bits. 973 uint64_t SignBit = MVT::getIntVTSignBit(VT); 974 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 975 976 if (KnownZero & SignBit) { 977 KnownZero |= HighBits; // New bits are known zero. 978 } else if (KnownOne & SignBit) { 979 KnownOne |= HighBits; // New bits are known one. 980 } 981 } 982 return; 983 case ISD::SIGN_EXTEND_INREG: { 984 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 985 986 // Sign extension. Compute the demanded bits in the result that are not 987 // present in the input. 988 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; 989 990 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 991 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); 992 993 // If the sign extended bits are demanded, we know that the sign 994 // bit is demanded. 995 if (NewBits) 996 InputDemandedBits |= InSignBit; 997 998 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 999 KnownZero, KnownOne, Depth+1); 1000 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1001 1002 // If the sign bit of the input is known set or clear, then we know the 1003 // top bits of the result. 1004 if (KnownZero & InSignBit) { // Input sign bit known clear 1005 KnownZero |= NewBits; 1006 KnownOne &= ~NewBits; 1007 } else if (KnownOne & InSignBit) { // Input sign bit known set 1008 KnownOne |= NewBits; 1009 KnownZero &= ~NewBits; 1010 } else { // Input sign bit unknown 1011 KnownZero &= ~NewBits; 1012 KnownOne &= ~NewBits; 1013 } 1014 return; 1015 } 1016 case ISD::CTTZ: 1017 case ISD::CTLZ: 1018 case ISD::CTPOP: { 1019 MVT::ValueType VT = Op.getValueType(); 1020 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 1021 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 1022 KnownOne = 0; 1023 return; 1024 } 1025 case ISD::LOAD: { 1026 if (ISD::isZEXTLoad(Op.Val)) { 1027 LoadSDNode *LD = cast<LoadSDNode>(Op); 1028 MVT::ValueType VT = LD->getLoadedVT(); 1029 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; 1030 } 1031 return; 1032 } 1033 case ISD::ZERO_EXTEND: { 1034 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 1035 uint64_t NewBits = (~InMask) & Mask; 1036 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1037 KnownOne, Depth+1); 1038 KnownZero |= NewBits & Mask; 1039 KnownOne &= ~NewBits; 1040 return; 1041 } 1042 case ISD::SIGN_EXTEND: { 1043 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 1044 unsigned InBits = MVT::getSizeInBits(InVT); 1045 uint64_t InMask = MVT::getIntVTBitMask(InVT); 1046 uint64_t InSignBit = 1ULL << (InBits-1); 1047 uint64_t NewBits = (~InMask) & Mask; 1048 uint64_t InDemandedBits = Mask & InMask; 1049 1050 // If any of the sign extended bits are demanded, we know that the sign 1051 // bit is demanded. 1052 if (NewBits & Mask) 1053 InDemandedBits |= InSignBit; 1054 1055 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1056 KnownOne, Depth+1); 1057 // If the sign bit is known zero or one, the top bits match. 1058 if (KnownZero & InSignBit) { 1059 KnownZero |= NewBits; 1060 KnownOne &= ~NewBits; 1061 } else if (KnownOne & InSignBit) { 1062 KnownOne |= NewBits; 1063 KnownZero &= ~NewBits; 1064 } else { // Otherwise, top bits aren't known. 1065 KnownOne &= ~NewBits; 1066 KnownZero &= ~NewBits; 1067 } 1068 return; 1069 } 1070 case ISD::ANY_EXTEND: { 1071 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1072 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), 1073 KnownZero, KnownOne, Depth+1); 1074 return; 1075 } 1076 case ISD::TRUNCATE: { 1077 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1078 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1079 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 1080 KnownZero &= OutMask; 1081 KnownOne &= OutMask; 1082 break; 1083 } 1084 case ISD::AssertZext: { 1085 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1086 uint64_t InMask = MVT::getIntVTBitMask(VT); 1087 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1088 KnownOne, Depth+1); 1089 KnownZero |= (~InMask) & Mask; 1090 return; 1091 } 1092 case ISD::ADD: { 1093 // If either the LHS or the RHS are Zero, the result is zero. 1094 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1095 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1096 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1097 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1098 1099 // Output known-0 bits are known if clear or set in both the low clear bits 1100 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1101 // low 3 bits clear. 1102 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 1103 CountTrailingZeros_64(~KnownZero2)); 1104 1105 KnownZero = (1ULL << KnownZeroOut) - 1; 1106 KnownOne = 0; 1107 return; 1108 } 1109 case ISD::SUB: { 1110 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1111 if (!CLHS) return; 1112 1113 // We know that the top bits of C-X are clear if X contains less bits 1114 // than C (i.e. no wrap-around can happen). For example, 20-X is 1115 // positive if we can prove that X is >= 0 and < 16. 1116 MVT::ValueType VT = CLHS->getValueType(0); 1117 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear 1118 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 1119 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit 1120 MaskV = ~MaskV & MVT::getIntVTBitMask(VT); 1121 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); 1122 1123 // If all of the MaskV bits are known to be zero, then we know the output 1124 // top bits are zero, because we now know that the output is from [0-C]. 1125 if ((KnownZero & MaskV) == MaskV) { 1126 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 1127 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. 1128 KnownOne = 0; // No one bits known. 1129 } else { 1130 KnownZero = KnownOne = 0; // Otherwise, nothing known. 1131 } 1132 } 1133 return; 1134 } 1135 default: 1136 // Allow the target to implement this method for its nodes. 1137 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1138 case ISD::INTRINSIC_WO_CHAIN: 1139 case ISD::INTRINSIC_W_CHAIN: 1140 case ISD::INTRINSIC_VOID: 1141 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 1142 } 1143 return; 1144 } 1145} 1146 1147/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1148/// in Mask are known to be either zero or one and return them in the 1149/// KnownZero/KnownOne bitsets. 1150void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1151 uint64_t Mask, 1152 uint64_t &KnownZero, 1153 uint64_t &KnownOne, 1154 unsigned Depth) const { 1155 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1156 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1157 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1158 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1159 "Should use MaskedValueIsZero if you don't know whether Op" 1160 " is a target node!"); 1161 KnownZero = 0; 1162 KnownOne = 0; 1163} 1164 1165/// ComputeNumSignBits - Return the number of times the sign bit of the 1166/// register is replicated into the other bits. We know that at least 1 bit 1167/// is always equal to the sign bit (itself), but other cases can give us 1168/// information. For example, immediately after an "SRA X, 2", we know that 1169/// the top 3 bits are all equal to each other, so we return 3. 1170unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ 1171 MVT::ValueType VT = Op.getValueType(); 1172 assert(MVT::isInteger(VT) && "Invalid VT!"); 1173 unsigned VTBits = MVT::getSizeInBits(VT); 1174 unsigned Tmp, Tmp2; 1175 1176 if (Depth == 6) 1177 return 1; // Limit search depth. 1178 1179 switch (Op.getOpcode()) { 1180 default: break; 1181 case ISD::AssertSext: 1182 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1183 return VTBits-Tmp+1; 1184 case ISD::AssertZext: 1185 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1186 return VTBits-Tmp; 1187 1188 case ISD::Constant: { 1189 uint64_t Val = cast<ConstantSDNode>(Op)->getValue(); 1190 // If negative, invert the bits, then look at it. 1191 if (Val & MVT::getIntVTSignBit(VT)) 1192 Val = ~Val; 1193 1194 // Shift the bits so they are the leading bits in the int64_t. 1195 Val <<= 64-VTBits; 1196 1197 // Return # leading zeros. We use 'min' here in case Val was zero before 1198 // shifting. We don't want to return '64' as for an i32 "0". 1199 return std::min(VTBits, CountLeadingZeros_64(Val)); 1200 } 1201 1202 case ISD::SIGN_EXTEND: 1203 Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); 1204 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1205 1206 case ISD::SIGN_EXTEND_INREG: 1207 // Max of the input and what this extends. 1208 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1209 Tmp = VTBits-Tmp+1; 1210 1211 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1212 return std::max(Tmp, Tmp2); 1213 1214 case ISD::SRA: 1215 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1216 // SRA X, C -> adds C sign bits. 1217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1218 Tmp += C->getValue(); 1219 if (Tmp > VTBits) Tmp = VTBits; 1220 } 1221 return Tmp; 1222 case ISD::SHL: 1223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1224 // shl destroys sign bits. 1225 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1226 if (C->getValue() >= VTBits || // Bad shift. 1227 C->getValue() >= Tmp) break; // Shifted all sign bits out. 1228 return Tmp - C->getValue(); 1229 } 1230 break; 1231 case ISD::AND: 1232 case ISD::OR: 1233 case ISD::XOR: // NOT is handled here. 1234 // Logical binary ops preserve the number of sign bits. 1235 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1236 if (Tmp == 1) return 1; // Early out. 1237 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1238 return std::min(Tmp, Tmp2); 1239 1240 case ISD::SELECT: 1241 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1242 if (Tmp == 1) return 1; // Early out. 1243 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1244 return std::min(Tmp, Tmp2); 1245 1246 case ISD::SETCC: 1247 // If setcc returns 0/-1, all bits are sign bits. 1248 if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult) 1249 return VTBits; 1250 break; 1251 case ISD::ROTL: 1252 case ISD::ROTR: 1253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1254 unsigned RotAmt = C->getValue() & (VTBits-1); 1255 1256 // Handle rotate right by N like a rotate left by 32-N. 1257 if (Op.getOpcode() == ISD::ROTR) 1258 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1259 1260 // If we aren't rotating out all of the known-in sign bits, return the 1261 // number that are left. This handles rotl(sext(x), 1) for example. 1262 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1263 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1264 } 1265 break; 1266 case ISD::ADD: 1267 // Add can have at most one carry bit. Thus we know that the output 1268 // is, at worst, one more bit than the inputs. 1269 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1270 if (Tmp == 1) return 1; // Early out. 1271 1272 // Special case decrementing a value (ADD X, -1): 1273 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1274 if (CRHS->isAllOnesValue()) { 1275 uint64_t KnownZero, KnownOne; 1276 uint64_t Mask = MVT::getIntVTBitMask(VT); 1277 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1278 1279 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1280 // sign bits set. 1281 if ((KnownZero|1) == Mask) 1282 return VTBits; 1283 1284 // If we are subtracting one from a positive number, there is no carry 1285 // out of the result. 1286 if (KnownZero & MVT::getIntVTSignBit(VT)) 1287 return Tmp; 1288 } 1289 1290 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1291 if (Tmp2 == 1) return 1; 1292 return std::min(Tmp, Tmp2)-1; 1293 break; 1294 1295 case ISD::SUB: 1296 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1297 if (Tmp2 == 1) return 1; 1298 1299 // Handle NEG. 1300 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1301 if (CLHS->getValue() == 0) { 1302 uint64_t KnownZero, KnownOne; 1303 uint64_t Mask = MVT::getIntVTBitMask(VT); 1304 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1305 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1306 // sign bits set. 1307 if ((KnownZero|1) == Mask) 1308 return VTBits; 1309 1310 // If the input is known to be positive (the sign bit is known clear), 1311 // the output of the NEG has the same number of sign bits as the input. 1312 if (KnownZero & MVT::getIntVTSignBit(VT)) 1313 return Tmp2; 1314 1315 // Otherwise, we treat this like a SUB. 1316 } 1317 1318 // Sub can have at most one carry bit. Thus we know that the output 1319 // is, at worst, one more bit than the inputs. 1320 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1321 if (Tmp == 1) return 1; // Early out. 1322 return std::min(Tmp, Tmp2)-1; 1323 break; 1324 case ISD::TRUNCATE: 1325 // FIXME: it's tricky to do anything useful for this, but it is an important 1326 // case for targets like X86. 1327 break; 1328 } 1329 1330 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1331 if (Op.getOpcode() == ISD::LOAD) { 1332 LoadSDNode *LD = cast<LoadSDNode>(Op); 1333 unsigned ExtType = LD->getExtensionType(); 1334 switch (ExtType) { 1335 default: break; 1336 case ISD::SEXTLOAD: // '17' bits known 1337 Tmp = MVT::getSizeInBits(LD->getLoadedVT()); 1338 return VTBits-Tmp+1; 1339 case ISD::ZEXTLOAD: // '16' bits known 1340 Tmp = MVT::getSizeInBits(LD->getLoadedVT()); 1341 return VTBits-Tmp; 1342 } 1343 } 1344 1345 // Allow the target to implement this method for its nodes. 1346 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1347 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1348 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1349 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1350 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); 1351 if (NumBits > 1) return NumBits; 1352 } 1353 1354 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1355 // use this information. 1356 uint64_t KnownZero, KnownOne; 1357 uint64_t Mask = MVT::getIntVTBitMask(VT); 1358 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1359 1360 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1361 if (KnownZero & SignBit) { // SignBit is 0 1362 Mask = KnownZero; 1363 } else if (KnownOne & SignBit) { // SignBit is 1; 1364 Mask = KnownOne; 1365 } else { 1366 // Nothing known. 1367 return 1; 1368 } 1369 1370 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 1371 // the number of identical bits in the top of the input value. 1372 Mask ^= ~0ULL; 1373 Mask <<= 64-VTBits; 1374 // Return # leading zeros. We use 'min' here in case Val was zero before 1375 // shifting. We don't want to return '64' as for an i32 "0". 1376 return std::min(VTBits, CountLeadingZeros_64(Mask)); 1377} 1378 1379 1380 1381/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1382/// targets that want to expose additional information about sign bits to the 1383/// DAG Combiner. 1384unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1385 unsigned Depth) const { 1386 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1387 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1388 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1389 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1390 "Should use ComputeNumSignBits if you don't know whether Op" 1391 " is a target node!"); 1392 return 1; 1393} 1394 1395 1396SDOperand TargetLowering:: 1397PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1398 // Default implementation: no optimization. 1399 return SDOperand(); 1400} 1401 1402//===----------------------------------------------------------------------===// 1403// Inline Assembler Implementation Methods 1404//===----------------------------------------------------------------------===// 1405 1406TargetLowering::ConstraintType 1407TargetLowering::getConstraintType(char ConstraintLetter) const { 1408 // FIXME: lots more standard ones to handle. 1409 switch (ConstraintLetter) { 1410 default: return C_Unknown; 1411 case 'r': return C_RegisterClass; 1412 case 'm': // memory 1413 case 'o': // offsetable 1414 case 'V': // not offsetable 1415 return C_Memory; 1416 case 'i': // Simple Integer or Relocatable Constant 1417 case 'n': // Simple Integer 1418 case 's': // Relocatable Constant 1419 case 'I': // Target registers. 1420 case 'J': 1421 case 'K': 1422 case 'L': 1423 case 'M': 1424 case 'N': 1425 case 'O': 1426 case 'P': 1427 return C_Other; 1428 } 1429} 1430 1431/// isOperandValidForConstraint - Return the specified operand (possibly 1432/// modified) if the specified SDOperand is valid for the specified target 1433/// constraint letter, otherwise return null. 1434SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op, 1435 char ConstraintLetter, 1436 SelectionDAG &DAG) { 1437 switch (ConstraintLetter) { 1438 default: return SDOperand(0,0); 1439 case 'i': // Simple Integer or Relocatable Constant 1440 case 'n': // Simple Integer 1441 case 's': // Relocatable Constant 1442 return Op; // FIXME: not right. 1443 } 1444} 1445 1446std::vector<unsigned> TargetLowering:: 1447getRegClassForInlineAsmConstraint(const std::string &Constraint, 1448 MVT::ValueType VT) const { 1449 return std::vector<unsigned>(); 1450} 1451 1452 1453std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1454getRegForInlineAsmConstraint(const std::string &Constraint, 1455 MVT::ValueType VT) const { 1456 if (Constraint[0] != '{') 1457 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1458 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1459 1460 // Remove the braces from around the name. 1461 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1462 1463 // Figure out which register class contains this reg. 1464 const MRegisterInfo *RI = TM.getRegisterInfo(); 1465 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1466 E = RI->regclass_end(); RCI != E; ++RCI) { 1467 const TargetRegisterClass *RC = *RCI; 1468 1469 // If none of the the value types for this register class are valid, we 1470 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1471 bool isLegal = false; 1472 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1473 I != E; ++I) { 1474 if (isTypeLegal(*I)) { 1475 isLegal = true; 1476 break; 1477 } 1478 } 1479 1480 if (!isLegal) continue; 1481 1482 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1483 I != E; ++I) { 1484 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1485 return std::make_pair(*I, RC); 1486 } 1487 } 1488 1489 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1490} 1491 1492//===----------------------------------------------------------------------===// 1493// Loop Strength Reduction hooks 1494//===----------------------------------------------------------------------===// 1495 1496/// isLegalAddressImmediate - Return true if the integer value or 1497/// GlobalValue can be used as the offset of the target addressing mode. 1498bool TargetLowering::isLegalAddressImmediate(int64_t V) const { 1499 return false; 1500} 1501bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { 1502 return false; 1503} 1504 1505 1506// Magic for divide replacement 1507 1508struct ms { 1509 int64_t m; // magic number 1510 int64_t s; // shift amount 1511}; 1512 1513struct mu { 1514 uint64_t m; // magic number 1515 int64_t a; // add indicator 1516 int64_t s; // shift amount 1517}; 1518 1519/// magic - calculate the magic numbers required to codegen an integer sdiv as 1520/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1521/// or -1. 1522static ms magic32(int32_t d) { 1523 int32_t p; 1524 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1525 const uint32_t two31 = 0x80000000U; 1526 struct ms mag; 1527 1528 ad = abs(d); 1529 t = two31 + ((uint32_t)d >> 31); 1530 anc = t - 1 - t%ad; // absolute value of nc 1531 p = 31; // initialize p 1532 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1533 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1534 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1535 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1536 do { 1537 p = p + 1; 1538 q1 = 2*q1; // update q1 = 2p/abs(nc) 1539 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1540 if (r1 >= anc) { // must be unsigned comparison 1541 q1 = q1 + 1; 1542 r1 = r1 - anc; 1543 } 1544 q2 = 2*q2; // update q2 = 2p/abs(d) 1545 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1546 if (r2 >= ad) { // must be unsigned comparison 1547 q2 = q2 + 1; 1548 r2 = r2 - ad; 1549 } 1550 delta = ad - r2; 1551 } while (q1 < delta || (q1 == delta && r1 == 0)); 1552 1553 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1554 if (d < 0) mag.m = -mag.m; // resulting magic number 1555 mag.s = p - 32; // resulting shift 1556 return mag; 1557} 1558 1559/// magicu - calculate the magic numbers required to codegen an integer udiv as 1560/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1561static mu magicu32(uint32_t d) { 1562 int32_t p; 1563 uint32_t nc, delta, q1, r1, q2, r2; 1564 struct mu magu; 1565 magu.a = 0; // initialize "add" indicator 1566 nc = - 1 - (-d)%d; 1567 p = 31; // initialize p 1568 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1569 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1570 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1571 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1572 do { 1573 p = p + 1; 1574 if (r1 >= nc - r1 ) { 1575 q1 = 2*q1 + 1; // update q1 1576 r1 = 2*r1 - nc; // update r1 1577 } 1578 else { 1579 q1 = 2*q1; // update q1 1580 r1 = 2*r1; // update r1 1581 } 1582 if (r2 + 1 >= d - r2) { 1583 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1584 q2 = 2*q2 + 1; // update q2 1585 r2 = 2*r2 + 1 - d; // update r2 1586 } 1587 else { 1588 if (q2 >= 0x80000000) magu.a = 1; 1589 q2 = 2*q2; // update q2 1590 r2 = 2*r2 + 1; // update r2 1591 } 1592 delta = d - 1 - r2; 1593 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1594 magu.m = q2 + 1; // resulting magic number 1595 magu.s = p - 32; // resulting shift 1596 return magu; 1597} 1598 1599/// magic - calculate the magic numbers required to codegen an integer sdiv as 1600/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1601/// or -1. 1602static ms magic64(int64_t d) { 1603 int64_t p; 1604 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1605 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1606 struct ms mag; 1607 1608 ad = d >= 0 ? d : -d; 1609 t = two63 + ((uint64_t)d >> 63); 1610 anc = t - 1 - t%ad; // absolute value of nc 1611 p = 63; // initialize p 1612 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1613 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1614 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1615 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1616 do { 1617 p = p + 1; 1618 q1 = 2*q1; // update q1 = 2p/abs(nc) 1619 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1620 if (r1 >= anc) { // must be unsigned comparison 1621 q1 = q1 + 1; 1622 r1 = r1 - anc; 1623 } 1624 q2 = 2*q2; // update q2 = 2p/abs(d) 1625 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1626 if (r2 >= ad) { // must be unsigned comparison 1627 q2 = q2 + 1; 1628 r2 = r2 - ad; 1629 } 1630 delta = ad - r2; 1631 } while (q1 < delta || (q1 == delta && r1 == 0)); 1632 1633 mag.m = q2 + 1; 1634 if (d < 0) mag.m = -mag.m; // resulting magic number 1635 mag.s = p - 64; // resulting shift 1636 return mag; 1637} 1638 1639/// magicu - calculate the magic numbers required to codegen an integer udiv as 1640/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1641static mu magicu64(uint64_t d) 1642{ 1643 int64_t p; 1644 uint64_t nc, delta, q1, r1, q2, r2; 1645 struct mu magu; 1646 magu.a = 0; // initialize "add" indicator 1647 nc = - 1 - (-d)%d; 1648 p = 63; // initialize p 1649 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1650 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1651 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1652 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1653 do { 1654 p = p + 1; 1655 if (r1 >= nc - r1 ) { 1656 q1 = 2*q1 + 1; // update q1 1657 r1 = 2*r1 - nc; // update r1 1658 } 1659 else { 1660 q1 = 2*q1; // update q1 1661 r1 = 2*r1; // update r1 1662 } 1663 if (r2 + 1 >= d - r2) { 1664 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1665 q2 = 2*q2 + 1; // update q2 1666 r2 = 2*r2 + 1 - d; // update r2 1667 } 1668 else { 1669 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1670 q2 = 2*q2; // update q2 1671 r2 = 2*r2 + 1; // update r2 1672 } 1673 delta = d - 1 - r2; 1674 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1675 magu.m = q2 + 1; // resulting magic number 1676 magu.s = p - 64; // resulting shift 1677 return magu; 1678} 1679 1680/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1681/// return a DAG expression to select that will generate the same value by 1682/// multiplying by a magic number. See: 1683/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1684SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1685 std::vector<SDNode*>* Created) const { 1686 MVT::ValueType VT = N->getValueType(0); 1687 1688 // Check to see if we can do this. 1689 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1690 return SDOperand(); // BuildSDIV only operates on i32 or i64 1691 if (!isOperationLegal(ISD::MULHS, VT)) 1692 return SDOperand(); // Make sure the target supports MULHS. 1693 1694 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1695 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1696 1697 // Multiply the numerator (operand 0) by the magic value 1698 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1699 DAG.getConstant(magics.m, VT)); 1700 // If d > 0 and m < 0, add the numerator 1701 if (d > 0 && magics.m < 0) { 1702 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1703 if (Created) 1704 Created->push_back(Q.Val); 1705 } 1706 // If d < 0 and m > 0, subtract the numerator. 1707 if (d < 0 && magics.m > 0) { 1708 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1709 if (Created) 1710 Created->push_back(Q.Val); 1711 } 1712 // Shift right algebraic if shift value is nonzero 1713 if (magics.s > 0) { 1714 Q = DAG.getNode(ISD::SRA, VT, Q, 1715 DAG.getConstant(magics.s, getShiftAmountTy())); 1716 if (Created) 1717 Created->push_back(Q.Val); 1718 } 1719 // Extract the sign bit and add it to the quotient 1720 SDOperand T = 1721 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1722 getShiftAmountTy())); 1723 if (Created) 1724 Created->push_back(T.Val); 1725 return DAG.getNode(ISD::ADD, VT, Q, T); 1726} 1727 1728/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1729/// return a DAG expression to select that will generate the same value by 1730/// multiplying by a magic number. See: 1731/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1732SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1733 std::vector<SDNode*>* Created) const { 1734 MVT::ValueType VT = N->getValueType(0); 1735 1736 // Check to see if we can do this. 1737 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1738 return SDOperand(); // BuildUDIV only operates on i32 or i64 1739 if (!isOperationLegal(ISD::MULHU, VT)) 1740 return SDOperand(); // Make sure the target supports MULHU. 1741 1742 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1743 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1744 1745 // Multiply the numerator (operand 0) by the magic value 1746 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1747 DAG.getConstant(magics.m, VT)); 1748 if (Created) 1749 Created->push_back(Q.Val); 1750 1751 if (magics.a == 0) { 1752 return DAG.getNode(ISD::SRL, VT, Q, 1753 DAG.getConstant(magics.s, getShiftAmountTy())); 1754 } else { 1755 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1756 if (Created) 1757 Created->push_back(NPQ.Val); 1758 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1759 DAG.getConstant(1, getShiftAmountTy())); 1760 if (Created) 1761 Created->push_back(NPQ.Val); 1762 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1763 if (Created) 1764 Created->push_back(NPQ.Val); 1765 return DAG.getNode(ISD::SRL, VT, NPQ, 1766 DAG.getConstant(magics.s-1, getShiftAmountTy())); 1767 } 1768} 1769 1770MVT::ValueType TargetLowering::getValueType(const Type *Ty) const { 1771 switch (Ty->getTypeID()) { 1772 default: assert(0 && "Unknown type!"); 1773 case Type::VoidTyID: return MVT::isVoid; 1774 case Type::IntegerTyID: 1775 switch (cast<IntegerType>(Ty)->getBitWidth()) { 1776 default: assert(0 && "Invalid width for value type"); 1777 case 1: return MVT::i1; 1778 case 8: return MVT::i8; 1779 case 16: return MVT::i16; 1780 case 32: return MVT::i32; 1781 case 64: return MVT::i64; 1782 } 1783 break; 1784 case Type::FloatTyID: return MVT::f32; 1785 case Type::DoubleTyID: return MVT::f64; 1786 case Type::PointerTyID: return PointerTy; 1787 case Type::PackedTyID: return MVT::Vector; 1788 } 1789} 1790