TargetInstrInfoImpl.cpp revision 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855
1641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// 2641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 3641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// The LLVM Compiler Infrastructure 4641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 5641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file is distributed under the University of Illinois Open Source 6641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// License. See LICENSE.TXT for details. 7641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 8641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 9641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 10641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file implements the TargetInstrInfoImpl class, it just provides default 11641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// implementations of various methods. 12641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 13641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 14641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 15641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng#include "llvm/Target/TargetLowering.h" 17a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetMachine.h" 18a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson#include "llvm/ADT/SmallVector.h" 20c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/MachineFrameInfo.h" 21641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/CodeGen/MachineInstr.h" 2258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 23c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman#include "llvm/CodeGen/MachineMemOperand.h" 24a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 25774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng#include "llvm/CodeGen/PostRAHazardRecognizer.h" 26c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/PseudoSourceValue.h" 2734c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/ErrorHandling.h" 2834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/raw_ostream.h" 29641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerusing namespace llvm; 30641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 314d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 324d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// after it, replacing it with an unconditional branch to NewDest. 3386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengvoid 3486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan ChengTargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 3586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const { 3686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *MBB = Tail->getParent(); 3786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 3886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the old successors of MBB from the CFG. 3986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng while (!MBB->succ_empty()) 4086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->removeSuccessor(MBB->succ_begin()); 4186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the dead instructions from the end of MBB. 4386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->erase(Tail, MBB->end()); 4486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // If MBB isn't immediately before MBB, insert a branch to it. 4686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) 4786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(), 4886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng Tail->getDebugLoc()); 4986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->addSuccessor(NewDest); 5086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 5186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 52641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// commuteInstruction - The default implementation of this method just exchanges 5334c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng// the two operands returned by findCommutedOpIndices. 5458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, 5558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI) const { 56498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 57498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool HasDef = TID.getNumDefs(); 5834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (HasDef && !MI->getOperand(0).isReg()) 5934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng // No idea how to commute this instruction. Target should implement its own. 6034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng return 0; 6134c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng unsigned Idx1, Idx2; 6234c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (!findCommutedOpIndices(MI, Idx1, Idx2)) { 6334c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng std::string msg; 6434c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng raw_string_ostream Msg(msg); 6534c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng Msg << "Don't know how to commute: " << *MI; 6675361b69f3f327842b9dad69fa7f28ae3b688412Chris Lattner report_fatal_error(Msg.str()); 6734c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng } 68498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng 69498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 70641055225092833197efe8e5bce01d50bcf1daaeChris Lattner "This only knows how to commute register operands so far"); 71498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg1 = MI->getOperand(Idx1).getReg(); 72498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg2 = MI->getOperand(Idx2).getReg(); 73498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg1IsKill = MI->getOperand(Idx1).isKill(); 74498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg2IsKill = MI->getOperand(Idx2).isKill(); 7558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 76498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef && MI->getOperand(0).getReg() == Reg1) { 77a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 78a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 79a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 80a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 8158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 8258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 8358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 8458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 8558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 86498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg0 = HasDef 87498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; 88498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; 898e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 90498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef) 91498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 92498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 93498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 94498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 95498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng else 96498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 97498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 98498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 99a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 10058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 10158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 10258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 103498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setReg(Reg1); 104498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setReg(Reg2); 105498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setIsKill(Reg1IsKill); 106498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setIsKill(Reg2IsKill); 107641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MI; 108641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 109641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 110261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// findCommutedOpIndices - If specified MI is commutable, return the two 111261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// operand indices that would swap value. Return true if the instruction 112261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// is not in a form which this routine understands. 113261ce1d5f89155d2e6f914f281db2004c89ee839Evan Chengbool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI, 114261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx1, 115261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const { 116498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 117261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!TID.isCommutable()) 118498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return false; 119261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this 120261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // is not true, then the target must implement this. 121261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx1 = TID.getNumDefs(); 122261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx2 = SrcOpIdx1 + 1; 123261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!MI->getOperand(SrcOpIdx1).isReg() || 124261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng !MI->getOperand(SrcOpIdx2).isReg()) 125261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // No idea. 126261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return false; 127261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return true; 128f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng} 129f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 130f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 131641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerbool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, 13244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const { 133641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool MadeChange = false; 134749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &TID = MI->getDesc(); 135749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (!TID.isPredicable()) 136749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return false; 137749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner 138749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { 139749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (TID.OpInfo[i].isPredicate()) { 140749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MachineOperand &MO = MI->getOperand(i); 141d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) { 142749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setReg(Pred[j].getReg()); 143749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 144d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isImm()) { 145749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setImm(Pred[j].getImm()); 146749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 147d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isMBB()) { 148749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setMBB(Pred[j].getMBB()); 149749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 150641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 151749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner ++j; 152641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 153641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 154641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MadeChange; 155641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 156ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 157ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Chengvoid TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, 158ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator I, 159ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 160378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned SubIdx, 161d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1629edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1638e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1649edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 165ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MBB.insert(I, MI); 166ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng} 167ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 168506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengbool TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0, 169506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const { 170506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 171506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng} 172506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng 17330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig, 17430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const { 17530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(!Orig->getDesc().isNotDuplicable() && 17630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Instruction cannot be duplicated"); 17730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MF.CloneMachineInstr(Orig); 17830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 17930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 18052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffrayunsigned 18152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas GeoffrayTargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const { 18252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray unsigned FnSize = 0; 18352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 18452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray MBBI != E; ++MBBI) { 18552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const MachineBasicBlock &MBB = *MBBI; 1863885578a36072dd55c3381b99d4a88299dddbfa3Evan Cheng for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 1873885578a36072dd55c3381b99d4a88299dddbfa3Evan Cheng I != E; ++I) 18852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray FnSize += GetInstSizeInBytes(I); 18952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 19052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return FnSize; 19152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray} 192c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 193c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Attempt to fold a load or store of the specified stack 194c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// slot into the specified machine instruction for the specified operand(s). 195c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// If this is possible, a new instruction is returned with the specified 196c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// operand folded, otherwise NULL is returned. The client is responsible for 197c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// removing the old instruction and adding the new one in the instruction 198c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stream. 199c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 200c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanTargetInstrInfo::foldMemoryOperand(MachineFunction &MF, 201c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 202c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 203c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 204c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman unsigned Flags = 0; 205c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 206c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (MI->getOperand(Ops[i]).isDef()) 207c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOStore; 208c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman else 209c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOLoad; 210c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 211c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 212c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex); 213c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (!NewMI) return 0; 214c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 215c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert((!(Flags & MachineMemOperand::MOStore) || 216c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman NewMI->getDesc().mayStore()) && 217c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman "Folded a def to a non-store!"); 218c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert((!(Flags & MachineMemOperand::MOLoad) || 219c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman NewMI->getDesc().mayLoad()) && 220c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman "Folded a use to a non-load!"); 221c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const MachineFrameInfo &MFI = *MF.getFrameInfo(); 222c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(MFI.getObjectOffset(FrameIndex) != -1); 223c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman MachineMemOperand *MMO = 224ff89dcb06fbd103373436e2d0ae85f252fae2254Evan Cheng MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex), 225c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman Flags, /*Offset=*/0, 226c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman MFI.getObjectSize(FrameIndex), 227c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman MFI.getObjectAlignment(FrameIndex)); 228c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman NewMI->addMemOperand(MF, MMO); 229c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 230c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return NewMI; 231c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 232c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 233c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Same as the previous version except it allows folding 234c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// of any load and store from / to any address, not just from a specific 235c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stack slot. 236c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 237c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanTargetInstrInfo::foldMemoryOperand(MachineFunction &MF, 238c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 239c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 240c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 241c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!"); 242c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#ifndef NDEBUG 243c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 244c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); 245c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#endif 246c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 247c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 248c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI); 249c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (!NewMI) return 0; 250c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 251c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Copy the memoperands from the load to the folded instruction. 252c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman NewMI->setMemRefs(LoadMI->memoperands_begin(), 253c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman LoadMI->memoperands_end()); 254c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 255c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return NewMI; 256c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 257a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 25844acc24117b1a9eafb7b9b993731ca0115569ea2Evan Chengbool TargetInstrInfo:: 25944acc24117b1a9eafb7b9b993731ca0115569ea2Evan ChengisReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 26044acc24117b1a9eafb7b9b993731ca0115569ea2Evan Cheng AliasAnalysis *AA) const { 261a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineFunction &MF = *MI->getParent()->getParent(); 262a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineRegisterInfo &MRI = MF.getRegInfo(); 263a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetMachine &TM = MF.getTarget(); 264a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrInfo &TII = *TM.getInstrInfo(); 265a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 266a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 267a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A load from a fixed stack slot can be rematerialized. This may be 268a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // redundant with subsequent checks, but it's target-independent, 269a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // simple, and a common case. 270a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman int FrameIdx = 0; 271a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TII.isLoadFromStackSlot(MI, FrameIdx) && 272a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) 273a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 274a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 275a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrDesc &TID = MI->getDesc(); 276a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 277a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions obviously unsafe for remat. 278a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() || 279a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman TID.mayStore()) 280a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 281a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 282a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions which load from potentially varying memory. 283a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TID.mayLoad() && !MI->isInvariantLoad(AA)) 284a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 285a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 286a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If any of the registers accessed are non-constant, conservatively assume 287a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // the instruction is not rematerializable. 288a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 289a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineOperand &MO = MI->getOperand(i); 290a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MO.isReg()) continue; 291a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned Reg = MO.getReg(); 292a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (Reg == 0) 293a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 294a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 295a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a well-behaved physical register. 296a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 297a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) { 298a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If the physreg has no defs anywhere, it's just an ambient register 299a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // and we can freely move its uses. Alternatively, if it's allocatable, 300a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // it could get allocated to something with a def during allocation. 301a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(Reg)) 302a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 303a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); 304a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(Reg)) 305a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 306a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a def among the register's aliases too. 307a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) { 308a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned AliasReg = *Alias; 309a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(AliasReg)) 310a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 311a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(AliasReg)) 312a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 313a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 314a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } else { 315a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A physreg def. We can't remat it. 316a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 317a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 318a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 319a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 320a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 321a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Only allow one virtual-register def, and that in the first operand. 322a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isDef() != (i == 0)) 323a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 324a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 325a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // For the def, it should be the only def of that register. 3267896c9f436a4eda5ec15e882a7505ba482a2fcd0Chris Lattner if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() || 327a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MRI.isLiveIn(Reg))) 328a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 329a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 330a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Don't allow any virtual-register uses. Rematting an instruction with 331a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // virtual register uses would length the live ranges of the uses, which 332a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // is not necessarily a good idea, certainly not "trivial". 333a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) 334a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 335a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 336a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 337a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Everything checked out. 338a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 339a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman} 340774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng 34186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// isSchedulingBoundary - Test if the given instruction should be 34286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// considered a scheduling boundary. This primarily includes labels 34386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// and terminators. 34486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI, 34586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 34686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const{ 34786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 34886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 34986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 35086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 35186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 35286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 35386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 35486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 35586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 35686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); 35786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore())) 35886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 35986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 36086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 36186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 36286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 363774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng// Default implementation of CreateTargetPostRAHazardRecognizer. 364774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan ChengScheduleHazardRecognizer *TargetInstrInfoImpl:: 365774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan ChengCreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { 366774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II); 367774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng} 368