TargetInstrInfoImpl.cpp revision 8e5f2c6f65841542e2a7092553fe42a00048e4c7
1641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// 2641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 3641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// The LLVM Compiler Infrastructure 4641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 5641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file is distributed under the University of Illinois Open Source 6641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// License. See LICENSE.TXT for details. 7641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 8641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 9641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 10641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file implements the TargetInstrInfoImpl class, it just provides default 11641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// implementations of various methods. 12641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 13641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 14641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 15641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/Target/TargetInstrInfo.h" 16641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/CodeGen/MachineInstr.h" 1758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 18641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerusing namespace llvm; 19641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 20641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// commuteInstruction - The default implementation of this method just exchanges 21641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// operand 1 and 2. 2258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, 2358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI) const { 24641055225092833197efe8e5bce01d50bcf1daaeChris Lattner assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && 25641055225092833197efe8e5bce01d50bcf1daaeChris Lattner "This only knows how to commute register operands so far"); 26641055225092833197efe8e5bce01d50bcf1daaeChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 27641055225092833197efe8e5bce01d50bcf1daaeChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 28641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool Reg1IsKill = MI->getOperand(1).isKill(); 29641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool Reg2IsKill = MI->getOperand(2).isKill(); 3058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 319cec00e7f1dec7c3142d81c1256d198afa3718d3Evan Cheng if (MI->getOperand(0).getReg() == Reg1) { 32a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 33a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 34a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 35a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 3658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 3758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 3858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 3958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 4058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 4158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 4258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool Reg0IsDead = MI->getOperand(0).isDead(); 438e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 448e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman return BuildMI(MF, MI->getDesc()) 458e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman .addReg(Reg0, true, false, false, Reg0IsDead) 4658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addReg(Reg2, false, false, Reg2IsKill) 4758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addReg(Reg1, false, false, Reg1IsKill); 48a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 4958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 5058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 5158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 52641055225092833197efe8e5bce01d50bcf1daaeChris Lattner MI->getOperand(2).setReg(Reg1); 53641055225092833197efe8e5bce01d50bcf1daaeChris Lattner MI->getOperand(1).setReg(Reg2); 54641055225092833197efe8e5bce01d50bcf1daaeChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 55641055225092833197efe8e5bce01d50bcf1daaeChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 56641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MI; 57641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 58641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 59f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng/// CommuteChangesDestination - Return true if commuting the specified 60f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng/// instruction will also changes the destination operand. Also return the 61f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng/// current operand index of the would be new destination register by 62f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng/// reference. This can happen when the commutable instruction is also a 63f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng/// two-address instruction. 64f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Chengbool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI, 65f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng unsigned &OpIdx) const{ 66f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && 67f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng "This only knows how to commute register operands so far"); 68f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 69f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng // Must be two address instruction! 70f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 71f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng "Expecting a two-address instruction!"); 72f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng OpIdx = 2; 73f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng return true; 74f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng } 75f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng return false; 76f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng} 77f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 78f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 79641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerbool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, 80f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng const std::vector<MachineOperand> &Pred) const { 81641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool MadeChange = false; 82749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &TID = MI->getDesc(); 83749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (!TID.isPredicable()) 84749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return false; 85749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner 86749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { 87749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (TID.OpInfo[i].isPredicate()) { 88749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MachineOperand &MO = MI->getOperand(i); 89749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (MO.isReg()) { 90749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setReg(Pred[j].getReg()); 91749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 92749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner } else if (MO.isImm()) { 93749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setImm(Pred[j].getImm()); 94749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 95749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner } else if (MO.isMBB()) { 96749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setMBB(Pred[j].getMBB()); 97749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 98641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 99749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner ++j; 100641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 101641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 102641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MadeChange; 103641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 104ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 105ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Chengvoid TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, 106ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator I, 107ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 108ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const { 1098e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 110ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MI->getOperand(0).setReg(DestReg); 111ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MBB.insert(I, MI); 112ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng} 113ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 11452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffrayunsigned 11552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas GeoffrayTargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const { 11652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray unsigned FnSize = 0; 11752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 11852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray MBBI != E; ++MBBI) { 11952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const MachineBasicBlock &MBB = *MBBI; 12052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I) 12152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray FnSize += GetInstSizeInBytes(I); 12252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 12352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return FnSize; 12452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray} 125