TargetInstrInfoImpl.cpp revision 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46
1641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// 2641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 3641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// The LLVM Compiler Infrastructure 4641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 5641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file is distributed under the University of Illinois Open Source 6641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// License. See LICENSE.TXT for details. 7641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 8641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 9641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 10641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file implements the TargetInstrInfoImpl class, it just provides default 11641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// implementations of various methods. 12641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 13641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 14641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 15641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng#include "llvm/Target/TargetLowering.h" 17a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetMachine.h" 18a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson#include "llvm/ADT/SmallVector.h" 20c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/MachineFrameInfo.h" 21641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/CodeGen/MachineInstr.h" 2258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 23c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman#include "llvm/CodeGen/MachineMemOperand.h" 24a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 256b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick#include "llvm/CodeGen/ScoreboardHazardRecognizer.h" 26c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/PseudoSourceValue.h" 279fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen#include "llvm/Support/Debug.h" 2834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/ErrorHandling.h" 2934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/raw_ostream.h" 30641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerusing namespace llvm; 31641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 324d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 334d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// after it, replacing it with an unconditional branch to NewDest. 3486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengvoid 3586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan ChengTargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 3686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const { 3786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *MBB = Tail->getParent(); 3886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 3986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the old successors of MBB from the CFG. 4086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng while (!MBB->succ_empty()) 4186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->removeSuccessor(MBB->succ_begin()); 4286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the dead instructions from the end of MBB. 4486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->erase(Tail, MBB->end()); 4586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // If MBB isn't immediately before MBB, insert a branch to it. 4786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) 4886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(), 4986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng Tail->getDebugLoc()); 5086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->addSuccessor(NewDest); 5186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 5286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 53641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// commuteInstruction - The default implementation of this method just exchanges 5434c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng// the two operands returned by findCommutedOpIndices. 5558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, 5658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI) const { 57498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 58498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool HasDef = TID.getNumDefs(); 5934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (HasDef && !MI->getOperand(0).isReg()) 6034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng // No idea how to commute this instruction. Target should implement its own. 6134c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng return 0; 6234c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng unsigned Idx1, Idx2; 6334c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (!findCommutedOpIndices(MI, Idx1, Idx2)) { 6434c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng std::string msg; 6534c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng raw_string_ostream Msg(msg); 6634c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng Msg << "Don't know how to commute: " << *MI; 6775361b69f3f327842b9dad69fa7f28ae3b688412Chris Lattner report_fatal_error(Msg.str()); 6834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng } 69498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng 70498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 71641055225092833197efe8e5bce01d50bcf1daaeChris Lattner "This only knows how to commute register operands so far"); 72498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg1 = MI->getOperand(Idx1).getReg(); 73498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg2 = MI->getOperand(Idx2).getReg(); 74498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg1IsKill = MI->getOperand(Idx1).isKill(); 75498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg2IsKill = MI->getOperand(Idx2).isKill(); 7658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 77498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef && MI->getOperand(0).getReg() == Reg1) { 78a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 79a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 80a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 81a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 8258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 8358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 8458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 8558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 8658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 87498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg0 = HasDef 88498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; 89498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; 908e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 91498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef) 92498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 93498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 94498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 95498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 96498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng else 97498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 98498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 99498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 100a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 10158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 10258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 10358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 104498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setReg(Reg1); 105498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setReg(Reg2); 106498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setIsKill(Reg1IsKill); 107498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setIsKill(Reg2IsKill); 108641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MI; 109641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 110641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 111261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// findCommutedOpIndices - If specified MI is commutable, return the two 112261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// operand indices that would swap value. Return true if the instruction 113261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// is not in a form which this routine understands. 114261ce1d5f89155d2e6f914f281db2004c89ee839Evan Chengbool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI, 115261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx1, 116261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const { 117498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 118261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!TID.isCommutable()) 119498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return false; 120261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this 121261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // is not true, then the target must implement this. 122261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx1 = TID.getNumDefs(); 123261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx2 = SrcOpIdx1 + 1; 124261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!MI->getOperand(SrcOpIdx1).isReg() || 125261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng !MI->getOperand(SrcOpIdx2).isReg()) 126261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // No idea. 127261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return false; 128261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return true; 129f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng} 130f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 131f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 132641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerbool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, 13344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const { 134641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool MadeChange = false; 135749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &TID = MI->getDesc(); 136749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (!TID.isPredicable()) 137749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return false; 1386b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick 139749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { 140749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (TID.OpInfo[i].isPredicate()) { 141749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MachineOperand &MO = MI->getOperand(i); 142d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) { 143749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setReg(Pred[j].getReg()); 144749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 145d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isImm()) { 146749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setImm(Pred[j].getImm()); 147749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 148d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isMBB()) { 149749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setMBB(Pred[j].getMBB()); 150749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 151641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 152749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner ++j; 153641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 154641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 155641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MadeChange; 156641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 157ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 158ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Chengvoid TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, 159ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator I, 160ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 161378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned SubIdx, 162d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1639edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1648e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1659edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 166ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MBB.insert(I, MI); 167ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng} 168ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 1699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool 1709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan ChengTargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0, 1719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 1729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 173506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 174506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng} 175506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng 17630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig, 17730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const { 17830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(!Orig->getDesc().isNotDuplicable() && 17930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Instruction cannot be duplicated"); 18030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MF.CloneMachineInstr(Orig); 18130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 18230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1831f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// If the COPY instruction in MI can be folded to a stack operation, return 1841f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// the register class to use. 1851f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenstatic const TargetRegisterClass *canFoldCopy(const MachineInstr *MI, 1861f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldIdx) { 1871f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MI->isCopy() && "MI must be a COPY instruction"); 1881f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (MI->getNumOperands() != 2) 1891f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 1901f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand"); 1911f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 1921f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &FoldOp = MI->getOperand(FoldIdx); 1931f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx); 1941f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 1951f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (FoldOp.getSubReg() || LiveOp.getSubReg()) 1961f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 1971f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 1981f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldReg = FoldOp.getReg(); 1991f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned LiveReg = LiveOp.getReg(); 2001f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2011f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(TargetRegisterInfo::isVirtualRegister(FoldReg) && 2021f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen "Cannot fold physregs"); 2031f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2041f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 2051f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 2061f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2071f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) 2081f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC->contains(LiveOp.getReg()) ? RC : 0; 2091f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2101f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg); 2111f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (RC == LiveRC || RC->hasSubClass(LiveRC)) 2121f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC; 2131f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2141f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen // FIXME: Allow folding when register classes are memory compatible. 2151f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2161f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2171f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2181f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenbool TargetInstrInfoImpl:: 2191f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund OlesencanFoldMemoryOperand(const MachineInstr *MI, 2201f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const { 2211f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]); 2221f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2231f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 224c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Attempt to fold a load or store of the specified stack 225c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// slot into the specified machine instruction for the specified operand(s). 226c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// If this is possible, a new instruction is returned with the specified 227c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// operand folded, otherwise NULL is returned. The client is responsible for 228c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// removing the old instruction and adding the new one in the instruction 229c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stream. 230c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 231e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 232c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 2331f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen int FI) const { 234c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman unsigned Flags = 0; 235c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 236c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (MI->getOperand(Ops[i]).isDef()) 237c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOStore; 238c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman else 239c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOLoad; 240c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 2411f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineBasicBlock *MBB = MI->getParent(); 2421f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MBB && "foldMemoryOperand needs an inserted instruction"); 2431f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineFunction &MF = *MBB->getParent(); 244e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 245c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 2469fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) { 2479fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Add a memory operand, foldMemoryOperandImpl doesn't do that. 2489fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOStore) || 2499fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->getDesc().mayStore()) && 2509fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a def to a non-store!"); 2519fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOLoad) || 2529fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->getDesc().mayLoad()) && 2539fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a use to a non-load!"); 2549fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 2559fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert(MFI.getObjectOffset(FI) != -1); 2569fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineMemOperand *MMO = 25793a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner MF.getMachineMemOperand( 25893a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 25993a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner Flags, MFI.getObjectSize(FI), 2609fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MFI.getObjectAlignment(FI)); 2619fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->addMemOperand(MF, MMO); 2621f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2639fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI. 2649fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return MBB->insert(MI, NewMI); 2659fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen } 2661f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2679fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Straight COPY may fold as load/store. 2689fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!MI->isCopy() || Ops.size() != 1) 2699fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 2701f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2719fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); 2729fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!RC) 2739fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 2741f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2759fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(1-Ops[0]); 2769fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineBasicBlock::iterator Pos = MI; 2779fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 2781f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2799fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (Flags == MachineMemOperand::MOStore) 2809fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 2819fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen else 2829fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); 2839fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return --Pos; 284c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 285c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 286c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Same as the previous version except it allows folding 287c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// of any load and store from / to any address, not just from a specific 288c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stack slot. 289c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 290e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 291c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 292c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 293c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!"); 294c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#ifndef NDEBUG 295c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 296c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); 297c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#endif 298e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineBasicBlock &MBB = *MI->getParent(); 299e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineFunction &MF = *MBB.getParent(); 300c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 301c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 302c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI); 303c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (!NewMI) return 0; 304c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 305e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen NewMI = MBB.insert(MI, NewMI); 306e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 307c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Copy the memoperands from the load to the folded instruction. 308c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman NewMI->setMemRefs(LoadMI->memoperands_begin(), 309c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman LoadMI->memoperands_end()); 310c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 311c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return NewMI; 312c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 313a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 31444acc24117b1a9eafb7b9b993731ca0115569ea2Evan Chengbool TargetInstrInfo:: 31544acc24117b1a9eafb7b9b993731ca0115569ea2Evan ChengisReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 31644acc24117b1a9eafb7b9b993731ca0115569ea2Evan Cheng AliasAnalysis *AA) const { 317a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineFunction &MF = *MI->getParent()->getParent(); 318a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineRegisterInfo &MRI = MF.getRegInfo(); 319a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetMachine &TM = MF.getTarget(); 320a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrInfo &TII = *TM.getInstrInfo(); 321a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 322a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 323a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A load from a fixed stack slot can be rematerialized. This may be 324a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // redundant with subsequent checks, but it's target-independent, 325a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // simple, and a common case. 326a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman int FrameIdx = 0; 327a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TII.isLoadFromStackSlot(MI, FrameIdx) && 328a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) 329a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 330a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 331a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrDesc &TID = MI->getDesc(); 332a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 333a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions obviously unsafe for remat. 334c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng if (TID.isNotDuplicable() || TID.mayStore() || 335c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->hasUnmodeledSideEffects()) 336c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng return false; 337c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng 338c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Don't remat inline asm. We have no idea how expensive it is 339c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // even if it's side effect free. 340c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng if (MI->isInlineAsm()) 341a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 342a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 343a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions which load from potentially varying memory. 344a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TID.mayLoad() && !MI->isInvariantLoad(AA)) 345a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 346a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 347a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If any of the registers accessed are non-constant, conservatively assume 348a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // the instruction is not rematerializable. 349a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 350a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineOperand &MO = MI->getOperand(i); 351a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MO.isReg()) continue; 352a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned Reg = MO.getReg(); 353a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (Reg == 0) 354a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 355a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 356a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a well-behaved physical register. 357a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 358a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) { 359a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If the physreg has no defs anywhere, it's just an ambient register 360a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // and we can freely move its uses. Alternatively, if it's allocatable, 361a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // it could get allocated to something with a def during allocation. 362a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(Reg)) 363a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 364a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); 365a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(Reg)) 366a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 367a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a def among the register's aliases too. 368a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) { 369a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned AliasReg = *Alias; 370a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(AliasReg)) 371a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 372a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(AliasReg)) 373a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 374a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 375a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } else { 376a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A physreg def. We can't remat it. 377a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 378a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 379a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 380a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 381a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 382a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Only allow one virtual-register def, and that in the first operand. 383a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isDef() != (i == 0)) 384a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 385a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 386a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // For the def, it should be the only def of that register. 3877896c9f436a4eda5ec15e882a7505ba482a2fcd0Chris Lattner if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() || 388a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MRI.isLiveIn(Reg))) 389a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 390a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 391a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Don't allow any virtual-register uses. Rematting an instruction with 392a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // virtual register uses would length the live ranges of the uses, which 393a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // is not necessarily a good idea, certainly not "trivial". 394a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) 395a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 396a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 397a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 398a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Everything checked out. 399a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 400a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman} 401774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng 40286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// isSchedulingBoundary - Test if the given instruction should be 40386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// considered a scheduling boundary. This primarily includes labels 40486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// and terminators. 40586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI, 40686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 40786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const{ 40886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 40986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 41086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 41186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 41286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 41386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 41486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 41586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 41686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 41786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); 41886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore())) 41986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 42086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 42186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 42286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 42386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4242da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick// Default implementation of CreateTargetPreRAHazardRecognizer. 4252da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *TargetInstrInfoImpl:: 4262da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 4272da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 4282da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick // Dummy hazard recognizer allows all instructions to issue. 4292da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScheduleHazardRecognizer(); 4302da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 4312da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 432774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng// Default implementation of CreateTargetPostRAHazardRecognizer. 433774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan ChengScheduleHazardRecognizer *TargetInstrInfoImpl:: 4342da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 4352da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 4362da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return (ScheduleHazardRecognizer *) 4372da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched"); 438774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng} 439