ARMInstPrinter.cpp revision 5e3d24588bcca470142e76f4d14918c92347bda2 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMBaseInfo.h"
16#include "ARMInstPrinter.h"
17#include "ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25#define GET_INSTRUCTION_NAME
26#include "ARMGenAsmWriter.inc"
27
28StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29  return getInstructionName(Opcode);
30}
31
32
33void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
34  // Check for MOVs and print canonical forms, instead.
35  if (MI->getOpcode() == ARM::MOVs) {
36    // FIXME: Thumb variants?
37    const MCOperand &Dst = MI->getOperand(0);
38    const MCOperand &MO1 = MI->getOperand(1);
39    const MCOperand &MO2 = MI->getOperand(2);
40    const MCOperand &MO3 = MI->getOperand(3);
41
42    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
43    printSBitModifierOperand(MI, 6, O);
44    printPredicateOperand(MI, 4, O);
45
46    O << '\t' << getRegisterName(Dst.getReg())
47      << ", " << getRegisterName(MO1.getReg());
48
49    if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
50      return;
51
52    O << ", ";
53
54    if (MO2.getReg()) {
55      O << getRegisterName(MO2.getReg());
56      assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
57    } else {
58      O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
59    }
60    return;
61  }
62
63  // A8.6.123 PUSH
64  if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
65      MI->getOperand(0).getReg() == ARM::SP) {
66    const MCOperand &MO1 = MI->getOperand(2);
67    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
68      O << '\t' << "push";
69      printPredicateOperand(MI, 3, O);
70      O << '\t';
71      printRegisterList(MI, 5, O);
72      return;
73    }
74  }
75
76  // A8.6.122 POP
77  if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
78      MI->getOperand(0).getReg() == ARM::SP) {
79    const MCOperand &MO1 = MI->getOperand(2);
80    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
81      O << '\t' << "pop";
82      printPredicateOperand(MI, 3, O);
83      O << '\t';
84      printRegisterList(MI, 5, O);
85      return;
86    }
87  }
88
89  // A8.6.355 VPUSH
90  if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
91      MI->getOperand(0).getReg() == ARM::SP) {
92    const MCOperand &MO1 = MI->getOperand(2);
93    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
94      O << '\t' << "vpush";
95      printPredicateOperand(MI, 3, O);
96      O << '\t';
97      printRegisterList(MI, 5, O);
98      return;
99    }
100  }
101
102  // A8.6.354 VPOP
103  if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
104      MI->getOperand(0).getReg() == ARM::SP) {
105    const MCOperand &MO1 = MI->getOperand(2);
106    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
107      O << '\t' << "vpop";
108      printPredicateOperand(MI, 3, O);
109      O << '\t';
110      printRegisterList(MI, 5, O);
111      return;
112    }
113  }
114
115  printInstruction(MI, O);
116 }
117
118void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
119                                  raw_ostream &O, const char *Modifier) {
120  const MCOperand &Op = MI->getOperand(OpNo);
121  if (Op.isReg()) {
122    unsigned Reg = Op.getReg();
123    O << getRegisterName(Reg);
124  } else if (Op.isImm()) {
125    assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
126    O << '#' << Op.getImm();
127  } else {
128    assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
129    assert(Op.isExpr() && "unknown operand kind in printOperand");
130    O << *Op.getExpr();
131  }
132}
133
134static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
135                       const MCAsmInfo *MAI) {
136  // Break it up into two parts that make up a shifter immediate.
137  V = ARM_AM::getSOImmVal(V);
138  assert(V != -1 && "Not a valid so_imm value!");
139
140  unsigned Imm = ARM_AM::getSOImmValImm(V);
141  unsigned Rot = ARM_AM::getSOImmValRot(V);
142
143  // Print low-level immediate formation info, per
144  // A5.1.3: "Data-processing operands - Immediate".
145  if (Rot) {
146    O << "#" << Imm << ", " << Rot;
147    // Pretty printed version.
148    if (CommentStream)
149      *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
150  } else {
151    O << "#" << Imm;
152  }
153}
154
155
156/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
157/// immediate in bits 0-7.
158void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
159                                       raw_ostream &O) {
160  const MCOperand &MO = MI->getOperand(OpNum);
161  assert(MO.isImm() && "Not a valid so_imm value!");
162  printSOImm(O, MO.getImm(), CommentStream, &MAI);
163}
164
165/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
166/// followed by an 'orr' to materialize.
167void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
168                                            raw_ostream &O) {
169  // FIXME: REMOVE this method.
170  abort();
171}
172
173// so_reg is a 4-operand unit corresponding to register forms of the A5.1
174// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
175//    REG 0   0           - e.g. R5
176//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
177//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
178void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
179                                       raw_ostream &O) {
180  const MCOperand &MO1 = MI->getOperand(OpNum);
181  const MCOperand &MO2 = MI->getOperand(OpNum+1);
182  const MCOperand &MO3 = MI->getOperand(OpNum+2);
183
184  O << getRegisterName(MO1.getReg());
185
186  // Print the shift opc.
187  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
188  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
189  if (MO2.getReg()) {
190    O << ' ' << getRegisterName(MO2.getReg());
191    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
192  } else if (ShOpc != ARM_AM::rrx) {
193    O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
194  }
195}
196
197
198void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
199                                           raw_ostream &O) {
200  const MCOperand &MO1 = MI->getOperand(Op);
201  const MCOperand &MO2 = MI->getOperand(Op+1);
202  const MCOperand &MO3 = MI->getOperand(Op+2);
203
204  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
205    printOperand(MI, Op, O);
206    return;
207  }
208
209  O << "[" << getRegisterName(MO1.getReg());
210
211  if (!MO2.getReg()) {
212    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
213      O << ", #"
214        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
215        << ARM_AM::getAM2Offset(MO3.getImm());
216    O << "]";
217    return;
218  }
219
220  O << ", "
221    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
222    << getRegisterName(MO2.getReg());
223
224  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
225    O << ", "
226    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
227    << " #" << ShImm;
228  O << "]";
229}
230
231void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
232                                                 unsigned OpNum,
233                                                 raw_ostream &O) {
234  const MCOperand &MO1 = MI->getOperand(OpNum);
235  const MCOperand &MO2 = MI->getOperand(OpNum+1);
236
237  if (!MO1.getReg()) {
238    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
239    O << '#'
240      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
241      << ImmOffs;
242    return;
243  }
244
245  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
246    << getRegisterName(MO1.getReg());
247
248  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
249    O << ", "
250    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
251    << " #" << ShImm;
252}
253
254void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
255                                           raw_ostream &O) {
256  const MCOperand &MO1 = MI->getOperand(OpNum);
257  const MCOperand &MO2 = MI->getOperand(OpNum+1);
258  const MCOperand &MO3 = MI->getOperand(OpNum+2);
259
260  O << '[' << getRegisterName(MO1.getReg());
261
262  if (MO2.getReg()) {
263    O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
264      << getRegisterName(MO2.getReg()) << ']';
265    return;
266  }
267
268  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
269    O << ", #"
270      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
271      << ImmOffs;
272  O << ']';
273}
274
275void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
276                                                 unsigned OpNum,
277                                                 raw_ostream &O) {
278  const MCOperand &MO1 = MI->getOperand(OpNum);
279  const MCOperand &MO2 = MI->getOperand(OpNum+1);
280
281  if (MO1.getReg()) {
282    O << (char)ARM_AM::getAM3Op(MO2.getImm())
283    << getRegisterName(MO1.getReg());
284    return;
285  }
286
287  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
288  O << '#'
289    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
290    << ImmOffs;
291}
292
293void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
294                                           raw_ostream &O,
295                                           const char *Modifier) {
296  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
297                                                 .getImm());
298  O << ARM_AM::getAMSubModeStr(Mode);
299}
300
301void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
302                                           raw_ostream &O,
303                                           const char *Modifier) {
304  const MCOperand &MO1 = MI->getOperand(OpNum);
305  const MCOperand &MO2 = MI->getOperand(OpNum+1);
306
307  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
308    printOperand(MI, OpNum, O);
309    return;
310  }
311
312  O << "[" << getRegisterName(MO1.getReg());
313
314  if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
315    O << ", #"
316      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
317      << ImmOffs*4;
318  }
319  O << "]";
320}
321
322void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
323                                           raw_ostream &O) {
324  const MCOperand &MO1 = MI->getOperand(OpNum);
325  const MCOperand &MO2 = MI->getOperand(OpNum+1);
326
327  O << "[" << getRegisterName(MO1.getReg());
328  if (MO2.getImm()) {
329    // FIXME: Both darwin as and GNU as violate ARM docs here.
330    O << ", :" << (MO2.getImm() << 3);
331  }
332  O << "]";
333}
334
335void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
336                                                 unsigned OpNum,
337                                                 raw_ostream &O) {
338  const MCOperand &MO = MI->getOperand(OpNum);
339  if (MO.getReg() == 0)
340    O << "!";
341  else
342    O << ", " << getRegisterName(MO.getReg());
343}
344
345void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
346                                            raw_ostream &O,
347                                            const char *Modifier) {
348  // All instructions using addrmodepc are pseudos and should have been
349  // handled explicitly in printInstructionThroughMCStreamer(). If one got
350  // here, it wasn't, so something's wrong.
351  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
352}
353
354void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
355                                                    unsigned OpNum,
356                                                    raw_ostream &O) {
357  const MCOperand &MO = MI->getOperand(OpNum);
358  uint32_t v = ~MO.getImm();
359  int32_t lsb = CountTrailingZeros_32(v);
360  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
361  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
362  O << '#' << lsb << ", #" << width;
363}
364
365void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
366                                     raw_ostream &O) {
367  unsigned val = MI->getOperand(OpNum).getImm();
368  O << ARM_MB::MemBOptToString(val);
369}
370
371void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
372                                          raw_ostream &O) {
373  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
374  ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
375  switch (Opc) {
376  case ARM_AM::no_shift:
377    return;
378  case ARM_AM::lsl:
379    O << ", lsl #";
380    break;
381  case ARM_AM::asr:
382    O << ", asr #";
383    break;
384  default:
385    assert(0 && "unexpected shift opcode for shift immediate operand");
386  }
387  O << ARM_AM::getSORegOffset(ShiftOp);
388}
389
390void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
391                                       raw_ostream &O) {
392  O << "{";
393  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
394    if (i != OpNum) O << ", ";
395    O << getRegisterName(MI->getOperand(i).getReg());
396  }
397  O << "}";
398}
399
400void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
401                                        raw_ostream &O) {
402  const MCOperand &Op = MI->getOperand(OpNum);
403  if (Op.getImm())
404    O << "be";
405  else
406    O << "le";
407}
408
409void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
410                                           raw_ostream &O) {
411  const MCOperand &Op = MI->getOperand(OpNum);
412  unsigned option = Op.getImm();
413  unsigned mode = option & 31;
414  bool changemode = option >> 5 & 1;
415  unsigned AIF = option >> 6 & 7;
416  unsigned imod = option >> 9 & 3;
417  if (imod == 2)
418    O << "ie";
419  else if (imod == 3)
420    O << "id";
421  O << '\t';
422  if (imod > 1) {
423    if (AIF & 4) O << 'a';
424    if (AIF & 2) O << 'i';
425    if (AIF & 1) O << 'f';
426    if (AIF > 0 && changemode) O << ", ";
427  }
428  if (changemode)
429    O << '#' << mode;
430}
431
432void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
433                                         raw_ostream &O) {
434  const MCOperand &Op = MI->getOperand(OpNum);
435  unsigned Mask = Op.getImm();
436  if (Mask) {
437    O << '_';
438    if (Mask & 8) O << 'f';
439    if (Mask & 4) O << 's';
440    if (Mask & 2) O << 'x';
441    if (Mask & 1) O << 'c';
442  }
443}
444
445void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
446                                         raw_ostream &O) {
447  const MCOperand &Op = MI->getOperand(OpNum);
448  O << '#';
449  if (Op.getImm() < 0)
450    O << '-' << (-Op.getImm() - 1);
451  else
452    O << Op.getImm();
453}
454
455void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
456                                           raw_ostream &O) {
457  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
458  if (CC != ARMCC::AL)
459    O << ARMCondCodeToString(CC);
460}
461
462void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
463                                                    unsigned OpNum,
464                                                    raw_ostream &O) {
465  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
466  O << ARMCondCodeToString(CC);
467}
468
469void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
470                                              raw_ostream &O) {
471  if (MI->getOperand(OpNum).getReg()) {
472    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
473           "Expect ARM CPSR register!");
474    O << 's';
475  }
476}
477
478void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
479                                          raw_ostream &O) {
480  O << MI->getOperand(OpNum).getImm();
481}
482
483void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
484                                  raw_ostream &O) {
485  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
486}
487
488void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
489                                            raw_ostream &O) {
490  O << "#" <<  MI->getOperand(OpNum).getImm() * 4;
491}
492
493void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
494                                      raw_ostream &O) {
495  // (3 - the number of trailing zeros) is the number of then / else.
496  unsigned Mask = MI->getOperand(OpNum).getImm();
497  unsigned CondBit0 = Mask >> 4 & 1;
498  unsigned NumTZ = CountTrailingZeros_32(Mask);
499  assert(NumTZ <= 3 && "Invalid IT mask!");
500  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
501    bool T = ((Mask >> Pos) & 1) == CondBit0;
502    if (T)
503      O << 't';
504    else
505      O << 'e';
506  }
507}
508
509void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
510                                                 raw_ostream &O) {
511  const MCOperand &MO1 = MI->getOperand(Op);
512  const MCOperand &MO2 = MI->getOperand(Op+1);
513  O << "[" << getRegisterName(MO1.getReg());
514  O << ", " << getRegisterName(MO2.getReg()) << "]";
515}
516
517void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
518                                                  raw_ostream &O,
519                                                  unsigned Scale) {
520  const MCOperand &MO1 = MI->getOperand(Op);
521  const MCOperand &MO2 = MI->getOperand(Op+1);
522  const MCOperand &MO3 = MI->getOperand(Op+2);
523
524  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
525    printOperand(MI, Op, O);
526    return;
527  }
528
529  O << "[" << getRegisterName(MO1.getReg());
530  if (MO3.getReg())
531    O << ", " << getRegisterName(MO3.getReg());
532  else if (unsigned ImmOffs = MO2.getImm())
533    O << ", #" << ImmOffs * Scale;
534  O << "]";
535}
536
537void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
538                                                 raw_ostream &O) {
539  printThumbAddrModeRI5Operand(MI, Op, O, 1);
540}
541
542void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
543                                                 raw_ostream &O) {
544  printThumbAddrModeRI5Operand(MI, Op, O, 2);
545}
546
547void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
548                                                 raw_ostream &O) {
549  printThumbAddrModeRI5Operand(MI, Op, O, 4);
550}
551
552void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
553                                                 raw_ostream &O) {
554  const MCOperand &MO1 = MI->getOperand(Op);
555  const MCOperand &MO2 = MI->getOperand(Op+1);
556  O << "[" << getRegisterName(MO1.getReg());
557  if (unsigned ImmOffs = MO2.getImm())
558    O << ", #" << ImmOffs*4;
559  O << "]";
560}
561
562void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
563                                     raw_ostream &O) {
564  O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
565  if (MI->getOpcode() == ARM::t2TBH)
566    O << ", lsl #1";
567  O << ']';
568}
569
570// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
571// register with shift forms.
572// REG 0   0           - e.g. R5
573// REG IMM, SH_OPC     - e.g. R5, LSL #3
574void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
575                                      raw_ostream &O) {
576  const MCOperand &MO1 = MI->getOperand(OpNum);
577  const MCOperand &MO2 = MI->getOperand(OpNum+1);
578
579  unsigned Reg = MO1.getReg();
580  O << getRegisterName(Reg);
581
582  // Print the shift opc.
583  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
584  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
585  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
586  if (ShOpc != ARM_AM::rrx)
587    O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
588}
589
590void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
591                                               raw_ostream &O) {
592  const MCOperand &MO1 = MI->getOperand(OpNum);
593  const MCOperand &MO2 = MI->getOperand(OpNum+1);
594
595  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
596    printOperand(MI, OpNum, O);
597    return;
598  }
599
600  O << "[" << getRegisterName(MO1.getReg());
601
602  int32_t OffImm = (int32_t)MO2.getImm();
603  bool isSub = OffImm < 0;
604  // Special value for #-0. All others are normal.
605  if (OffImm == INT32_MIN)
606    OffImm = 0;
607  if (isSub)
608    O << ", #-" << -OffImm;
609  else if (OffImm > 0)
610    O << ", #" << OffImm;
611  O << "]";
612}
613
614void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
615                                                unsigned OpNum,
616                                                raw_ostream &O) {
617  const MCOperand &MO1 = MI->getOperand(OpNum);
618  const MCOperand &MO2 = MI->getOperand(OpNum+1);
619
620  O << "[" << getRegisterName(MO1.getReg());
621
622  int32_t OffImm = (int32_t)MO2.getImm();
623  // Don't print +0.
624  if (OffImm < 0)
625    O << ", #-" << -OffImm;
626  else if (OffImm > 0)
627    O << ", #" << OffImm;
628  O << "]";
629}
630
631void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
632                                                  unsigned OpNum,
633                                                  raw_ostream &O) {
634  const MCOperand &MO1 = MI->getOperand(OpNum);
635  const MCOperand &MO2 = MI->getOperand(OpNum+1);
636
637  O << "[" << getRegisterName(MO1.getReg());
638
639  int32_t OffImm = (int32_t)MO2.getImm() / 4;
640  // Don't print +0.
641  if (OffImm < 0)
642    O << ", #-" << -OffImm * 4;
643  else if (OffImm > 0)
644    O << ", #" << OffImm * 4;
645  O << "]";
646}
647
648void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
649                                                      unsigned OpNum,
650                                                      raw_ostream &O) {
651  const MCOperand &MO1 = MI->getOperand(OpNum);
652  int32_t OffImm = (int32_t)MO1.getImm();
653  // Don't print +0.
654  if (OffImm < 0)
655    O << "#-" << -OffImm;
656  else if (OffImm > 0)
657    O << "#" << OffImm;
658}
659
660void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
661                                                        unsigned OpNum,
662                                                        raw_ostream &O) {
663  const MCOperand &MO1 = MI->getOperand(OpNum);
664  int32_t OffImm = (int32_t)MO1.getImm() / 4;
665  // Don't print +0.
666  if (OffImm < 0)
667    O << "#-" << -OffImm * 4;
668  else if (OffImm > 0)
669    O << "#" << OffImm * 4;
670}
671
672void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
673                                                 unsigned OpNum,
674                                                 raw_ostream &O) {
675  const MCOperand &MO1 = MI->getOperand(OpNum);
676  const MCOperand &MO2 = MI->getOperand(OpNum+1);
677  const MCOperand &MO3 = MI->getOperand(OpNum+2);
678
679  O << "[" << getRegisterName(MO1.getReg());
680
681  assert(MO2.getReg() && "Invalid so_reg load / store address!");
682  O << ", " << getRegisterName(MO2.getReg());
683
684  unsigned ShAmt = MO3.getImm();
685  if (ShAmt) {
686    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
687    O << ", lsl #" << ShAmt;
688  }
689  O << "]";
690}
691
692void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
693                                           raw_ostream &O) {
694  O << '#' << (float)MI->getOperand(OpNum).getFPImm();
695}
696
697void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
698                                           raw_ostream &O) {
699  O << '#' << MI->getOperand(OpNum).getFPImm();
700}
701
702void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
703                                            raw_ostream &O) {
704  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
705  unsigned EltBits;
706  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
707  O << "#0x" << utohexstr(Val);
708}
709