ARMInstPrinter.cpp revision e90ac9bce9aa6de288568df9bf6133c08534ae2f 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMInstPrinter.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/Support/raw_ostream.h"
22using namespace llvm;
23
24#define GET_INSTRUCTION_NAME
25#include "ARMGenAsmWriter.inc"
26
27/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
28///
29/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
30static unsigned translateShiftImm(unsigned imm) {
31  if (imm == 0)
32    return 32;
33  return imm;
34}
35
36
37ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
38                               const MCSubtargetInfo &STI) :
39  MCInstPrinter(MAI) {
40  // Initialize the set of available features.
41  setAvailableFeatures(STI.getFeatureBits());
42}
43
44StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
45  return getInstructionName(Opcode);
46}
47
48void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
49  OS << getRegisterName(RegNo);
50}
51
52void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53                               StringRef Annot) {
54  unsigned Opcode = MI->getOpcode();
55
56  // Check for MOVs and print canonical forms, instead.
57  if (Opcode == ARM::MOVsr) {
58    // FIXME: Thumb variants?
59    const MCOperand &Dst = MI->getOperand(0);
60    const MCOperand &MO1 = MI->getOperand(1);
61    const MCOperand &MO2 = MI->getOperand(2);
62    const MCOperand &MO3 = MI->getOperand(3);
63
64    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
65    printSBitModifierOperand(MI, 6, O);
66    printPredicateOperand(MI, 4, O);
67
68    O << '\t' << getRegisterName(Dst.getReg())
69      << ", " << getRegisterName(MO1.getReg());
70
71    O << ", " << getRegisterName(MO2.getReg());
72    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
73    printAnnotation(O, Annot);
74    return;
75  }
76
77  if (Opcode == ARM::MOVsi) {
78    // FIXME: Thumb variants?
79    const MCOperand &Dst = MI->getOperand(0);
80    const MCOperand &MO1 = MI->getOperand(1);
81    const MCOperand &MO2 = MI->getOperand(2);
82
83    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
84    printSBitModifierOperand(MI, 5, O);
85    printPredicateOperand(MI, 3, O);
86
87    O << '\t' << getRegisterName(Dst.getReg())
88      << ", " << getRegisterName(MO1.getReg());
89
90    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
91      printAnnotation(O, Annot);
92      return;
93    }
94
95    O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
96    printAnnotation(O, Annot);
97    return;
98  }
99
100
101  // A8.6.123 PUSH
102  if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
103      MI->getOperand(0).getReg() == ARM::SP &&
104      MI->getNumOperands() > 5) {
105    // Should only print PUSH if there are at least two registers in the list.
106    O << '\t' << "push";
107    printPredicateOperand(MI, 2, O);
108    if (Opcode == ARM::t2STMDB_UPD)
109      O << ".w";
110    O << '\t';
111    printRegisterList(MI, 4, O);
112    printAnnotation(O, Annot);
113    return;
114  }
115  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
116      MI->getOperand(3).getImm() == -4) {
117    O << '\t' << "push";
118    printPredicateOperand(MI, 4, O);
119    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
120    printAnnotation(O, Annot);
121    return;
122  }
123
124  // A8.6.122 POP
125  if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
126      MI->getOperand(0).getReg() == ARM::SP &&
127      MI->getNumOperands() > 5) {
128    // Should only print POP if there are at least two registers in the list.
129    O << '\t' << "pop";
130    printPredicateOperand(MI, 2, O);
131    if (Opcode == ARM::t2LDMIA_UPD)
132      O << ".w";
133    O << '\t';
134    printRegisterList(MI, 4, O);
135    printAnnotation(O, Annot);
136    return;
137  }
138  if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
139      MI->getOperand(4).getImm() == 4) {
140    O << '\t' << "pop";
141    printPredicateOperand(MI, 5, O);
142    O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
143    printAnnotation(O, Annot);
144    return;
145  }
146
147
148  // A8.6.355 VPUSH
149  if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
150      MI->getOperand(0).getReg() == ARM::SP) {
151    O << '\t' << "vpush";
152    printPredicateOperand(MI, 2, O);
153    O << '\t';
154    printRegisterList(MI, 4, O);
155    printAnnotation(O, Annot);
156    return;
157  }
158
159  // A8.6.354 VPOP
160  if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
161      MI->getOperand(0).getReg() == ARM::SP) {
162    O << '\t' << "vpop";
163    printPredicateOperand(MI, 2, O);
164    O << '\t';
165    printRegisterList(MI, 4, O);
166    printAnnotation(O, Annot);
167    return;
168  }
169
170  if (Opcode == ARM::tLDMIA) {
171    bool Writeback = true;
172    unsigned BaseReg = MI->getOperand(0).getReg();
173    for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
174      if (MI->getOperand(i).getReg() == BaseReg)
175        Writeback = false;
176    }
177
178    O << "\tldm";
179
180    printPredicateOperand(MI, 1, O);
181    O << '\t' << getRegisterName(BaseReg);
182    if (Writeback) O << "!";
183    O << ", ";
184    printRegisterList(MI, 3, O);
185    printAnnotation(O, Annot);
186    return;
187  }
188
189  // Thumb1 NOP
190  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
191      MI->getOperand(1).getReg() == ARM::R8) {
192    O << "\tnop";
193    printPredicateOperand(MI, 2, O);
194    printAnnotation(O, Annot);
195    return;
196  }
197
198  printInstruction(MI, O);
199  printAnnotation(O, Annot);
200}
201
202void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
203                                  raw_ostream &O) {
204  const MCOperand &Op = MI->getOperand(OpNo);
205  if (Op.isReg()) {
206    unsigned Reg = Op.getReg();
207    O << getRegisterName(Reg);
208  } else if (Op.isImm()) {
209    O << '#' << Op.getImm();
210  } else {
211    assert(Op.isExpr() && "unknown operand kind in printOperand");
212    // If a symbolic branch target was added as a constant expression then print
213    // that address in hex.
214    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
215    int64_t Address;
216    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
217      O << "0x";
218      O.write_hex(Address);
219    }
220    else {
221      // Otherwise, just print the expression.
222      O << *Op.getExpr();
223    }
224  }
225}
226
227void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
228                                       raw_ostream &O) {
229  const MCOperand &MO1 = MI->getOperand(OpNum);
230  if (MO1.isExpr())
231    O << *MO1.getExpr();
232  else if (MO1.isImm())
233    O << "[pc, #" << MO1.getImm() << "]";
234  else
235    llvm_unreachable("Unknown LDR label operand?");
236}
237
238// so_reg is a 4-operand unit corresponding to register forms of the A5.1
239// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
240//    REG 0   0           - e.g. R5
241//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
242//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
243void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
244                                       raw_ostream &O) {
245  const MCOperand &MO1 = MI->getOperand(OpNum);
246  const MCOperand &MO2 = MI->getOperand(OpNum+1);
247  const MCOperand &MO3 = MI->getOperand(OpNum+2);
248
249  O << getRegisterName(MO1.getReg());
250
251  // Print the shift opc.
252  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
253  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
254  if (ShOpc == ARM_AM::rrx)
255    return;
256
257  O << ' ' << getRegisterName(MO2.getReg());
258  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
259}
260
261void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
262                                       raw_ostream &O) {
263  const MCOperand &MO1 = MI->getOperand(OpNum);
264  const MCOperand &MO2 = MI->getOperand(OpNum+1);
265
266  O << getRegisterName(MO1.getReg());
267
268  // Print the shift opc.
269  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
270  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
271  if (ShOpc == ARM_AM::rrx)
272    return;
273  O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
274}
275
276
277//===--------------------------------------------------------------------===//
278// Addressing Mode #2
279//===--------------------------------------------------------------------===//
280
281void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
282                                                raw_ostream &O) {
283  const MCOperand &MO1 = MI->getOperand(Op);
284  const MCOperand &MO2 = MI->getOperand(Op+1);
285  const MCOperand &MO3 = MI->getOperand(Op+2);
286
287  O << "[" << getRegisterName(MO1.getReg());
288
289  if (!MO2.getReg()) {
290    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
291      O << ", #"
292        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
293        << ARM_AM::getAM2Offset(MO3.getImm());
294    O << "]";
295    return;
296  }
297
298  O << ", "
299    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
300    << getRegisterName(MO2.getReg());
301
302  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
303    O << ", "
304    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
305    << " #" << ShImm;
306  O << "]";
307}
308
309void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
310                                         raw_ostream &O) {
311  const MCOperand &MO1 = MI->getOperand(Op);
312  const MCOperand &MO2 = MI->getOperand(Op+1);
313  const MCOperand &MO3 = MI->getOperand(Op+2);
314
315  O << "[" << getRegisterName(MO1.getReg()) << "], ";
316
317  if (!MO2.getReg()) {
318    unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
319    O << '#'
320      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
321      << ImmOffs;
322    return;
323  }
324
325  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
326    << getRegisterName(MO2.getReg());
327
328  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
329    O << ", "
330    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
331    << " #" << ShImm;
332}
333
334void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
335                                           raw_ostream &O) {
336  const MCOperand &MO1 = MI->getOperand(Op);
337  const MCOperand &MO2 = MI->getOperand(Op+1);
338  O << "[" << getRegisterName(MO1.getReg()) << ", "
339    << getRegisterName(MO2.getReg()) << "]";
340}
341
342void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
343                                           raw_ostream &O) {
344  const MCOperand &MO1 = MI->getOperand(Op);
345  const MCOperand &MO2 = MI->getOperand(Op+1);
346  O << "[" << getRegisterName(MO1.getReg()) << ", "
347    << getRegisterName(MO2.getReg()) << ", lsl #1]";
348}
349
350void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
351                                           raw_ostream &O) {
352  const MCOperand &MO1 = MI->getOperand(Op);
353
354  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
355    printOperand(MI, Op, O);
356    return;
357  }
358
359  const MCOperand &MO3 = MI->getOperand(Op+2);
360  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
361
362  if (IdxMode == ARMII::IndexModePost) {
363    printAM2PostIndexOp(MI, Op, O);
364    return;
365  }
366  printAM2PreOrOffsetIndexOp(MI, Op, O);
367}
368
369void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
370                                                 unsigned OpNum,
371                                                 raw_ostream &O) {
372  const MCOperand &MO1 = MI->getOperand(OpNum);
373  const MCOperand &MO2 = MI->getOperand(OpNum+1);
374
375  if (!MO1.getReg()) {
376    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
377    O << '#'
378      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
379      << ImmOffs;
380    return;
381  }
382
383  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
384    << getRegisterName(MO1.getReg());
385
386  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
387    O << ", "
388    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
389    << " #" << ShImm;
390}
391
392//===--------------------------------------------------------------------===//
393// Addressing Mode #3
394//===--------------------------------------------------------------------===//
395
396void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
397                                         raw_ostream &O) {
398  const MCOperand &MO1 = MI->getOperand(Op);
399  const MCOperand &MO2 = MI->getOperand(Op+1);
400  const MCOperand &MO3 = MI->getOperand(Op+2);
401
402  O << "[" << getRegisterName(MO1.getReg()) << "], ";
403
404  if (MO2.getReg()) {
405    O << (char)ARM_AM::getAM3Op(MO3.getImm())
406    << getRegisterName(MO2.getReg());
407    return;
408  }
409
410  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
411  O << '#'
412    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
413    << ImmOffs;
414}
415
416void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
417                                                raw_ostream &O) {
418  const MCOperand &MO1 = MI->getOperand(Op);
419  const MCOperand &MO2 = MI->getOperand(Op+1);
420  const MCOperand &MO3 = MI->getOperand(Op+2);
421
422  O << '[' << getRegisterName(MO1.getReg());
423
424  if (MO2.getReg()) {
425    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
426      << getRegisterName(MO2.getReg()) << ']';
427    return;
428  }
429
430  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
431    O << ", #"
432      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
433      << ImmOffs;
434  O << ']';
435}
436
437void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
438                                           raw_ostream &O) {
439  const MCOperand &MO3 = MI->getOperand(Op+2);
440  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
441
442  if (IdxMode == ARMII::IndexModePost) {
443    printAM3PostIndexOp(MI, Op, O);
444    return;
445  }
446  printAM3PreOrOffsetIndexOp(MI, Op, O);
447}
448
449void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
450                                                 unsigned OpNum,
451                                                 raw_ostream &O) {
452  const MCOperand &MO1 = MI->getOperand(OpNum);
453  const MCOperand &MO2 = MI->getOperand(OpNum+1);
454
455  if (MO1.getReg()) {
456    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
457      << getRegisterName(MO1.getReg());
458    return;
459  }
460
461  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
462  O << '#'
463    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
464    << ImmOffs;
465}
466
467void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
468                                             unsigned OpNum,
469                                             raw_ostream &O) {
470  const MCOperand &MO = MI->getOperand(OpNum);
471  unsigned Imm = MO.getImm();
472  O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
473}
474
475void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
476                                            raw_ostream &O) {
477  const MCOperand &MO1 = MI->getOperand(OpNum);
478  const MCOperand &MO2 = MI->getOperand(OpNum+1);
479
480  O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
481}
482
483void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
484                                             unsigned OpNum,
485                                             raw_ostream &O) {
486  const MCOperand &MO = MI->getOperand(OpNum);
487  unsigned Imm = MO.getImm();
488  O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
489}
490
491
492void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
493                                           raw_ostream &O) {
494  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
495                                                 .getImm());
496  O << ARM_AM::getAMSubModeStr(Mode);
497}
498
499void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
500                                           raw_ostream &O) {
501  const MCOperand &MO1 = MI->getOperand(OpNum);
502  const MCOperand &MO2 = MI->getOperand(OpNum+1);
503
504  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
505    printOperand(MI, OpNum, O);
506    return;
507  }
508
509  O << "[" << getRegisterName(MO1.getReg());
510
511  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
512  unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
513  if (ImmOffs || Op == ARM_AM::sub) {
514    O << ", #"
515      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
516      << ImmOffs * 4;
517  }
518  O << "]";
519}
520
521void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
522                                           raw_ostream &O) {
523  const MCOperand &MO1 = MI->getOperand(OpNum);
524  const MCOperand &MO2 = MI->getOperand(OpNum+1);
525
526  O << "[" << getRegisterName(MO1.getReg());
527  if (MO2.getImm()) {
528    // FIXME: Both darwin as and GNU as violate ARM docs here.
529    O << ", :" << (MO2.getImm() << 3);
530  }
531  O << "]";
532}
533
534void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
535                                           raw_ostream &O) {
536  const MCOperand &MO1 = MI->getOperand(OpNum);
537  O << "[" << getRegisterName(MO1.getReg()) << "]";
538}
539
540void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
541                                                 unsigned OpNum,
542                                                 raw_ostream &O) {
543  const MCOperand &MO = MI->getOperand(OpNum);
544  if (MO.getReg() == 0)
545    O << "!";
546  else
547    O << ", " << getRegisterName(MO.getReg());
548}
549
550void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
551                                                    unsigned OpNum,
552                                                    raw_ostream &O) {
553  const MCOperand &MO = MI->getOperand(OpNum);
554  uint32_t v = ~MO.getImm();
555  int32_t lsb = CountTrailingZeros_32(v);
556  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
557  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
558  O << '#' << lsb << ", #" << width;
559}
560
561void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
562                                     raw_ostream &O) {
563  unsigned val = MI->getOperand(OpNum).getImm();
564  O << ARM_MB::MemBOptToString(val);
565}
566
567void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
568                                          raw_ostream &O) {
569  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
570  bool isASR = (ShiftOp & (1 << 5)) != 0;
571  unsigned Amt = ShiftOp & 0x1f;
572  if (isASR)
573    O << ", asr #" << (Amt == 0 ? 32 : Amt);
574  else if (Amt)
575    O << ", lsl #" << Amt;
576}
577
578void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
579                                         raw_ostream &O) {
580  unsigned Imm = MI->getOperand(OpNum).getImm();
581  if (Imm == 0)
582    return;
583  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
584  O << ", lsl #" << Imm;
585}
586
587void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
588                                         raw_ostream &O) {
589  unsigned Imm = MI->getOperand(OpNum).getImm();
590  // A shift amount of 32 is encoded as 0.
591  if (Imm == 0)
592    Imm = 32;
593  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
594  O << ", asr #" << Imm;
595}
596
597void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
598                                       raw_ostream &O) {
599  O << "{";
600  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
601    if (i != OpNum) O << ", ";
602    O << getRegisterName(MI->getOperand(i).getReg());
603  }
604  O << "}";
605}
606
607void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
608                                        raw_ostream &O) {
609  const MCOperand &Op = MI->getOperand(OpNum);
610  if (Op.getImm())
611    O << "be";
612  else
613    O << "le";
614}
615
616void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
617                                  raw_ostream &O) {
618  const MCOperand &Op = MI->getOperand(OpNum);
619  O << ARM_PROC::IModToString(Op.getImm());
620}
621
622void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
623                                   raw_ostream &O) {
624  const MCOperand &Op = MI->getOperand(OpNum);
625  unsigned IFlags = Op.getImm();
626  for (int i=2; i >= 0; --i)
627    if (IFlags & (1 << i))
628      O << ARM_PROC::IFlagsToString(1 << i);
629
630  if (IFlags == 0)
631    O << "none";
632}
633
634void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
635                                         raw_ostream &O) {
636  const MCOperand &Op = MI->getOperand(OpNum);
637  unsigned SpecRegRBit = Op.getImm() >> 4;
638  unsigned Mask = Op.getImm() & 0xf;
639
640  if (getAvailableFeatures() & ARM::FeatureMClass) {
641    switch (Op.getImm()) {
642    default: assert(0 && "Unexpected mask value!");
643    case 0: O << "apsr"; return;
644    case 1: O << "iapsr"; return;
645    case 2: O << "eapsr"; return;
646    case 3: O << "xpsr"; return;
647    case 5: O << "ipsr"; return;
648    case 6: O << "epsr"; return;
649    case 7: O << "iepsr"; return;
650    case 8: O << "msp"; return;
651    case 9: O << "psp"; return;
652    case 16: O << "primask"; return;
653    case 17: O << "basepri"; return;
654    case 18: O << "basepri_max"; return;
655    case 19: O << "faultmask"; return;
656    case 20: O << "control"; return;
657    }
658  }
659
660  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
661  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
662  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
663    O << "APSR_";
664    switch (Mask) {
665    default: assert(0);
666    case 4:  O << "g"; return;
667    case 8:  O << "nzcvq"; return;
668    case 12: O << "nzcvqg"; return;
669    }
670    llvm_unreachable("Unexpected mask value!");
671  }
672
673  if (SpecRegRBit)
674    O << "SPSR";
675  else
676    O << "CPSR";
677
678  if (Mask) {
679    O << '_';
680    if (Mask & 8) O << 'f';
681    if (Mask & 4) O << 's';
682    if (Mask & 2) O << 'x';
683    if (Mask & 1) O << 'c';
684  }
685}
686
687void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
688                                           raw_ostream &O) {
689  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
690  if (CC != ARMCC::AL)
691    O << ARMCondCodeToString(CC);
692}
693
694void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
695                                                    unsigned OpNum,
696                                                    raw_ostream &O) {
697  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
698  O << ARMCondCodeToString(CC);
699}
700
701void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
702                                              raw_ostream &O) {
703  if (MI->getOperand(OpNum).getReg()) {
704    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
705           "Expect ARM CPSR register!");
706    O << 's';
707  }
708}
709
710void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
711                                          raw_ostream &O) {
712  O << MI->getOperand(OpNum).getImm();
713}
714
715void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
716                                     raw_ostream &O) {
717  O << "p" << MI->getOperand(OpNum).getImm();
718}
719
720void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
721                                     raw_ostream &O) {
722  O << "c" << MI->getOperand(OpNum).getImm();
723}
724
725void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
726                                          raw_ostream &O) {
727  O << "{" << MI->getOperand(OpNum).getImm() << "}";
728}
729
730void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
731                                  raw_ostream &O) {
732  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
733}
734
735void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
736                                            raw_ostream &O) {
737  O << "#" << MI->getOperand(OpNum).getImm() * 4;
738}
739
740void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
741                                     raw_ostream &O) {
742  unsigned Imm = MI->getOperand(OpNum).getImm();
743  O << "#" << (Imm == 0 ? 32 : Imm);
744}
745
746void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
747                                      raw_ostream &O) {
748  // (3 - the number of trailing zeros) is the number of then / else.
749  unsigned Mask = MI->getOperand(OpNum).getImm();
750  unsigned CondBit0 = Mask >> 4 & 1;
751  unsigned NumTZ = CountTrailingZeros_32(Mask);
752  assert(NumTZ <= 3 && "Invalid IT mask!");
753  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
754    bool T = ((Mask >> Pos) & 1) == CondBit0;
755    if (T)
756      O << 't';
757    else
758      O << 'e';
759  }
760}
761
762void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
763                                                 raw_ostream &O) {
764  const MCOperand &MO1 = MI->getOperand(Op);
765  const MCOperand &MO2 = MI->getOperand(Op + 1);
766
767  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
768    printOperand(MI, Op, O);
769    return;
770  }
771
772  O << "[" << getRegisterName(MO1.getReg());
773  if (unsigned RegNum = MO2.getReg())
774    O << ", " << getRegisterName(RegNum);
775  O << "]";
776}
777
778void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
779                                                    unsigned Op,
780                                                    raw_ostream &O,
781                                                    unsigned Scale) {
782  const MCOperand &MO1 = MI->getOperand(Op);
783  const MCOperand &MO2 = MI->getOperand(Op + 1);
784
785  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
786    printOperand(MI, Op, O);
787    return;
788  }
789
790  O << "[" << getRegisterName(MO1.getReg());
791  if (unsigned ImmOffs = MO2.getImm())
792    O << ", #" << ImmOffs * Scale;
793  O << "]";
794}
795
796void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
797                                                     unsigned Op,
798                                                     raw_ostream &O) {
799  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
800}
801
802void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
803                                                     unsigned Op,
804                                                     raw_ostream &O) {
805  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
806}
807
808void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
809                                                     unsigned Op,
810                                                     raw_ostream &O) {
811  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
812}
813
814void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
815                                                 raw_ostream &O) {
816  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
817}
818
819// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
820// register with shift forms.
821// REG 0   0           - e.g. R5
822// REG IMM, SH_OPC     - e.g. R5, LSL #3
823void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
824                                      raw_ostream &O) {
825  const MCOperand &MO1 = MI->getOperand(OpNum);
826  const MCOperand &MO2 = MI->getOperand(OpNum+1);
827
828  unsigned Reg = MO1.getReg();
829  O << getRegisterName(Reg);
830
831  // Print the shift opc.
832  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
833  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
834  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
835  if (ShOpc != ARM_AM::rrx)
836    O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
837}
838
839void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
840                                               raw_ostream &O) {
841  const MCOperand &MO1 = MI->getOperand(OpNum);
842  const MCOperand &MO2 = MI->getOperand(OpNum+1);
843
844  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
845    printOperand(MI, OpNum, O);
846    return;
847  }
848
849  O << "[" << getRegisterName(MO1.getReg());
850
851  int32_t OffImm = (int32_t)MO2.getImm();
852  bool isSub = OffImm < 0;
853  // Special value for #-0. All others are normal.
854  if (OffImm == INT32_MIN)
855    OffImm = 0;
856  if (isSub)
857    O << ", #-" << -OffImm;
858  else if (OffImm > 0)
859    O << ", #" << OffImm;
860  O << "]";
861}
862
863void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
864                                                unsigned OpNum,
865                                                raw_ostream &O) {
866  const MCOperand &MO1 = MI->getOperand(OpNum);
867  const MCOperand &MO2 = MI->getOperand(OpNum+1);
868
869  O << "[" << getRegisterName(MO1.getReg());
870
871  int32_t OffImm = (int32_t)MO2.getImm();
872  // Don't print +0.
873  if (OffImm == INT32_MIN)
874    O << ", #-0";
875  else if (OffImm < 0)
876    O << ", #-" << -OffImm;
877  else if (OffImm > 0)
878    O << ", #" << OffImm;
879  O << "]";
880}
881
882void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
883                                                  unsigned OpNum,
884                                                  raw_ostream &O) {
885  const MCOperand &MO1 = MI->getOperand(OpNum);
886  const MCOperand &MO2 = MI->getOperand(OpNum+1);
887
888  O << "[" << getRegisterName(MO1.getReg());
889
890  int32_t OffImm = (int32_t)MO2.getImm() / 4;
891  // Don't print +0.
892  if (OffImm < 0)
893    O << ", #-" << -OffImm * 4;
894  else if (OffImm > 0)
895    O << ", #" << OffImm * 4;
896  O << "]";
897}
898
899void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
900                                                       unsigned OpNum,
901                                                       raw_ostream &O) {
902  const MCOperand &MO1 = MI->getOperand(OpNum);
903  const MCOperand &MO2 = MI->getOperand(OpNum+1);
904
905  O << "[" << getRegisterName(MO1.getReg());
906  if (MO2.getImm())
907    O << ", #" << MO2.getImm() * 4;
908  O << "]";
909}
910
911void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
912                                                      unsigned OpNum,
913                                                      raw_ostream &O) {
914  const MCOperand &MO1 = MI->getOperand(OpNum);
915  int32_t OffImm = (int32_t)MO1.getImm();
916  // Don't print +0.
917  if (OffImm < 0)
918    O << ", #-" << -OffImm;
919  else
920    O << ", #" << OffImm;
921}
922
923void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
924                                                        unsigned OpNum,
925                                                        raw_ostream &O) {
926  const MCOperand &MO1 = MI->getOperand(OpNum);
927  int32_t OffImm = (int32_t)MO1.getImm() / 4;
928  // Don't print +0.
929  if (OffImm != 0) {
930    O << ", ";
931    if (OffImm < 0)
932      O << "#-" << -OffImm * 4;
933    else if (OffImm > 0)
934      O << "#" << OffImm * 4;
935  }
936}
937
938void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
939                                                 unsigned OpNum,
940                                                 raw_ostream &O) {
941  const MCOperand &MO1 = MI->getOperand(OpNum);
942  const MCOperand &MO2 = MI->getOperand(OpNum+1);
943  const MCOperand &MO3 = MI->getOperand(OpNum+2);
944
945  O << "[" << getRegisterName(MO1.getReg());
946
947  assert(MO2.getReg() && "Invalid so_reg load / store address!");
948  O << ", " << getRegisterName(MO2.getReg());
949
950  unsigned ShAmt = MO3.getImm();
951  if (ShAmt) {
952    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
953    O << ", lsl #" << ShAmt;
954  }
955  O << "]";
956}
957
958void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
959                                       raw_ostream &O) {
960  const MCOperand &MO = MI->getOperand(OpNum);
961  O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
962}
963
964void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
965                                            raw_ostream &O) {
966  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
967  unsigned EltBits;
968  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
969  O << "#0x";
970  O.write_hex(Val);
971}
972
973void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
974                                            raw_ostream &O) {
975  unsigned Imm = MI->getOperand(OpNum).getImm();
976  O << "#" << Imm + 1;
977}
978
979void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
980                                        raw_ostream &O) {
981  unsigned Imm = MI->getOperand(OpNum).getImm();
982  if (Imm == 0)
983    return;
984  O << ", ror #";
985  switch (Imm) {
986  default: assert (0 && "illegal ror immediate!");
987  case 1: O << "8"; break;
988  case 2: O << "16"; break;
989  case 3: O << "24"; break;
990  }
991}
992
993void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
994                                      raw_ostream &O) {
995  O << "[" << MI->getOperand(OpNum).getImm() << "]";
996}
997
998void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
999                                        raw_ostream &O) {
1000  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1001}
1002
1003void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1004                                        raw_ostream &O) {
1005  // Normally, it's not safe to use register enum values directly with
1006  // addition to get the next register, but for VFP registers, the
1007  // sort order is guaranteed because they're all of the form D<n>.
1008  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1009    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
1010}
1011
1012void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1013                                          raw_ostream &O) {
1014  // Normally, it's not safe to use register enum values directly with
1015  // addition to get the next register, but for VFP registers, the
1016  // sort order is guaranteed because they're all of the form D<n>.
1017  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1018    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1019    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1020}
1021
1022void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1023                                         raw_ostream &O) {
1024  // Normally, it's not safe to use register enum values directly with
1025  // addition to get the next register, but for VFP registers, the
1026  // sort order is guaranteed because they're all of the form D<n>.
1027  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1028    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1029    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1030    << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1031}
1032
1033void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1034                                                unsigned OpNum,
1035                                                raw_ostream &O) {
1036  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1037}
1038
1039void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1040                                                unsigned OpNum,
1041                                                raw_ostream &O) {
1042  // Normally, it's not safe to use register enum values directly with
1043  // addition to get the next register, but for VFP registers, the
1044  // sort order is guaranteed because they're all of the form D<n>.
1045  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1046    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
1047}
1048
1049void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1050                                              raw_ostream &O) {
1051  // Normally, it's not safe to use register enum values directly with
1052  // addition to get the next register, but for VFP registers, the
1053  // sort order is guaranteed because they're all of the form D<n>.
1054  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1055    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1056}
1057
1058