Thumb1InstrInfo.cpp revision 77521f5232e679aa3de10aaaed2464aa91d7ff55 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/ADT/SmallVector.h"
21#include "Thumb1InstrInfo.h"
22
23using namespace llvm;
24
25Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26  : ARMBaseInstrInfo(STI), RI(*this, STI) {
27}
28
29unsigned Thumb1InstrInfo::
30getUnindexedOpcode(unsigned Opc) const {
31  return 0;
32}
33
34unsigned Thumb1InstrInfo::
35getOpcode(ARMII::Op Op) const {
36  switch (Op) {
37  case ARMII::ADDri: return ARM::tADDi8;
38  case ARMII::ADDrs: return 0;
39  case ARMII::ADDrr: return ARM::tADDrr;
40  case ARMII::B: return ARM::tB;
41  case ARMII::Bcc: return ARM::tBcc;
42  case ARMII::BR_JTr: return ARM::tBR_JTr;
43  case ARMII::BR_JTm: return 0;
44  case ARMII::BR_JTadd: return 0;
45  case ARMII::BX_RET: return ARM::tBX_RET;
46  case ARMII::FCPYS: return 0;
47  case ARMII::FCPYD: return 0;
48  case ARMII::FLDD: return 0;
49  case ARMII::FLDS: return 0;
50  case ARMII::FSTD: return 0;
51  case ARMII::FSTS: return 0;
52  case ARMII::LDR: return ARM::tLDR;
53  case ARMII::MOVr: return ARM::tMOVr;
54  case ARMII::STR: return ARM::tSTR;
55  case ARMII::SUBri: return ARM::tSUBi8;
56  case ARMII::SUBrs: return 0;
57  case ARMII::SUBrr: return ARM::tSUBrr;
58  case ARMII::VMOVD: return 0;
59  case ARMII::VMOVQ: return 0;
60  default:
61    break;
62  }
63
64  return 0;
65}
66
67bool
68Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
69  if (MBB.empty()) return false;
70
71  switch (MBB.back().getOpcode()) {
72  case ARM::tBX_RET:
73  case ARM::tBX_RET_vararg:
74  case ARM::tPOP_RET:
75  case ARM::tB:
76  case ARM::tBR_JTr:
77    return true;
78  default:
79    break;
80  }
81
82  return false;
83}
84
85bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
86                                  unsigned &SrcReg, unsigned &DstReg,
87                                  unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
88  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
89
90  unsigned oc = MI.getOpcode();
91  switch (oc) {
92  default:
93    return false;
94  case ARM::tMOVr:
95  case ARM::tMOVhir2lor:
96  case ARM::tMOVlor2hir:
97  case ARM::tMOVhir2hir:
98    assert(MI.getDesc().getNumOperands() >= 2 &&
99           MI.getOperand(0).isReg() &&
100           MI.getOperand(1).isReg() &&
101           "Invalid Thumb MOV instruction");
102    SrcReg = MI.getOperand(1).getReg();
103    DstReg = MI.getOperand(0).getReg();
104    return true;
105  }
106}
107
108unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
109                                              int &FrameIndex) const {
110  switch (MI->getOpcode()) {
111  default: break;
112  case ARM::tRestore:
113    if (MI->getOperand(1).isFI() &&
114        MI->getOperand(2).isImm() &&
115        MI->getOperand(2).getImm() == 0) {
116      FrameIndex = MI->getOperand(1).getIndex();
117      return MI->getOperand(0).getReg();
118    }
119    break;
120  }
121  return 0;
122}
123
124unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
125                                             int &FrameIndex) const {
126  switch (MI->getOpcode()) {
127  default: break;
128  case ARM::tSpill:
129    if (MI->getOperand(1).isFI() &&
130        MI->getOperand(2).isImm() &&
131        MI->getOperand(2).getImm() == 0) {
132      FrameIndex = MI->getOperand(1).getIndex();
133      return MI->getOperand(0).getReg();
134    }
135    break;
136  }
137  return 0;
138}
139
140bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
141                                   MachineBasicBlock::iterator I,
142                                   unsigned DestReg, unsigned SrcReg,
143                                   const TargetRegisterClass *DestRC,
144                                   const TargetRegisterClass *SrcRC) const {
145  DebugLoc DL = DebugLoc::getUnknownLoc();
146  if (I != MBB.end()) DL = I->getDebugLoc();
147
148  if (DestRC == ARM::GPRRegisterClass) {
149    if (SrcRC == ARM::GPRRegisterClass) {
150      BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
151      return true;
152    } else if (SrcRC == ARM::tGPRRegisterClass) {
153      BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
154      return true;
155    }
156  } else if (DestRC == ARM::tGPRRegisterClass) {
157    if (SrcRC == ARM::GPRRegisterClass) {
158      BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
159      return true;
160    } else if (SrcRC == ARM::tGPRRegisterClass) {
161      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
162      return true;
163    }
164  }
165
166  return false;
167}
168
169bool Thumb1InstrInfo::
170canFoldMemoryOperand(const MachineInstr *MI,
171                     const SmallVectorImpl<unsigned> &Ops) const {
172  if (Ops.size() != 1) return false;
173
174  unsigned OpNum = Ops[0];
175  unsigned Opc = MI->getOpcode();
176  switch (Opc) {
177  default: break;
178  case ARM::tMOVr:
179  case ARM::tMOVlor2hir:
180  case ARM::tMOVhir2lor:
181  case ARM::tMOVhir2hir: {
182    if (OpNum == 0) { // move -> store
183      unsigned SrcReg = MI->getOperand(1).getReg();
184      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
185        // tSpill cannot take a high register operand.
186        return false;
187    } else {          // move -> load
188      unsigned DstReg = MI->getOperand(0).getReg();
189      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
190        // tRestore cannot target a high register operand.
191        return false;
192    }
193    return true;
194  }
195  }
196
197  return false;
198}
199
200void Thumb1InstrInfo::
201storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
202                    unsigned SrcReg, bool isKill, int FI,
203                    const TargetRegisterClass *RC) const {
204  DebugLoc DL = DebugLoc::getUnknownLoc();
205  if (I != MBB.end()) DL = I->getDebugLoc();
206
207  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
208
209  if (RC == ARM::tGPRRegisterClass) {
210    BuildMI(MBB, I, DL, get(ARM::tSpill))
211      .addReg(SrcReg, getKillRegState(isKill))
212      .addFrameIndex(FI).addImm(0);
213  }
214}
215
216void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
217                                     bool isKill,
218                                     SmallVectorImpl<MachineOperand> &Addr,
219                                     const TargetRegisterClass *RC,
220                                     SmallVectorImpl<MachineInstr*> &NewMIs) const{
221  DebugLoc DL = DebugLoc::getUnknownLoc();
222  unsigned Opc = 0;
223
224  assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
225  if (RC == ARM::GPRRegisterClass) {
226    Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
227  }
228
229  MachineInstrBuilder MIB =
230    BuildMI(MF, DL,  get(Opc)).addReg(SrcReg, getKillRegState(isKill));
231  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
232    MIB.addOperand(Addr[i]);
233  NewMIs.push_back(MIB);
234  return;
235}
236
237void Thumb1InstrInfo::
238loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
239                     unsigned DestReg, int FI,
240                     const TargetRegisterClass *RC) const {
241  DebugLoc DL = DebugLoc::getUnknownLoc();
242  if (I != MBB.end()) DL = I->getDebugLoc();
243
244  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
245
246  if (RC == ARM::tGPRRegisterClass) {
247    BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
248      .addFrameIndex(FI).addImm(0);
249  }
250}
251
252void Thumb1InstrInfo::
253loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
254                SmallVectorImpl<MachineOperand> &Addr,
255                const TargetRegisterClass *RC,
256                SmallVectorImpl<MachineInstr*> &NewMIs) const {
257  DebugLoc DL = DebugLoc::getUnknownLoc();
258  unsigned Opc = 0;
259
260  if (RC == ARM::GPRRegisterClass) {
261    Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
262  }
263
264  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
265  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
266    MIB.addOperand(Addr[i]);
267  NewMIs.push_back(MIB);
268  return;
269}
270
271bool Thumb1InstrInfo::
272spillCalleeSavedRegisters(MachineBasicBlock &MBB,
273                          MachineBasicBlock::iterator MI,
274                          const std::vector<CalleeSavedInfo> &CSI) const {
275  if (CSI.empty())
276    return false;
277
278  DebugLoc DL = DebugLoc::getUnknownLoc();
279  if (MI != MBB.end()) DL = MI->getDebugLoc();
280
281  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
282  for (unsigned i = CSI.size(); i != 0; --i) {
283    unsigned Reg = CSI[i-1].getReg();
284    // Add the callee-saved register as live-in. It's killed at the spill.
285    MBB.addLiveIn(Reg);
286    MIB.addReg(Reg, RegState::Kill);
287  }
288  return true;
289}
290
291bool Thumb1InstrInfo::
292restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
293                            MachineBasicBlock::iterator MI,
294                            const std::vector<CalleeSavedInfo> &CSI) const {
295  MachineFunction &MF = *MBB.getParent();
296  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
297  if (CSI.empty())
298    return false;
299
300  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
301  MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
302  for (unsigned i = CSI.size(); i != 0; --i) {
303    unsigned Reg = CSI[i-1].getReg();
304    if (Reg == ARM::LR) {
305      // Special epilogue for vararg functions. See emitEpilogue
306      if (isVarArg)
307        continue;
308      Reg = ARM::PC;
309      PopMI->setDesc(get(ARM::tPOP_RET));
310      MI = MBB.erase(MI);
311    }
312    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
313  }
314
315  // It's illegal to emit pop instruction without operands.
316  if (PopMI->getNumOperands() > 0)
317    MBB.insert(MI, PopMI);
318
319  return true;
320}
321
322MachineInstr *Thumb1InstrInfo::
323foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
324                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
325  if (Ops.size() != 1) return NULL;
326
327  unsigned OpNum = Ops[0];
328  unsigned Opc = MI->getOpcode();
329  MachineInstr *NewMI = NULL;
330  switch (Opc) {
331  default: break;
332  case ARM::tMOVr:
333  case ARM::tMOVlor2hir:
334  case ARM::tMOVhir2lor:
335  case ARM::tMOVhir2hir: {
336    if (OpNum == 0) { // move -> store
337      unsigned SrcReg = MI->getOperand(1).getReg();
338      bool isKill = MI->getOperand(1).isKill();
339      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
340        // tSpill cannot take a high register operand.
341        break;
342      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
343        .addReg(SrcReg, getKillRegState(isKill))
344        .addFrameIndex(FI).addImm(0);
345    } else {          // move -> load
346      unsigned DstReg = MI->getOperand(0).getReg();
347      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
348        // tRestore cannot target a high register operand.
349        break;
350      bool isDead = MI->getOperand(0).isDead();
351      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
352        .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
353        .addFrameIndex(FI).addImm(0);
354    }
355    break;
356  }
357  }
358
359  return NewMI;
360}
361