SPUSubtarget.cpp revision 59ee62d2418df8db499eca1ae17f5900dc2dcbba 
1//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CellSPU-specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SPUSubtarget.h"
15#include "SPU.h"
16#include "SPURegisterInfo.h"
17#include "llvm/Target/TargetRegistry.h"
18#include "llvm/ADT/SmallVector.h"
19
20#define GET_SUBTARGETINFO_ENUM
21#define GET_SUBTARGETINFO_MC_DESC
22#define GET_SUBTARGETINFO_TARGET_DESC
23#define GET_SUBTARGETINFO_CTOR
24#include "SPUGenSubtargetInfo.inc"
25
26using namespace llvm;
27
28SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
29                           const std::string &FS) :
30  SPUGenSubtargetInfo(TT, CPU, FS),
31  StackAlignment(16),
32  ProcDirective(SPU::DEFAULT_PROC),
33  UseLargeMem(false)
34{
35  // Should be the target SPU processor type. For now, since there's only
36  // one, simply default to the current "v0" default:
37  std::string default_cpu("v0");
38
39  // Parse features string.
40  ParseSubtargetFeatures(default_cpu, FS);
41
42  // Initialize scheduling itinerary for the specified CPU.
43  InstrItins = getInstrItineraryForCPU(default_cpu);
44}
45
46/// SetJITMode - This is called to inform the subtarget info that we are
47/// producing code for the JIT.
48void SPUSubtarget::SetJITMode() {
49}
50
51/// Enable PostRA scheduling for optimization levels -O2 and -O3.
52bool SPUSubtarget::enablePostRAScheduler(
53                       CodeGenOpt::Level OptLevel,
54                       TargetSubtargetInfo::AntiDepBreakMode& Mode,
55                       RegClassVector& CriticalPathRCs) const {
56  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
57  // CriticalPathsRCs seems to be the set of
58  // RegisterClasses that antidep breakings are performed for.
59  // Do it for all register classes
60  CriticalPathRCs.clear();
61  CriticalPathRCs.push_back(&SPU::R8CRegClass);
62  CriticalPathRCs.push_back(&SPU::R16CRegClass);
63  CriticalPathRCs.push_back(&SPU::R32CRegClass);
64  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
65  CriticalPathRCs.push_back(&SPU::R64CRegClass);
66  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
67  return OptLevel >= CodeGenOpt::Default;
68}
69
70MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
71                                          StringRef FS) {
72  MCSubtargetInfo *X = new MCSubtargetInfo();
73  InitSPUMCSubtargetInfo(X, TT, CPU, FS);
74  return X;
75}
76
77extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
78  TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
79                                          createSPUMCSubtargetInfo);
80}
81