HexagonInstrInfo.cpp revision 31d157ae1ac2cd9c787dc3c1d28e64c682803844 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonRegisterInfo.h"
15#include "HexagonInstrInfo.h"
16#include "HexagonSubtarget.h"
17#include "Hexagon.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#include "HexagonGenInstrInfo.inc"
29#include "HexagonGenDFAPacketizer.inc"
30
31using namespace llvm;
32
33///
34/// Constants for Hexagon instructions.
35///
36const int Hexagon_MEMW_OFFSET_MAX = 4095;
37const int Hexagon_MEMW_OFFSET_MIN = 4096;
38const int Hexagon_MEMD_OFFSET_MAX = 8191;
39const int Hexagon_MEMD_OFFSET_MIN = 8192;
40const int Hexagon_MEMH_OFFSET_MAX = 2047;
41const int Hexagon_MEMH_OFFSET_MIN = 2048;
42const int Hexagon_MEMB_OFFSET_MAX = 1023;
43const int Hexagon_MEMB_OFFSET_MIN = 1024;
44const int Hexagon_ADDI_OFFSET_MAX = 32767;
45const int Hexagon_ADDI_OFFSET_MIN = 32768;
46const int Hexagon_MEMD_AUTOINC_MAX = 56;
47const int Hexagon_MEMD_AUTOINC_MIN = 64;
48const int Hexagon_MEMW_AUTOINC_MAX = 28;
49const int Hexagon_MEMW_AUTOINC_MIN = 32;
50const int Hexagon_MEMH_AUTOINC_MAX = 14;
51const int Hexagon_MEMH_AUTOINC_MIN = 16;
52const int Hexagon_MEMB_AUTOINC_MAX = 7;
53const int Hexagon_MEMB_AUTOINC_MIN = 8;
54
55
56
57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59    RI(ST, *this), Subtarget(ST) {
60}
61
62
63/// isLoadFromStackSlot - If the specified machine instruction is a direct
64/// load from a stack slot, return the virtual or physical register number of
65/// the destination along with the FrameIndex of the loaded stack slot.  If
66/// not, return 0.  This predicate must return 0 if the instruction has
67/// any side effects other than loading from the stack slot.
68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69                                             int &FrameIndex) const {
70
71
72  switch (MI->getOpcode()) {
73  case Hexagon::LDriw:
74  case Hexagon::LDrid:
75  case Hexagon::LDrih:
76  case Hexagon::LDrib:
77  case Hexagon::LDriub:
78    if (MI->getOperand(2).isFI() &&
79        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80      FrameIndex = MI->getOperand(2).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83    break;
84
85  default:
86    break;
87  }
88
89  return 0;
90}
91
92
93/// isStoreToStackSlot - If the specified machine instruction is a direct
94/// store to a stack slot, return the virtual or physical register number of
95/// the source reg along with the FrameIndex of the loaded stack slot.  If
96/// not, return 0.  This predicate must return 0 if the instruction has
97/// any side effects other than storing to the stack slot.
98unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99                                            int &FrameIndex) const {
100  switch (MI->getOpcode()) {
101  case Hexagon::STriw:
102  case Hexagon::STrid:
103  case Hexagon::STrih:
104  case Hexagon::STrib:
105    if (MI->getOperand(2).isFI() &&
106        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107      FrameIndex = MI->getOperand(2).getIndex();
108      return MI->getOperand(0).getReg();
109    }
110    break;
111
112  default:
113    break;
114  }
115
116  return 0;
117}
118
119
120unsigned
121HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122                             MachineBasicBlock *FBB,
123                             const SmallVectorImpl<MachineOperand> &Cond,
124                             DebugLoc DL) const{
125
126    int BOpc   = Hexagon::JMP;
127    int BccOpc = Hexagon::JMP_c;
128
129    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
130
131    int regPos = 0;
132    // Check if ReverseBranchCondition has asked to reverse this branch
133    // If we want to reverse the branch an odd number of times, we want
134    // JMP_cNot.
135    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136      BccOpc = Hexagon::JMP_cNot;
137      regPos = 1;
138    }
139
140    if (FBB == 0) {
141      if (Cond.empty()) {
142        // Due to a bug in TailMerging/CFG Optimization, we need to add a
143        // special case handling of a predicated jump followed by an
144        // unconditional jump. If not, Tail Merging and CFG Optimization go
145        // into an infinite loop.
146        MachineBasicBlock *NewTBB, *NewFBB;
147        SmallVector<MachineOperand, 4> Cond;
148        MachineInstr *Term = MBB.getFirstTerminator();
149        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150                                                 false)) {
151          MachineBasicBlock *NextBB =
152            llvm::next(MachineFunction::iterator(&MBB));
153          if (NewTBB == NextBB) {
154            ReverseBranchCondition(Cond);
155            RemoveBranch(MBB);
156            return InsertBranch(MBB, TBB, 0, Cond, DL);
157          }
158        }
159        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160      } else {
161        BuildMI(&MBB, DL,
162                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163      }
164      return 1;
165    }
166
167    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
169
170    return 2;
171}
172
173
174bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175                                     MachineBasicBlock *&TBB,
176                                 MachineBasicBlock *&FBB,
177                                 SmallVectorImpl<MachineOperand> &Cond,
178                                 bool AllowModify) const {
179  FBB = NULL;
180
181  // If the block has no terminators, it just falls into the block after it.
182  MachineBasicBlock::iterator I = MBB.end();
183  if (I == MBB.begin())
184    return false;
185
186  // A basic block may looks like this:
187  //
188  //  [   insn
189  //     EH_LABEL
190  //      insn
191  //      insn
192  //      insn
193  //     EH_LABEL
194  //      insn     ]
195  //
196  // It has two succs but does not have a terminator
197  // Don't know how to handle it.
198  do {
199    --I;
200    if (I->isEHLabel())
201      return true;
202  } while (I != MBB.begin());
203
204  I = MBB.end();
205  --I;
206
207  while (I->isDebugValue()) {
208    if (I == MBB.begin())
209      return false;
210    --I;
211  }
212  if (!isUnpredicatedTerminator(I))
213    return false;
214
215  // Get the last instruction in the block.
216  MachineInstr *LastInst = I;
217
218  // If there is only one terminator instruction, process it.
219  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
220    if (LastInst->getOpcode() == Hexagon::JMP) {
221      TBB = LastInst->getOperand(0).getMBB();
222      return false;
223    }
224    if (LastInst->getOpcode() == Hexagon::JMP_c) {
225      // Block ends with fall-through true condbranch.
226      TBB = LastInst->getOperand(1).getMBB();
227      Cond.push_back(LastInst->getOperand(0));
228      return false;
229    }
230    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
231      // Block ends with fall-through false condbranch.
232      TBB = LastInst->getOperand(1).getMBB();
233      Cond.push_back(MachineOperand::CreateImm(0));
234      Cond.push_back(LastInst->getOperand(0));
235      return false;
236    }
237    // Otherwise, don't know what this is.
238    return true;
239  }
240
241  // Get the instruction before it if it's a terminator.
242  MachineInstr *SecondLastInst = I;
243
244  // If there are three terminators, we don't know what sort of block this is.
245  if (SecondLastInst && I != MBB.begin() &&
246      isUnpredicatedTerminator(--I))
247    return true;
248
249  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
250  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
251      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
252      LastInst->getOpcode() == Hexagon::JMP) {
253    TBB =  SecondLastInst->getOperand(1).getMBB();
254    Cond.push_back(SecondLastInst->getOperand(0));
255    FBB = LastInst->getOperand(0).getMBB();
256    return false;
257  }
258
259  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
260  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
261      LastInst->getOpcode() == Hexagon::JMP) {
262    TBB =  SecondLastInst->getOperand(1).getMBB();
263    Cond.push_back(MachineOperand::CreateImm(0));
264    Cond.push_back(SecondLastInst->getOperand(0));
265    FBB = LastInst->getOperand(0).getMBB();
266    return false;
267  }
268
269  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
270  // executed, so remove it.
271  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
272      LastInst->getOpcode() == Hexagon::JMP) {
273    TBB = SecondLastInst->getOperand(0).getMBB();
274    I = LastInst;
275    if (AllowModify)
276      I->eraseFromParent();
277    return false;
278  }
279
280  // Otherwise, can't handle this.
281  return true;
282}
283
284
285unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286  int BOpc   = Hexagon::JMP;
287  int BccOpc = Hexagon::JMP_c;
288  int BccOpcNot = Hexagon::JMP_cNot;
289
290  MachineBasicBlock::iterator I = MBB.end();
291  if (I == MBB.begin()) return 0;
292  --I;
293  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
294      I->getOpcode() != BccOpcNot)
295    return 0;
296
297  // Remove the branch.
298  I->eraseFromParent();
299
300  I = MBB.end();
301
302  if (I == MBB.begin()) return 1;
303  --I;
304  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
305    return 1;
306
307  // Remove the branch.
308  I->eraseFromParent();
309  return 2;
310}
311
312
313void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314                                 MachineBasicBlock::iterator I, DebugLoc DL,
315                                 unsigned DestReg, unsigned SrcReg,
316                                 bool KillSrc) const {
317  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
318    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
319    return;
320  }
321  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
322    BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
323    return;
324  }
325  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
326    // Map Pd = Ps to Pd = or(Ps, Ps).
327    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
328            DestReg).addReg(SrcReg).addReg(SrcReg);
329    return;
330  }
331  if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
332    // We can have an overlap between single and double reg: r1:0 = r0.
333    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
334        // r1:0 = r0
335        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336                Hexagon::subreg_hireg))).addImm(0);
337    } else {
338        // r1:0 = r1 or no overlap.
339        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
340                Hexagon::subreg_loreg))).addReg(SrcReg);
341        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
342                Hexagon::subreg_hireg))).addImm(0);
343    }
344    return;
345  }
346  if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
347    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
348    return;
349  }
350
351  llvm_unreachable("Unimplemented");
352}
353
354
355void HexagonInstrInfo::
356storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
357                    unsigned SrcReg, bool isKill, int FI,
358                    const TargetRegisterClass *RC,
359                    const TargetRegisterInfo *TRI) const {
360
361  DebugLoc DL = MBB.findDebugLoc(I);
362  MachineFunction &MF = *MBB.getParent();
363  MachineFrameInfo &MFI = *MF.getFrameInfo();
364  unsigned Align = MFI.getObjectAlignment(FI);
365
366  MachineMemOperand *MMO =
367      MF.getMachineMemOperand(
368                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
369                      MachineMemOperand::MOStore,
370                      MFI.getObjectSize(FI),
371                      Align);
372
373  if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
374    BuildMI(MBB, I, DL, get(Hexagon::STriw))
375          .addFrameIndex(FI).addImm(0)
376          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
377  } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
378    BuildMI(MBB, I, DL, get(Hexagon::STrid))
379          .addFrameIndex(FI).addImm(0)
380          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381  } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
382    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
383          .addFrameIndex(FI).addImm(0)
384          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
385  } else {
386    llvm_unreachable("Unimplemented");
387  }
388}
389
390
391void HexagonInstrInfo::storeRegToAddr(
392                                 MachineFunction &MF, unsigned SrcReg,
393                                 bool isKill,
394                                 SmallVectorImpl<MachineOperand> &Addr,
395                                 const TargetRegisterClass *RC,
396                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
397{
398  llvm_unreachable("Unimplemented");
399}
400
401
402void HexagonInstrInfo::
403loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
404                     unsigned DestReg, int FI,
405                     const TargetRegisterClass *RC,
406                     const TargetRegisterInfo *TRI) const {
407  DebugLoc DL = MBB.findDebugLoc(I);
408  MachineFunction &MF = *MBB.getParent();
409  MachineFrameInfo &MFI = *MF.getFrameInfo();
410  unsigned Align = MFI.getObjectAlignment(FI);
411
412  MachineMemOperand *MMO =
413      MF.getMachineMemOperand(
414                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
415                      MachineMemOperand::MOLoad,
416                      MFI.getObjectSize(FI),
417                      Align);
418
419  if (RC == Hexagon::IntRegsRegisterClass) {
420    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
421          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422  } else if (RC == Hexagon::DoubleRegsRegisterClass) {
423    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
424          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
425  } else if (RC == Hexagon::PredRegsRegisterClass) {
426    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
428  } else {
429    llvm_unreachable("Can't store this register to stack slot");
430  }
431}
432
433
434void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
435                                        SmallVectorImpl<MachineOperand> &Addr,
436                                        const TargetRegisterClass *RC,
437                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
438  llvm_unreachable("Unimplemented");
439}
440
441
442MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
443                                                    MachineInstr* MI,
444                                          const SmallVectorImpl<unsigned> &Ops,
445                                                    int FI) const {
446  // Hexagon_TODO: Implement.
447  return(0);
448}
449
450
451unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
452
453  MachineRegisterInfo &RegInfo = MF->getRegInfo();
454  const TargetRegisterClass *TRC;
455  if (VT == MVT::i1) {
456    TRC =  Hexagon::PredRegsRegisterClass;
457  } else if (VT == MVT::i32) {
458    TRC =  Hexagon::IntRegsRegisterClass;
459  } else if (VT == MVT::i64) {
460    TRC =  Hexagon::DoubleRegsRegisterClass;
461  } else {
462    llvm_unreachable("Cannot handle this register class");
463  }
464
465  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
466  return NewReg;
467}
468
469
470
471bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
472  bool isPred = MI->getDesc().isPredicable();
473
474  if (!isPred)
475    return false;
476
477  const int Opc = MI->getOpcode();
478
479  switch(Opc) {
480  case Hexagon::TFRI:
481    return isInt<12>(MI->getOperand(1).getImm());
482
483  case Hexagon::STrid:
484  case Hexagon::STrid_indexed:
485    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
486
487  case Hexagon::STriw:
488  case Hexagon::STriw_indexed:
489  case Hexagon::STriw_nv_V4:
490    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
491
492  case Hexagon::STrih:
493  case Hexagon::STrih_indexed:
494  case Hexagon::STrih_nv_V4:
495    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
496
497  case Hexagon::STrib:
498  case Hexagon::STrib_indexed:
499  case Hexagon::STrib_nv_V4:
500    return isUInt<6>(MI->getOperand(1).getImm());
501
502  case Hexagon::LDrid:
503  case Hexagon::LDrid_indexed:
504    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
505
506  case Hexagon::LDriw:
507  case Hexagon::LDriw_indexed:
508    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
509
510  case Hexagon::LDrih:
511  case Hexagon::LDriuh:
512  case Hexagon::LDrih_indexed:
513  case Hexagon::LDriuh_indexed:
514    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
515
516  case Hexagon::LDrib:
517  case Hexagon::LDriub:
518  case Hexagon::LDrib_indexed:
519  case Hexagon::LDriub_indexed:
520    return isUInt<6>(MI->getOperand(2).getImm());
521
522  case Hexagon::POST_LDrid:
523    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
524
525  case Hexagon::POST_LDriw:
526    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
527
528  case Hexagon::POST_LDrih:
529  case Hexagon::POST_LDriuh:
530    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
531
532  case Hexagon::POST_LDrib:
533  case Hexagon::POST_LDriub:
534    return isInt<4>(MI->getOperand(3).getImm());
535
536  case Hexagon::STrib_imm_V4:
537  case Hexagon::STrih_imm_V4:
538  case Hexagon::STriw_imm_V4:
539    return (isUInt<6>(MI->getOperand(1).getImm()) &&
540            isInt<6>(MI->getOperand(2).getImm()));
541
542  case Hexagon::ADD_ri:
543    return isInt<8>(MI->getOperand(2).getImm());
544
545  case Hexagon::ASLH:
546  case Hexagon::ASRH:
547  case Hexagon::SXTB:
548  case Hexagon::SXTH:
549  case Hexagon::ZXTB:
550  case Hexagon::ZXTH:
551    return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
552
553  case Hexagon::JMPR:
554    return false;
555  }
556
557  return true;
558}
559
560unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
561  switch(Opc) {
562    case Hexagon::TFR_cPt:
563      return Hexagon::TFR_cNotPt;
564    case Hexagon::TFR_cNotPt:
565      return Hexagon::TFR_cPt;
566
567    case Hexagon::TFRI_cPt:
568      return Hexagon::TFRI_cNotPt;
569    case Hexagon::TFRI_cNotPt:
570      return Hexagon::TFRI_cPt;
571
572    case Hexagon::JMP_c:
573      return Hexagon::JMP_cNot;
574    case Hexagon::JMP_cNot:
575      return Hexagon::JMP_c;
576
577    case Hexagon::ADD_ri_cPt:
578      return Hexagon::ADD_ri_cNotPt;
579    case Hexagon::ADD_ri_cNotPt:
580      return Hexagon::ADD_ri_cPt;
581
582    case Hexagon::ADD_rr_cPt:
583      return Hexagon::ADD_rr_cNotPt;
584    case Hexagon::ADD_rr_cNotPt:
585      return Hexagon::ADD_rr_cPt;
586
587    case Hexagon::XOR_rr_cPt:
588      return Hexagon::XOR_rr_cNotPt;
589    case Hexagon::XOR_rr_cNotPt:
590      return Hexagon::XOR_rr_cPt;
591
592    case Hexagon::AND_rr_cPt:
593      return Hexagon::AND_rr_cNotPt;
594    case Hexagon::AND_rr_cNotPt:
595      return Hexagon::AND_rr_cPt;
596
597    case Hexagon::OR_rr_cPt:
598      return Hexagon::OR_rr_cNotPt;
599    case Hexagon::OR_rr_cNotPt:
600      return Hexagon::OR_rr_cPt;
601
602    case Hexagon::SUB_rr_cPt:
603      return Hexagon::SUB_rr_cNotPt;
604    case Hexagon::SUB_rr_cNotPt:
605      return Hexagon::SUB_rr_cPt;
606
607    case Hexagon::COMBINE_rr_cPt:
608      return Hexagon::COMBINE_rr_cNotPt;
609    case Hexagon::COMBINE_rr_cNotPt:
610      return Hexagon::COMBINE_rr_cPt;
611
612    case Hexagon::ASLH_cPt_V4:
613      return Hexagon::ASLH_cNotPt_V4;
614    case Hexagon::ASLH_cNotPt_V4:
615      return Hexagon::ASLH_cPt_V4;
616
617    case Hexagon::ASRH_cPt_V4:
618      return Hexagon::ASRH_cNotPt_V4;
619    case Hexagon::ASRH_cNotPt_V4:
620      return Hexagon::ASRH_cPt_V4;
621
622    case Hexagon::SXTB_cPt_V4:
623      return Hexagon::SXTB_cNotPt_V4;
624    case Hexagon::SXTB_cNotPt_V4:
625      return Hexagon::SXTB_cPt_V4;
626
627    case Hexagon::SXTH_cPt_V4:
628      return Hexagon::SXTH_cNotPt_V4;
629    case Hexagon::SXTH_cNotPt_V4:
630      return Hexagon::SXTH_cPt_V4;
631
632    case Hexagon::ZXTB_cPt_V4:
633      return Hexagon::ZXTB_cNotPt_V4;
634    case Hexagon::ZXTB_cNotPt_V4:
635      return Hexagon::ZXTB_cPt_V4;
636
637    case Hexagon::ZXTH_cPt_V4:
638      return Hexagon::ZXTH_cNotPt_V4;
639    case Hexagon::ZXTH_cNotPt_V4:
640      return Hexagon::ZXTH_cPt_V4;
641
642
643    case Hexagon::JMPR_cPt:
644      return Hexagon::JMPR_cNotPt;
645    case Hexagon::JMPR_cNotPt:
646      return Hexagon::JMPR_cPt;
647
648  // V4 indexed+scaled load.
649    case Hexagon::LDrid_indexed_cPt_V4:
650      return Hexagon::LDrid_indexed_cNotPt_V4;
651    case Hexagon::LDrid_indexed_cNotPt_V4:
652      return Hexagon::LDrid_indexed_cPt_V4;
653
654    case Hexagon::LDrid_indexed_shl_cPt_V4:
655      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
656    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
657      return Hexagon::LDrid_indexed_shl_cPt_V4;
658
659    case Hexagon::LDrib_indexed_cPt_V4:
660      return Hexagon::LDrib_indexed_cNotPt_V4;
661    case Hexagon::LDrib_indexed_cNotPt_V4:
662      return Hexagon::LDrib_indexed_cPt_V4;
663
664    case Hexagon::LDriub_indexed_cPt_V4:
665      return Hexagon::LDriub_indexed_cNotPt_V4;
666    case Hexagon::LDriub_indexed_cNotPt_V4:
667      return Hexagon::LDriub_indexed_cPt_V4;
668
669    case Hexagon::LDrib_indexed_shl_cPt_V4:
670      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
671    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
672      return Hexagon::LDrib_indexed_shl_cPt_V4;
673
674    case Hexagon::LDriub_indexed_shl_cPt_V4:
675      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
676    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
677      return Hexagon::LDriub_indexed_shl_cPt_V4;
678
679    case Hexagon::LDrih_indexed_cPt_V4:
680      return Hexagon::LDrih_indexed_cNotPt_V4;
681    case Hexagon::LDrih_indexed_cNotPt_V4:
682      return Hexagon::LDrih_indexed_cPt_V4;
683
684    case Hexagon::LDriuh_indexed_cPt_V4:
685      return Hexagon::LDriuh_indexed_cNotPt_V4;
686    case Hexagon::LDriuh_indexed_cNotPt_V4:
687      return Hexagon::LDriuh_indexed_cPt_V4;
688
689    case Hexagon::LDrih_indexed_shl_cPt_V4:
690      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
691    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
692      return Hexagon::LDrih_indexed_shl_cPt_V4;
693
694    case Hexagon::LDriuh_indexed_shl_cPt_V4:
695      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
696    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
697      return Hexagon::LDriuh_indexed_shl_cPt_V4;
698
699    case Hexagon::LDriw_indexed_cPt_V4:
700      return Hexagon::LDriw_indexed_cNotPt_V4;
701    case Hexagon::LDriw_indexed_cNotPt_V4:
702      return Hexagon::LDriw_indexed_cPt_V4;
703
704    case Hexagon::LDriw_indexed_shl_cPt_V4:
705      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
706    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
707      return Hexagon::LDriw_indexed_shl_cPt_V4;
708
709    // Byte.
710    case Hexagon::POST_STbri_cPt:
711      return Hexagon::POST_STbri_cNotPt;
712    case Hexagon::POST_STbri_cNotPt:
713      return Hexagon::POST_STbri_cPt;
714
715    case Hexagon::STrib_cPt:
716      return Hexagon::STrib_cNotPt;
717    case Hexagon::STrib_cNotPt:
718      return Hexagon::STrib_cPt;
719
720    case Hexagon::STrib_indexed_cPt:
721      return Hexagon::STrib_indexed_cNotPt;
722    case Hexagon::STrib_indexed_cNotPt:
723      return Hexagon::STrib_indexed_cPt;
724
725    case Hexagon::STrib_imm_cPt_V4:
726      return Hexagon::STrib_imm_cNotPt_V4;
727    case Hexagon::STrib_imm_cNotPt_V4:
728      return Hexagon::STrib_imm_cPt_V4;
729
730    case Hexagon::STrib_indexed_shl_cPt_V4:
731      return Hexagon::STrib_indexed_shl_cNotPt_V4;
732    case Hexagon::STrib_indexed_shl_cNotPt_V4:
733      return Hexagon::STrib_indexed_shl_cPt_V4;
734
735  // Halfword.
736    case Hexagon::POST_SThri_cPt:
737      return Hexagon::POST_SThri_cNotPt;
738    case Hexagon::POST_SThri_cNotPt:
739      return Hexagon::POST_SThri_cPt;
740
741    case Hexagon::STrih_cPt:
742      return Hexagon::STrih_cNotPt;
743    case Hexagon::STrih_cNotPt:
744      return Hexagon::STrih_cPt;
745
746    case Hexagon::STrih_indexed_cPt:
747      return Hexagon::STrih_indexed_cNotPt;
748    case Hexagon::STrih_indexed_cNotPt:
749      return Hexagon::STrih_indexed_cPt;
750
751    case Hexagon::STrih_imm_cPt_V4:
752      return Hexagon::STrih_imm_cNotPt_V4;
753    case Hexagon::STrih_imm_cNotPt_V4:
754      return Hexagon::STrih_imm_cPt_V4;
755
756    case Hexagon::STrih_indexed_shl_cPt_V4:
757      return Hexagon::STrih_indexed_shl_cNotPt_V4;
758    case Hexagon::STrih_indexed_shl_cNotPt_V4:
759      return Hexagon::STrih_indexed_shl_cPt_V4;
760
761  // Word.
762    case Hexagon::POST_STwri_cPt:
763      return Hexagon::POST_STwri_cNotPt;
764    case Hexagon::POST_STwri_cNotPt:
765      return Hexagon::POST_STwri_cPt;
766
767    case Hexagon::STriw_cPt:
768      return Hexagon::STriw_cNotPt;
769    case Hexagon::STriw_cNotPt:
770      return Hexagon::STriw_cPt;
771
772    case Hexagon::STriw_indexed_cPt:
773      return Hexagon::STriw_indexed_cNotPt;
774    case Hexagon::STriw_indexed_cNotPt:
775      return Hexagon::STriw_indexed_cPt;
776
777    case Hexagon::STriw_indexed_shl_cPt_V4:
778      return Hexagon::STriw_indexed_shl_cNotPt_V4;
779    case Hexagon::STriw_indexed_shl_cNotPt_V4:
780      return Hexagon::STriw_indexed_shl_cPt_V4;
781
782    case Hexagon::STriw_imm_cPt_V4:
783      return Hexagon::STriw_imm_cNotPt_V4;
784    case Hexagon::STriw_imm_cNotPt_V4:
785      return Hexagon::STriw_imm_cPt_V4;
786
787  // Double word.
788    case Hexagon::POST_STdri_cPt:
789      return Hexagon::POST_STdri_cNotPt;
790    case Hexagon::POST_STdri_cNotPt:
791      return Hexagon::POST_STdri_cPt;
792
793    case Hexagon::STrid_cPt:
794      return Hexagon::STrid_cNotPt;
795    case Hexagon::STrid_cNotPt:
796      return Hexagon::STrid_cPt;
797
798    case Hexagon::STrid_indexed_cPt:
799      return Hexagon::STrid_indexed_cNotPt;
800    case Hexagon::STrid_indexed_cNotPt:
801      return Hexagon::STrid_indexed_cPt;
802
803    case Hexagon::STrid_indexed_shl_cPt_V4:
804      return Hexagon::STrid_indexed_shl_cNotPt_V4;
805    case Hexagon::STrid_indexed_shl_cNotPt_V4:
806      return Hexagon::STrid_indexed_shl_cPt_V4;
807
808  // Load.
809    case Hexagon::LDrid_cPt:
810      return Hexagon::LDrid_cNotPt;
811    case Hexagon::LDrid_cNotPt:
812      return Hexagon::LDrid_cPt;
813
814    case Hexagon::LDriw_cPt:
815      return Hexagon::LDriw_cNotPt;
816    case Hexagon::LDriw_cNotPt:
817      return Hexagon::LDriw_cPt;
818
819    case Hexagon::LDrih_cPt:
820      return Hexagon::LDrih_cNotPt;
821    case Hexagon::LDrih_cNotPt:
822      return Hexagon::LDrih_cPt;
823
824    case Hexagon::LDriuh_cPt:
825      return Hexagon::LDriuh_cNotPt;
826    case Hexagon::LDriuh_cNotPt:
827      return Hexagon::LDriuh_cPt;
828
829    case Hexagon::LDrib_cPt:
830      return Hexagon::LDrib_cNotPt;
831    case Hexagon::LDrib_cNotPt:
832      return Hexagon::LDrib_cPt;
833
834    case Hexagon::LDriub_cPt:
835      return Hexagon::LDriub_cNotPt;
836    case Hexagon::LDriub_cNotPt:
837      return Hexagon::LDriub_cPt;
838
839 // Load Indexed.
840    case Hexagon::LDrid_indexed_cPt:
841      return Hexagon::LDrid_indexed_cNotPt;
842    case Hexagon::LDrid_indexed_cNotPt:
843      return Hexagon::LDrid_indexed_cPt;
844
845    case Hexagon::LDriw_indexed_cPt:
846      return Hexagon::LDriw_indexed_cNotPt;
847    case Hexagon::LDriw_indexed_cNotPt:
848      return Hexagon::LDriw_indexed_cPt;
849
850    case Hexagon::LDrih_indexed_cPt:
851      return Hexagon::LDrih_indexed_cNotPt;
852    case Hexagon::LDrih_indexed_cNotPt:
853      return Hexagon::LDrih_indexed_cPt;
854
855    case Hexagon::LDriuh_indexed_cPt:
856      return Hexagon::LDriuh_indexed_cNotPt;
857    case Hexagon::LDriuh_indexed_cNotPt:
858      return Hexagon::LDriuh_indexed_cPt;
859
860    case Hexagon::LDrib_indexed_cPt:
861      return Hexagon::LDrib_indexed_cNotPt;
862    case Hexagon::LDrib_indexed_cNotPt:
863      return Hexagon::LDrib_indexed_cPt;
864
865    case Hexagon::LDriub_indexed_cPt:
866      return Hexagon::LDriub_indexed_cNotPt;
867    case Hexagon::LDriub_indexed_cNotPt:
868      return Hexagon::LDriub_indexed_cPt;
869
870  // Post Inc Load.
871    case Hexagon::POST_LDrid_cPt:
872      return Hexagon::POST_LDrid_cNotPt;
873    case Hexagon::POST_LDriw_cNotPt:
874      return Hexagon::POST_LDriw_cPt;
875
876    case Hexagon::POST_LDrih_cPt:
877      return Hexagon::POST_LDrih_cNotPt;
878    case Hexagon::POST_LDrih_cNotPt:
879      return Hexagon::POST_LDrih_cPt;
880
881    case Hexagon::POST_LDriuh_cPt:
882      return Hexagon::POST_LDriuh_cNotPt;
883    case Hexagon::POST_LDriuh_cNotPt:
884      return Hexagon::POST_LDriuh_cPt;
885
886    case Hexagon::POST_LDrib_cPt:
887      return Hexagon::POST_LDrib_cNotPt;
888    case Hexagon::POST_LDrib_cNotPt:
889      return Hexagon::POST_LDrib_cPt;
890
891    case Hexagon::POST_LDriub_cPt:
892      return Hexagon::POST_LDriub_cNotPt;
893    case Hexagon::POST_LDriub_cNotPt:
894      return Hexagon::POST_LDriub_cPt;
895
896  // Dealloc_return.
897    case Hexagon::DEALLOC_RET_cPt_V4:
898      return Hexagon::DEALLOC_RET_cNotPt_V4;
899    case Hexagon::DEALLOC_RET_cNotPt_V4:
900      return Hexagon::DEALLOC_RET_cPt_V4;
901
902   // New Value Jump.
903   // JMPEQ_ri - with -1.
904    case Hexagon::JMP_EQriPtneg_nv_V4:
905      return Hexagon::JMP_EQriNotPtneg_nv_V4;
906    case Hexagon::JMP_EQriNotPtneg_nv_V4:
907      return Hexagon::JMP_EQriPtneg_nv_V4;
908
909    case Hexagon::JMP_EQriPntneg_nv_V4:
910      return Hexagon::JMP_EQriNotPntneg_nv_V4;
911    case Hexagon::JMP_EQriNotPntneg_nv_V4:
912      return Hexagon::JMP_EQriPntneg_nv_V4;
913
914   // JMPEQ_ri.
915     case Hexagon::JMP_EQriPt_nv_V4:
916      return Hexagon::JMP_EQriNotPt_nv_V4;
917    case Hexagon::JMP_EQriNotPt_nv_V4:
918      return Hexagon::JMP_EQriPt_nv_V4;
919
920     case Hexagon::JMP_EQriPnt_nv_V4:
921      return Hexagon::JMP_EQriNotPnt_nv_V4;
922    case Hexagon::JMP_EQriNotPnt_nv_V4:
923      return Hexagon::JMP_EQriPnt_nv_V4;
924
925   // JMPEQ_rr.
926     case Hexagon::JMP_EQrrPt_nv_V4:
927      return Hexagon::JMP_EQrrNotPt_nv_V4;
928    case Hexagon::JMP_EQrrNotPt_nv_V4:
929      return Hexagon::JMP_EQrrPt_nv_V4;
930
931     case Hexagon::JMP_EQrrPnt_nv_V4:
932      return Hexagon::JMP_EQrrNotPnt_nv_V4;
933    case Hexagon::JMP_EQrrNotPnt_nv_V4:
934      return Hexagon::JMP_EQrrPnt_nv_V4;
935
936   // JMPGT_ri - with -1.
937    case Hexagon::JMP_GTriPtneg_nv_V4:
938      return Hexagon::JMP_GTriNotPtneg_nv_V4;
939    case Hexagon::JMP_GTriNotPtneg_nv_V4:
940      return Hexagon::JMP_GTriPtneg_nv_V4;
941
942    case Hexagon::JMP_GTriPntneg_nv_V4:
943      return Hexagon::JMP_GTriNotPntneg_nv_V4;
944    case Hexagon::JMP_GTriNotPntneg_nv_V4:
945      return Hexagon::JMP_GTriPntneg_nv_V4;
946
947   // JMPGT_ri.
948     case Hexagon::JMP_GTriPt_nv_V4:
949      return Hexagon::JMP_GTriNotPt_nv_V4;
950    case Hexagon::JMP_GTriNotPt_nv_V4:
951      return Hexagon::JMP_GTriPt_nv_V4;
952
953     case Hexagon::JMP_GTriPnt_nv_V4:
954      return Hexagon::JMP_GTriNotPnt_nv_V4;
955    case Hexagon::JMP_GTriNotPnt_nv_V4:
956      return Hexagon::JMP_GTriPnt_nv_V4;
957
958   // JMPGT_rr.
959     case Hexagon::JMP_GTrrPt_nv_V4:
960      return Hexagon::JMP_GTrrNotPt_nv_V4;
961    case Hexagon::JMP_GTrrNotPt_nv_V4:
962      return Hexagon::JMP_GTrrPt_nv_V4;
963
964     case Hexagon::JMP_GTrrPnt_nv_V4:
965      return Hexagon::JMP_GTrrNotPnt_nv_V4;
966    case Hexagon::JMP_GTrrNotPnt_nv_V4:
967      return Hexagon::JMP_GTrrPnt_nv_V4;
968
969   // JMPGT_rrdn.
970     case Hexagon::JMP_GTrrdnPt_nv_V4:
971      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
972    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
973      return Hexagon::JMP_GTrrdnPt_nv_V4;
974
975     case Hexagon::JMP_GTrrdnPnt_nv_V4:
976      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
977    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
978      return Hexagon::JMP_GTrrdnPnt_nv_V4;
979
980   // JMPGTU_ri.
981     case Hexagon::JMP_GTUriPt_nv_V4:
982      return Hexagon::JMP_GTUriNotPt_nv_V4;
983    case Hexagon::JMP_GTUriNotPt_nv_V4:
984      return Hexagon::JMP_GTUriPt_nv_V4;
985
986     case Hexagon::JMP_GTUriPnt_nv_V4:
987      return Hexagon::JMP_GTUriNotPnt_nv_V4;
988    case Hexagon::JMP_GTUriNotPnt_nv_V4:
989      return Hexagon::JMP_GTUriPnt_nv_V4;
990
991   // JMPGTU_rr.
992     case Hexagon::JMP_GTUrrPt_nv_V4:
993      return Hexagon::JMP_GTUrrNotPt_nv_V4;
994    case Hexagon::JMP_GTUrrNotPt_nv_V4:
995      return Hexagon::JMP_GTUrrPt_nv_V4;
996
997     case Hexagon::JMP_GTUrrPnt_nv_V4:
998      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
999    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1000      return Hexagon::JMP_GTUrrPnt_nv_V4;
1001
1002   // JMPGTU_rrdn.
1003     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1004      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1005    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1006      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1007
1008     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1009      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1010    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1011      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1012
1013  default:
1014    llvm_unreachable("Unexpected predicated instruction");
1015  }
1016}
1017
1018
1019int HexagonInstrInfo::
1020getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1021  switch(Opc) {
1022  case Hexagon::TFR:
1023    return !invertPredicate ? Hexagon::TFR_cPt :
1024                              Hexagon::TFR_cNotPt;
1025  case Hexagon::TFRI:
1026    return !invertPredicate ? Hexagon::TFRI_cPt :
1027                              Hexagon::TFRI_cNotPt;
1028  case Hexagon::JMP:
1029    return !invertPredicate ? Hexagon::JMP_c :
1030                              Hexagon::JMP_cNot;
1031  case Hexagon::ADD_ri:
1032    return !invertPredicate ? Hexagon::ADD_ri_cPt :
1033                              Hexagon::ADD_ri_cNotPt;
1034  case Hexagon::ADD_rr:
1035    return !invertPredicate ? Hexagon::ADD_rr_cPt :
1036                              Hexagon::ADD_rr_cNotPt;
1037  case Hexagon::XOR_rr:
1038    return !invertPredicate ? Hexagon::XOR_rr_cPt :
1039                              Hexagon::XOR_rr_cNotPt;
1040  case Hexagon::AND_rr:
1041    return !invertPredicate ? Hexagon::AND_rr_cPt :
1042                              Hexagon::AND_rr_cNotPt;
1043  case Hexagon::OR_rr:
1044    return !invertPredicate ? Hexagon::OR_rr_cPt :
1045                              Hexagon::OR_rr_cNotPt;
1046  case Hexagon::SUB_rr:
1047    return !invertPredicate ? Hexagon::SUB_rr_cPt :
1048                              Hexagon::SUB_rr_cNotPt;
1049  case Hexagon::COMBINE_rr:
1050    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1051                              Hexagon::COMBINE_rr_cNotPt;
1052  case Hexagon::ASLH:
1053    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1054                              Hexagon::ASLH_cNotPt_V4;
1055  case Hexagon::ASRH:
1056    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1057                              Hexagon::ASRH_cNotPt_V4;
1058  case Hexagon::SXTB:
1059    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1060                              Hexagon::SXTB_cNotPt_V4;
1061  case Hexagon::SXTH:
1062    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1063                              Hexagon::SXTH_cNotPt_V4;
1064  case Hexagon::ZXTB:
1065    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1066                              Hexagon::ZXTB_cNotPt_V4;
1067  case Hexagon::ZXTH:
1068    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1069                              Hexagon::ZXTH_cNotPt_V4;
1070
1071  case Hexagon::JMPR:
1072    return !invertPredicate ? Hexagon::JMPR_cPt :
1073                              Hexagon::JMPR_cNotPt;
1074
1075  // V4 indexed+scaled load.
1076  case Hexagon::LDrid_indexed_V4:
1077    return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1078                              Hexagon::LDrid_indexed_cNotPt_V4;
1079  case Hexagon::LDrid_indexed_shl_V4:
1080    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1081                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1082  case Hexagon::LDrib_indexed_V4:
1083    return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1084                              Hexagon::LDrib_indexed_cNotPt_V4;
1085  case Hexagon::LDriub_indexed_V4:
1086    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1087                              Hexagon::LDriub_indexed_cNotPt_V4;
1088  case Hexagon::LDriub_ae_indexed_V4:
1089    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1090                              Hexagon::LDriub_indexed_cNotPt_V4;
1091  case Hexagon::LDrib_indexed_shl_V4:
1092    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1093                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1094  case Hexagon::LDriub_indexed_shl_V4:
1095    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1096                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1097  case Hexagon::LDriub_ae_indexed_shl_V4:
1098    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1099                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1100  case Hexagon::LDrih_indexed_V4:
1101    return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1102                              Hexagon::LDrih_indexed_cNotPt_V4;
1103  case Hexagon::LDriuh_indexed_V4:
1104    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1105                              Hexagon::LDriuh_indexed_cNotPt_V4;
1106  case Hexagon::LDriuh_ae_indexed_V4:
1107    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1108                              Hexagon::LDriuh_indexed_cNotPt_V4;
1109  case Hexagon::LDrih_indexed_shl_V4:
1110    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1111                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1112  case Hexagon::LDriuh_indexed_shl_V4:
1113    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1114                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1115  case Hexagon::LDriuh_ae_indexed_shl_V4:
1116    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1117                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1118  case Hexagon::LDriw_indexed_V4:
1119    return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1120                              Hexagon::LDriw_indexed_cNotPt_V4;
1121  case Hexagon::LDriw_indexed_shl_V4:
1122    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1123                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1124    // Byte.
1125  case Hexagon::POST_STbri:
1126    return !invertPredicate ? Hexagon::POST_STbri_cPt :
1127                              Hexagon::POST_STbri_cNotPt;
1128  case Hexagon::STrib:
1129    return !invertPredicate ? Hexagon::STrib_cPt :
1130                              Hexagon::STrib_cNotPt;
1131  case Hexagon::STrib_indexed:
1132    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1133                              Hexagon::STrib_indexed_cNotPt;
1134  case Hexagon::STrib_imm_V4:
1135    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1136                              Hexagon::STrib_imm_cNotPt_V4;
1137  case Hexagon::STrib_indexed_shl_V4:
1138    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1139                              Hexagon::STrib_indexed_shl_cNotPt_V4;
1140  // Halfword.
1141  case Hexagon::POST_SThri:
1142    return !invertPredicate ? Hexagon::POST_SThri_cPt :
1143                              Hexagon::POST_SThri_cNotPt;
1144  case Hexagon::STrih:
1145    return !invertPredicate ? Hexagon::STrih_cPt :
1146                              Hexagon::STrih_cNotPt;
1147  case Hexagon::STrih_indexed:
1148    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1149                              Hexagon::STrih_indexed_cNotPt;
1150  case Hexagon::STrih_imm_V4:
1151    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1152                              Hexagon::STrih_imm_cNotPt_V4;
1153  case Hexagon::STrih_indexed_shl_V4:
1154    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1155                              Hexagon::STrih_indexed_shl_cNotPt_V4;
1156  // Word.
1157  case Hexagon::POST_STwri:
1158    return !invertPredicate ? Hexagon::POST_STwri_cPt :
1159                              Hexagon::POST_STwri_cNotPt;
1160  case Hexagon::STriw:
1161    return !invertPredicate ? Hexagon::STriw_cPt :
1162                              Hexagon::STriw_cNotPt;
1163  case Hexagon::STriw_indexed:
1164    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1165                              Hexagon::STriw_indexed_cNotPt;
1166  case Hexagon::STriw_indexed_shl_V4:
1167    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1168                              Hexagon::STriw_indexed_shl_cNotPt_V4;
1169  case Hexagon::STriw_imm_V4:
1170    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1171                              Hexagon::STriw_imm_cNotPt_V4;
1172  // Double word.
1173  case Hexagon::POST_STdri:
1174    return !invertPredicate ? Hexagon::POST_STdri_cPt :
1175                              Hexagon::POST_STdri_cNotPt;
1176  case Hexagon::STrid:
1177    return !invertPredicate ? Hexagon::STrid_cPt :
1178                              Hexagon::STrid_cNotPt;
1179  case Hexagon::STrid_indexed:
1180    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1181                              Hexagon::STrid_indexed_cNotPt;
1182  case Hexagon::STrid_indexed_shl_V4:
1183    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1184                              Hexagon::STrid_indexed_shl_cNotPt_V4;
1185  // Load.
1186  case Hexagon::LDrid:
1187    return !invertPredicate ? Hexagon::LDrid_cPt :
1188                              Hexagon::LDrid_cNotPt;
1189  case Hexagon::LDriw:
1190    return !invertPredicate ? Hexagon::LDriw_cPt :
1191                              Hexagon::LDriw_cNotPt;
1192  case Hexagon::LDrih:
1193    return !invertPredicate ? Hexagon::LDrih_cPt :
1194                              Hexagon::LDrih_cNotPt;
1195  case Hexagon::LDriuh:
1196    return !invertPredicate ? Hexagon::LDriuh_cPt :
1197                              Hexagon::LDriuh_cNotPt;
1198  case Hexagon::LDrib:
1199    return !invertPredicate ? Hexagon::LDrib_cPt :
1200                              Hexagon::LDrib_cNotPt;
1201  case Hexagon::LDriub:
1202    return !invertPredicate ? Hexagon::LDriub_cPt :
1203                              Hexagon::LDriub_cNotPt;
1204  case Hexagon::LDriubit:
1205    return !invertPredicate ? Hexagon::LDriub_cPt :
1206                              Hexagon::LDriub_cNotPt;
1207 // Load Indexed.
1208  case Hexagon::LDrid_indexed:
1209    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1210                              Hexagon::LDrid_indexed_cNotPt;
1211  case Hexagon::LDriw_indexed:
1212    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1213                              Hexagon::LDriw_indexed_cNotPt;
1214  case Hexagon::LDrih_indexed:
1215    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1216                              Hexagon::LDrih_indexed_cNotPt;
1217  case Hexagon::LDriuh_indexed:
1218    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1219                              Hexagon::LDriuh_indexed_cNotPt;
1220  case Hexagon::LDrib_indexed:
1221    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1222                              Hexagon::LDrib_indexed_cNotPt;
1223  case Hexagon::LDriub_indexed:
1224    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1225                              Hexagon::LDriub_indexed_cNotPt;
1226  // Post Increment Load.
1227  case Hexagon::POST_LDrid:
1228    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1229                              Hexagon::POST_LDrid_cNotPt;
1230  case Hexagon::POST_LDriw:
1231    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1232                              Hexagon::POST_LDriw_cNotPt;
1233  case Hexagon::POST_LDrih:
1234    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1235                              Hexagon::POST_LDrih_cNotPt;
1236  case Hexagon::POST_LDriuh:
1237    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1238                              Hexagon::POST_LDriuh_cNotPt;
1239  case Hexagon::POST_LDrib:
1240    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1241                              Hexagon::POST_LDrib_cNotPt;
1242  case Hexagon::POST_LDriub:
1243    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1244                              Hexagon::POST_LDriub_cNotPt;
1245  // DEALLOC_RETURN.
1246  case Hexagon::DEALLOC_RET_V4:
1247    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1248                              Hexagon::DEALLOC_RET_cNotPt_V4;
1249  }
1250  llvm_unreachable("Unexpected predicable instruction");
1251}
1252
1253
1254bool HexagonInstrInfo::
1255PredicateInstruction(MachineInstr *MI,
1256                     const SmallVectorImpl<MachineOperand> &Cond) const {
1257  int Opc = MI->getOpcode();
1258  assert (isPredicable(MI) && "Expected predicable instruction");
1259  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1260                     (Cond[0].getImm() == 0));
1261  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1262  //
1263  // This assumes that the predicate is always the first operand
1264  // in the set of inputs.
1265  //
1266  MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1267  int oper;
1268  for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
1269    MachineOperand MO = MI->getOperand(oper);
1270    if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
1271      break;
1272    }
1273
1274    if (MO.isReg()) {
1275      MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1276                                              MO.isImplicit(), MO.isKill(),
1277                                              MO.isDead(), MO.isUndef(),
1278                                              MO.isDebug());
1279    } else if (MO.isImm()) {
1280      MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1281    } else {
1282      llvm_unreachable("Unexpected operand type");
1283    }
1284  }
1285
1286  int regPos = invertJump ? 1 : 0;
1287  MachineOperand PredMO = Cond[regPos];
1288  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1289                                          PredMO.isImplicit(), PredMO.isKill(),
1290                                          PredMO.isDead(), PredMO.isUndef(),
1291                                          PredMO.isDebug());
1292
1293  return true;
1294}
1295
1296
1297bool
1298HexagonInstrInfo::
1299isProfitableToIfCvt(MachineBasicBlock &MBB,
1300                    unsigned NumCyles,
1301                    unsigned ExtraPredCycles,
1302                    const BranchProbability &Probability) const {
1303  return true;
1304}
1305
1306
1307bool
1308HexagonInstrInfo::
1309isProfitableToIfCvt(MachineBasicBlock &TMBB,
1310                    unsigned NumTCycles,
1311                    unsigned ExtraTCycles,
1312                    MachineBasicBlock &FMBB,
1313                    unsigned NumFCycles,
1314                    unsigned ExtraFCycles,
1315                    const BranchProbability &Probability) const {
1316  return true;
1317}
1318
1319
1320bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1321  const uint64_t F = MI->getDesc().TSFlags;
1322
1323  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1324}
1325
1326
1327bool
1328HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1329                                   std::vector<MachineOperand> &Pred) const {
1330  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1331    MachineOperand MO = MI->getOperand(oper);
1332    if (MO.isReg() && MO.isDef()) {
1333      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1334      if (RC == Hexagon::PredRegsRegisterClass) {
1335        Pred.push_back(MO);
1336        return true;
1337      }
1338    }
1339  }
1340  return false;
1341}
1342
1343
1344bool
1345HexagonInstrInfo::
1346SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1347                  const SmallVectorImpl<MachineOperand> &Pred2) const {
1348  // TODO: Fix this
1349  return false;
1350}
1351
1352
1353//
1354// We indicate that we want to reverse the branch by
1355// inserting a 0 at the beginning of the Cond vector.
1356//
1357bool HexagonInstrInfo::
1358ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1359  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1360    Cond.erase(Cond.begin());
1361  } else {
1362    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1363  }
1364  return false;
1365}
1366
1367
1368bool HexagonInstrInfo::
1369isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1370                          const BranchProbability &Probability) const {
1371  return (NumInstrs <= 4);
1372}
1373
1374bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1375  switch (MI->getOpcode()) {
1376  case Hexagon::DEALLOC_RET_V4 :
1377  case Hexagon::DEALLOC_RET_cPt_V4 :
1378  case Hexagon::DEALLOC_RET_cNotPt_V4 :
1379  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1380  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1381  case Hexagon::DEALLOC_RET_cdnPt_V4 :
1382  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1383   return true;
1384  }
1385  return false;
1386}
1387
1388
1389bool HexagonInstrInfo::
1390isValidOffset(const int Opcode, const int Offset) const {
1391  // This function is to check whether the "Offset" is in the correct range of
1392  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1393  // inserted to calculate the final address. Due to this reason, the function
1394  // assumes that the "Offset" has correct alignment.
1395
1396  switch(Opcode) {
1397
1398  case Hexagon::LDriw:
1399  case Hexagon::STriw:
1400  case Hexagon::STriwt:
1401    assert((Offset % 4 == 0) && "Offset has incorrect alignment");
1402    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1403      (Offset <= Hexagon_MEMW_OFFSET_MAX);
1404
1405  case Hexagon::LDrid:
1406  case Hexagon::STrid:
1407    assert((Offset % 8 == 0) && "Offset has incorrect alignment");
1408    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1409      (Offset <= Hexagon_MEMD_OFFSET_MAX);
1410
1411  case Hexagon::LDrih:
1412  case Hexagon::LDriuh:
1413  case Hexagon::STrih:
1414  case Hexagon::LDrih_ae:
1415    assert((Offset % 2 == 0) && "Offset has incorrect alignment");
1416    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1417      (Offset <= Hexagon_MEMH_OFFSET_MAX);
1418
1419  case Hexagon::LDrib:
1420  case Hexagon::STrib:
1421  case Hexagon::LDriub:
1422  case Hexagon::LDriubit:
1423  case Hexagon::LDrib_ae:
1424  case Hexagon::LDriub_ae:
1425    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1426      (Offset <= Hexagon_MEMB_OFFSET_MAX);
1427
1428  case Hexagon::ADD_ri:
1429  case Hexagon::TFR_FI:
1430    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1431      (Offset <= Hexagon_ADDI_OFFSET_MAX);
1432
1433  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
1434  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1435  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1436  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1437  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1438  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1439  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1440  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
1441  case Hexagon::MEMw_ADDi_MEM_V4 :
1442  case Hexagon::MEMw_SUBi_MEM_V4 :
1443  case Hexagon::MEMw_ADDr_MEM_V4 :
1444  case Hexagon::MEMw_SUBr_MEM_V4 :
1445  case Hexagon::MEMw_ANDr_MEM_V4 :
1446  case Hexagon::MEMw_ORr_MEM_V4 :
1447    assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
1448    return (0 <= Offset && Offset <= 255);
1449
1450  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
1451  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1452  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1453  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1454  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1455  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1456  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1457  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1458  case Hexagon::MEMh_ADDi_MEM_V4 :
1459  case Hexagon::MEMh_SUBi_MEM_V4 :
1460  case Hexagon::MEMh_ADDr_MEM_V4 :
1461  case Hexagon::MEMh_SUBr_MEM_V4 :
1462  case Hexagon::MEMh_ANDr_MEM_V4 :
1463  case Hexagon::MEMh_ORr_MEM_V4 :
1464    assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
1465    return (0 <= Offset && Offset <= 127);
1466
1467  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1468  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1469  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1470  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1471  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1472  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1473  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1474  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1475  case Hexagon::MEMb_ADDi_MEM_V4 :
1476  case Hexagon::MEMb_SUBi_MEM_V4 :
1477  case Hexagon::MEMb_ADDr_MEM_V4 :
1478  case Hexagon::MEMb_SUBr_MEM_V4 :
1479  case Hexagon::MEMb_ANDr_MEM_V4 :
1480  case Hexagon::MEMb_ORr_MEM_V4 :
1481    return (0 <= Offset && Offset <= 63);
1482
1483  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1484  // any size. Later pass knows how to handle it.
1485  case Hexagon::STriw_pred:
1486  case Hexagon::LDriw_pred:
1487    return true;
1488
1489  // INLINEASM is very special.
1490  case Hexagon::INLINEASM:
1491    return true;
1492  }
1493
1494  llvm_unreachable("No offset range is defined for this opcode. "
1495                   "Please define it in the above switch statement!");
1496}
1497
1498
1499//
1500// Check if the Offset is a valid auto-inc imm by Load/Store Type.
1501//
1502bool HexagonInstrInfo::
1503isValidAutoIncImm(const EVT VT, const int Offset) const {
1504
1505  if (VT == MVT::i64) {
1506      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1507              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1508              (Offset & 0x7) == 0);
1509  }
1510  if (VT == MVT::i32) {
1511      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1512              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1513              (Offset & 0x3) == 0);
1514  }
1515  if (VT == MVT::i16) {
1516      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1517              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1518              (Offset & 0x1) == 0);
1519  }
1520  if (VT == MVT::i8) {
1521      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1522              Offset <= Hexagon_MEMB_AUTOINC_MAX);
1523  }
1524  llvm_unreachable("Not an auto-inc opc!");
1525}
1526
1527
1528bool HexagonInstrInfo::
1529isMemOp(const MachineInstr *MI) const {
1530  switch (MI->getOpcode())
1531  {
1532    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
1533    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1534    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1535    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1536    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1537    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1538    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1539    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
1540    case Hexagon::MEMw_ADDi_MEM_V4 :
1541    case Hexagon::MEMw_SUBi_MEM_V4 :
1542    case Hexagon::MEMw_ADDr_MEM_V4 :
1543    case Hexagon::MEMw_SUBr_MEM_V4 :
1544    case Hexagon::MEMw_ANDr_MEM_V4 :
1545    case Hexagon::MEMw_ORr_MEM_V4 :
1546    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
1547    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1548    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1549    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1550    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1551    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1552    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1553    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1554    case Hexagon::MEMh_ADDi_MEM_V4 :
1555    case Hexagon::MEMh_SUBi_MEM_V4 :
1556    case Hexagon::MEMh_ADDr_MEM_V4 :
1557    case Hexagon::MEMh_SUBr_MEM_V4 :
1558    case Hexagon::MEMh_ANDr_MEM_V4 :
1559    case Hexagon::MEMh_ORr_MEM_V4 :
1560    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1561    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1562    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1563    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1564    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1565    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1566    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1567    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1568    case Hexagon::MEMb_ADDi_MEM_V4 :
1569    case Hexagon::MEMb_SUBi_MEM_V4 :
1570    case Hexagon::MEMb_ADDr_MEM_V4 :
1571    case Hexagon::MEMb_SUBr_MEM_V4 :
1572    case Hexagon::MEMb_ANDr_MEM_V4 :
1573    case Hexagon::MEMb_ORr_MEM_V4 :
1574    return true;
1575  }
1576  return false;
1577}
1578
1579
1580bool HexagonInstrInfo::
1581isSpillPredRegOp(const MachineInstr *MI) const {
1582  switch (MI->getOpcode())
1583  {
1584    case Hexagon::STriw_pred :
1585    case Hexagon::LDriw_pred :
1586    return true;
1587  }
1588  return false;
1589}
1590
1591
1592bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1593  const HexagonRegisterInfo& QRI = getRegisterInfo();
1594  switch (MI->getOpcode())
1595  {
1596    case Hexagon::ADD_ri_cPt:
1597    case Hexagon::ADD_ri_cNotPt:
1598    case Hexagon::ADD_rr_cPt:
1599    case Hexagon::ADD_rr_cNotPt:
1600    case Hexagon::XOR_rr_cPt:
1601    case Hexagon::XOR_rr_cNotPt:
1602    case Hexagon::AND_rr_cPt:
1603    case Hexagon::AND_rr_cNotPt:
1604    case Hexagon::OR_rr_cPt:
1605    case Hexagon::OR_rr_cNotPt:
1606    case Hexagon::SUB_rr_cPt:
1607    case Hexagon::SUB_rr_cNotPt:
1608    case Hexagon::COMBINE_rr_cPt:
1609    case Hexagon::COMBINE_rr_cNotPt:
1610      return true;
1611    case Hexagon::ASLH_cPt_V4:
1612    case Hexagon::ASLH_cNotPt_V4:
1613    case Hexagon::ASRH_cPt_V4:
1614    case Hexagon::ASRH_cNotPt_V4:
1615    case Hexagon::SXTB_cPt_V4:
1616    case Hexagon::SXTB_cNotPt_V4:
1617    case Hexagon::SXTH_cPt_V4:
1618    case Hexagon::SXTH_cNotPt_V4:
1619    case Hexagon::ZXTB_cPt_V4:
1620    case Hexagon::ZXTB_cNotPt_V4:
1621    case Hexagon::ZXTH_cPt_V4:
1622    case Hexagon::ZXTH_cNotPt_V4:
1623      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1624
1625    default:
1626      return false;
1627  }
1628}
1629
1630
1631bool HexagonInstrInfo::
1632isConditionalLoad (const MachineInstr* MI) const {
1633  const HexagonRegisterInfo& QRI = getRegisterInfo();
1634  switch (MI->getOpcode())
1635  {
1636    case Hexagon::LDrid_cPt :
1637    case Hexagon::LDrid_cNotPt :
1638    case Hexagon::LDrid_indexed_cPt :
1639    case Hexagon::LDrid_indexed_cNotPt :
1640    case Hexagon::LDriw_cPt :
1641    case Hexagon::LDriw_cNotPt :
1642    case Hexagon::LDriw_indexed_cPt :
1643    case Hexagon::LDriw_indexed_cNotPt :
1644    case Hexagon::LDrih_cPt :
1645    case Hexagon::LDrih_cNotPt :
1646    case Hexagon::LDrih_indexed_cPt :
1647    case Hexagon::LDrih_indexed_cNotPt :
1648    case Hexagon::LDrib_cPt :
1649    case Hexagon::LDrib_cNotPt :
1650    case Hexagon::LDrib_indexed_cPt :
1651    case Hexagon::LDrib_indexed_cNotPt :
1652    case Hexagon::LDriuh_cPt :
1653    case Hexagon::LDriuh_cNotPt :
1654    case Hexagon::LDriuh_indexed_cPt :
1655    case Hexagon::LDriuh_indexed_cNotPt :
1656    case Hexagon::LDriub_cPt :
1657    case Hexagon::LDriub_cNotPt :
1658    case Hexagon::LDriub_indexed_cPt :
1659    case Hexagon::LDriub_indexed_cNotPt :
1660      return true;
1661    case Hexagon::POST_LDrid_cPt :
1662    case Hexagon::POST_LDrid_cNotPt :
1663    case Hexagon::POST_LDriw_cPt :
1664    case Hexagon::POST_LDriw_cNotPt :
1665    case Hexagon::POST_LDrih_cPt :
1666    case Hexagon::POST_LDrih_cNotPt :
1667    case Hexagon::POST_LDrib_cPt :
1668    case Hexagon::POST_LDrib_cNotPt :
1669    case Hexagon::POST_LDriuh_cPt :
1670    case Hexagon::POST_LDriuh_cNotPt :
1671    case Hexagon::POST_LDriub_cPt :
1672    case Hexagon::POST_LDriub_cNotPt :
1673      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1674    case Hexagon::LDrid_indexed_cPt_V4 :
1675    case Hexagon::LDrid_indexed_cNotPt_V4 :
1676    case Hexagon::LDrid_indexed_shl_cPt_V4 :
1677    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1678    case Hexagon::LDrib_indexed_cPt_V4 :
1679    case Hexagon::LDrib_indexed_cNotPt_V4 :
1680    case Hexagon::LDrib_indexed_shl_cPt_V4 :
1681    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1682    case Hexagon::LDriub_indexed_cPt_V4 :
1683    case Hexagon::LDriub_indexed_cNotPt_V4 :
1684    case Hexagon::LDriub_indexed_shl_cPt_V4 :
1685    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1686    case Hexagon::LDrih_indexed_cPt_V4 :
1687    case Hexagon::LDrih_indexed_cNotPt_V4 :
1688    case Hexagon::LDrih_indexed_shl_cPt_V4 :
1689    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1690    case Hexagon::LDriuh_indexed_cPt_V4 :
1691    case Hexagon::LDriuh_indexed_cNotPt_V4 :
1692    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1693    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1694    case Hexagon::LDriw_indexed_cPt_V4 :
1695    case Hexagon::LDriw_indexed_cNotPt_V4 :
1696    case Hexagon::LDriw_indexed_shl_cPt_V4 :
1697    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1698      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1699    default:
1700      return false;
1701  }
1702}
1703
1704DFAPacketizer *HexagonInstrInfo::
1705CreateTargetScheduleState(const TargetMachine *TM,
1706                           const ScheduleDAG *DAG) const {
1707  const InstrItineraryData *II = TM->getInstrItineraryData();
1708  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1709}
1710
1711bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1712                                            const MachineBasicBlock *MBB,
1713                                            const MachineFunction &MF) const {
1714  // Debug info is never a scheduling boundary. It's necessary to be explicit
1715  // due to the special treatment of IT instructions below, otherwise a
1716  // dbg_value followed by an IT will result in the IT instruction being
1717  // considered a scheduling hazard, which is wrong. It should be the actual
1718  // instruction preceding the dbg_value instruction(s), just like it is
1719  // when debug info is not present.
1720  if (MI->isDebugValue())
1721    return false;
1722
1723  // Terminators and labels can't be scheduled around.
1724  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
1725    return true;
1726
1727  return false;
1728}
1729