MSP430InstrInfo.cpp revision 746ad69e088176819981b4b2c5ac8dcd49f5e60e 
1//===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430.h"
15#include "MSP430InstrInfo.h"
16#include "MSP430MachineFunctionInfo.h"
17#include "MSP430TargetMachine.h"
18#include "MSP430GenInstrInfo.inc"
19#include "llvm/Function.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/PseudoSourceValue.h"
24#include "llvm/Support/ErrorHandling.h"
25
26using namespace llvm;
27
28MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
29  : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
30    RI(tm, *this), TM(tm) {}
31
32void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
33                                          MachineBasicBlock::iterator MI,
34                                    unsigned SrcReg, bool isKill, int FrameIdx,
35                                          const TargetRegisterClass *RC,
36                                          const TargetRegisterInfo *TRI) const {
37  DebugLoc DL;
38  if (MI != MBB.end()) DL = MI->getDebugLoc();
39  MachineFunction &MF = *MBB.getParent();
40  MachineFrameInfo &MFI = *MF.getFrameInfo();
41
42  MachineMemOperand *MMO =
43    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
44                            MachineMemOperand::MOStore, 0,
45                            MFI.getObjectSize(FrameIdx),
46                            MFI.getObjectAlignment(FrameIdx));
47
48  if (RC == &MSP430::GR16RegClass)
49    BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
50      .addFrameIndex(FrameIdx).addImm(0)
51      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
52  else if (RC == &MSP430::GR8RegClass)
53    BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
54      .addFrameIndex(FrameIdx).addImm(0)
55      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56  else
57    llvm_unreachable("Cannot store this register to stack slot!");
58}
59
60void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61                                           MachineBasicBlock::iterator MI,
62                                           unsigned DestReg, int FrameIdx,
63                                           const TargetRegisterClass *RC,
64                                           const TargetRegisterInfo *TRI) const{
65  DebugLoc DL;
66  if (MI != MBB.end()) DL = MI->getDebugLoc();
67  MachineFunction &MF = *MBB.getParent();
68  MachineFrameInfo &MFI = *MF.getFrameInfo();
69
70  MachineMemOperand *MMO =
71    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
72                            MachineMemOperand::MOLoad, 0,
73                            MFI.getObjectSize(FrameIdx),
74                            MFI.getObjectAlignment(FrameIdx));
75
76  if (RC == &MSP430::GR16RegClass)
77    BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
78      .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
79  else if (RC == &MSP430::GR8RegClass)
80    BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
81      .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
82  else
83    llvm_unreachable("Cannot store this register to stack slot!");
84}
85
86bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
87                                   MachineBasicBlock::iterator I,
88                                   unsigned DestReg, unsigned SrcReg,
89                                   const TargetRegisterClass *DestRC,
90                                   const TargetRegisterClass *SrcRC) const {
91  DebugLoc DL;
92  if (I != MBB.end()) DL = I->getDebugLoc();
93
94  if (DestRC == SrcRC) {
95    unsigned Opc;
96    if (DestRC == &MSP430::GR16RegClass) {
97      Opc = MSP430::MOV16rr;
98    } else if (DestRC == &MSP430::GR8RegClass) {
99      Opc = MSP430::MOV8rr;
100    } else {
101      return false;
102    }
103
104    BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
105    return true;
106  }
107
108  return false;
109}
110
111bool
112MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
113                             unsigned &SrcReg, unsigned &DstReg,
114                             unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
115  SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
116
117  switch (MI.getOpcode()) {
118  default:
119    return false;
120  case MSP430::MOV8rr:
121  case MSP430::MOV16rr:
122   assert(MI.getNumOperands() >= 2 &&
123           MI.getOperand(0).isReg() &&
124           MI.getOperand(1).isReg() &&
125           "invalid register-register move instruction");
126    SrcReg = MI.getOperand(1).getReg();
127    DstReg = MI.getOperand(0).getReg();
128    return true;
129  }
130}
131
132bool
133MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
134                                           MachineBasicBlock::iterator MI,
135                                const std::vector<CalleeSavedInfo> &CSI) const {
136  if (CSI.empty())
137    return false;
138
139  DebugLoc DL;
140  if (MI != MBB.end()) DL = MI->getDebugLoc();
141
142  MachineFunction &MF = *MBB.getParent();
143  MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
144  MFI->setCalleeSavedFrameSize(CSI.size() * 2);
145
146  for (unsigned i = CSI.size(); i != 0; --i) {
147    unsigned Reg = CSI[i-1].getReg();
148    // Add the callee-saved register as live-in. It's killed at the spill.
149    MBB.addLiveIn(Reg);
150    BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
151      .addReg(Reg, RegState::Kill);
152  }
153  return true;
154}
155
156bool
157MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
158                                             MachineBasicBlock::iterator MI,
159                                const std::vector<CalleeSavedInfo> &CSI) const {
160  if (CSI.empty())
161    return false;
162
163  DebugLoc DL;
164  if (MI != MBB.end()) DL = MI->getDebugLoc();
165
166  for (unsigned i = 0, e = CSI.size(); i != e; ++i)
167    BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
168
169  return true;
170}
171
172unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
173  MachineBasicBlock::iterator I = MBB.end();
174  unsigned Count = 0;
175
176  while (I != MBB.begin()) {
177    --I;
178    if (I->isDebugValue())
179      continue;
180    if (I->getOpcode() != MSP430::JMP &&
181        I->getOpcode() != MSP430::JCC &&
182        I->getOpcode() != MSP430::Br &&
183        I->getOpcode() != MSP430::Bm)
184      break;
185    // Remove the branch.
186    I->eraseFromParent();
187    I = MBB.end();
188    ++Count;
189  }
190
191  return Count;
192}
193
194bool MSP430InstrInfo::
195ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
196  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
197
198  MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
199
200  switch (CC) {
201  default:
202    assert(0 && "Invalid branch condition!");
203    break;
204  case MSP430CC::COND_E:
205    CC = MSP430CC::COND_NE;
206    break;
207  case MSP430CC::COND_NE:
208    CC = MSP430CC::COND_E;
209    break;
210  case MSP430CC::COND_L:
211    CC = MSP430CC::COND_GE;
212    break;
213  case MSP430CC::COND_GE:
214    CC = MSP430CC::COND_L;
215    break;
216  case MSP430CC::COND_HS:
217    CC = MSP430CC::COND_LO;
218    break;
219  case MSP430CC::COND_LO:
220    CC = MSP430CC::COND_HS;
221    break;
222  }
223
224  Cond[0].setImm(CC);
225  return false;
226}
227
228bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
229  const TargetInstrDesc &TID = MI->getDesc();
230  if (!TID.isTerminator()) return false;
231
232  // Conditional branch is a special case.
233  if (TID.isBranch() && !TID.isBarrier())
234    return true;
235  if (!TID.isPredicable())
236    return true;
237  return !isPredicated(MI);
238}
239
240bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
241                                    MachineBasicBlock *&TBB,
242                                    MachineBasicBlock *&FBB,
243                                    SmallVectorImpl<MachineOperand> &Cond,
244                                    bool AllowModify) const {
245  // Start from the bottom of the block and work up, examining the
246  // terminator instructions.
247  MachineBasicBlock::iterator I = MBB.end();
248  while (I != MBB.begin()) {
249    --I;
250    if (I->isDebugValue())
251      continue;
252
253    // Working from the bottom, when we see a non-terminator
254    // instruction, we're done.
255    if (!isUnpredicatedTerminator(I))
256      break;
257
258    // A terminator that isn't a branch can't easily be handled
259    // by this analysis.
260    if (!I->getDesc().isBranch())
261      return true;
262
263    // Cannot handle indirect branches.
264    if (I->getOpcode() == MSP430::Br ||
265        I->getOpcode() == MSP430::Bm)
266      return true;
267
268    // Handle unconditional branches.
269    if (I->getOpcode() == MSP430::JMP) {
270      if (!AllowModify) {
271        TBB = I->getOperand(0).getMBB();
272        continue;
273      }
274
275      // If the block has any instructions after a JMP, delete them.
276      while (llvm::next(I) != MBB.end())
277        llvm::next(I)->eraseFromParent();
278      Cond.clear();
279      FBB = 0;
280
281      // Delete the JMP if it's equivalent to a fall-through.
282      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
283        TBB = 0;
284        I->eraseFromParent();
285        I = MBB.end();
286        continue;
287      }
288
289      // TBB is used to indicate the unconditinal destination.
290      TBB = I->getOperand(0).getMBB();
291      continue;
292    }
293
294    // Handle conditional branches.
295    assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
296    MSP430CC::CondCodes BranchCode =
297      static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
298    if (BranchCode == MSP430CC::COND_INVALID)
299      return true;  // Can't handle weird stuff.
300
301    // Working from the bottom, handle the first conditional branch.
302    if (Cond.empty()) {
303      FBB = TBB;
304      TBB = I->getOperand(0).getMBB();
305      Cond.push_back(MachineOperand::CreateImm(BranchCode));
306      continue;
307    }
308
309    // Handle subsequent conditional branches. Only handle the case where all
310    // conditional branches branch to the same destination.
311    assert(Cond.size() == 1);
312    assert(TBB);
313
314    // Only handle the case where all conditional branches branch to
315    // the same destination.
316    if (TBB != I->getOperand(0).getMBB())
317      return true;
318
319    MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
320    // If the conditions are the same, we can leave them alone.
321    if (OldBranchCode == BranchCode)
322      continue;
323
324    return true;
325  }
326
327  return false;
328}
329
330unsigned
331MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
332                              MachineBasicBlock *FBB,
333                            const SmallVectorImpl<MachineOperand> &Cond) const {
334  // FIXME this should probably have a DebugLoc operand
335  DebugLoc DL;
336
337  // Shouldn't be a fall through.
338  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
339  assert((Cond.size() == 1 || Cond.size() == 0) &&
340         "MSP430 branch conditions have one component!");
341
342  if (Cond.empty()) {
343    // Unconditional branch?
344    assert(!FBB && "Unconditional branch with multiple successors!");
345    BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
346    return 1;
347  }
348
349  // Conditional branch.
350  unsigned Count = 0;
351  BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
352  ++Count;
353
354  if (FBB) {
355    // Two-way Conditional branch. Insert the second branch.
356    BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
357    ++Count;
358  }
359  return Count;
360}
361
362/// GetInstSize - Return the number of bytes of code the specified
363/// instruction may be.  This returns the maximum number of bytes.
364///
365unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
366  const TargetInstrDesc &Desc = MI->getDesc();
367
368  switch (Desc.TSFlags & MSP430II::SizeMask) {
369  default:
370    switch (Desc.getOpcode()) {
371    default:
372      assert(0 && "Unknown instruction size!");
373    case TargetOpcode::DBG_LABEL:
374    case TargetOpcode::EH_LABEL:
375    case TargetOpcode::IMPLICIT_DEF:
376    case TargetOpcode::KILL:
377    case TargetOpcode::DBG_VALUE:
378      return 0;
379    case TargetOpcode::INLINEASM: {
380      const MachineFunction *MF = MI->getParent()->getParent();
381      const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
382      return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
383                                    *MF->getTarget().getMCAsmInfo());
384    }
385    }
386  case MSP430II::SizeSpecial:
387    switch (MI->getOpcode()) {
388    default:
389      assert(0 && "Unknown instruction size!");
390    case MSP430::SAR8r1c:
391    case MSP430::SAR16r1c:
392      return 4;
393    }
394  case MSP430II::Size2Bytes:
395    return 2;
396  case MSP430II::Size4Bytes:
397    return 4;
398  case MSP430II::Size6Bytes:
399    return 6;
400  }
401
402  return 6;
403}
404