PPCTargetMachine.cpp revision ebdeeab812beec0385b445f3d4c41a114e0d972f 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC.h"
15#include "PPCMCAsmInfo.h"
16#include "PPCTargetMachine.h"
17#include "llvm/PassManager.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/Target/TargetOptions.h"
20#include "llvm/Target/TargetRegistry.h"
21#include "llvm/Support/FormattedStream.h"
22using namespace llvm;
23
24static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
25  Triple TheTriple(TT);
26  bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
27  if (TheTriple.isOSDarwin())
28    return new PPCMCAsmInfoDarwin(isPPC64);
29  return new PPCLinuxMCAsmInfo(isPPC64);
30
31}
32
33// This is duplicated code. Refactor this.
34static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
35                                    MCContext &Ctx, TargetAsmBackend &TAB,
36                                    raw_ostream &OS,
37                                    MCCodeEmitter *Emitter,
38                                    bool RelaxAll,
39                                    bool NoExecStack) {
40  if (Triple(TT).isOSDarwin())
41    return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
42
43  return NULL;
44}
45
46extern "C" void LLVMInitializePowerPCTarget() {
47  // Register the targets
48  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
49  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
50
51  RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
52  RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
53
54  // Register the MC Code Emitter
55  TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
56  TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
57
58
59  // Register the asm backend.
60  TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
61  TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
62
63  // Register the object streamer.
64  TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
65  TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
66}
67
68
69PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
70                                   const std::string &CPU,
71                                   const std::string &FS, bool is64Bit)
72  : LLVMTargetMachine(T, TT, CPU, FS),
73    Subtarget(TT, CPU, FS, is64Bit),
74    DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
75    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
76    TLInfo(*this), TSInfo(*this),
77    InstrItins(Subtarget.getInstrItineraryData()) {
78
79  if (getRelocationModel() == Reloc::Default) {
80    if (Subtarget.isDarwin())
81      setRelocationModel(Reloc::DynamicNoPIC);
82    else
83      setRelocationModel(Reloc::Static);
84  }
85}
86
87/// Override this for PowerPC.  Tail merging happily breaks up instruction issue
88/// groups, which typically degrades performance.
89bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
90
91PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
92                                       const std::string &CPU,
93                                       const std::string &FS)
94  : PPCTargetMachine(T, TT, CPU, FS, false) {
95}
96
97
98PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
99                                       const std::string &CPU,
100                                       const std::string &FS)
101  : PPCTargetMachine(T, TT, CPU, FS, true) {
102}
103
104
105//===----------------------------------------------------------------------===//
106// Pass Pipeline Configuration
107//===----------------------------------------------------------------------===//
108
109bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
110                                       CodeGenOpt::Level OptLevel) {
111  // Install an instruction selector.
112  PM.add(createPPCISelDag(*this));
113  return false;
114}
115
116bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
117                                      CodeGenOpt::Level OptLevel) {
118  // Must run branch selection immediately preceding the asm printer.
119  PM.add(createPPCBranchSelectionPass());
120  return false;
121}
122
123bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
124                                      CodeGenOpt::Level OptLevel,
125                                      JITCodeEmitter &JCE) {
126  // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
127  // FIXME: This should be moved to TargetJITInfo!!
128  if (Subtarget.isPPC64()) {
129    // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
130    // instructions to materialize arbitrary global variable + function +
131    // constant pool addresses.
132    setRelocationModel(Reloc::PIC_);
133    // Temporary workaround for the inability of PPC64 JIT to handle jump
134    // tables.
135    DisableJumpTables = true;
136  } else {
137    setRelocationModel(Reloc::Static);
138  }
139
140  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
141  // writing?
142  Subtarget.SetJITMode();
143
144  // Machine code emitter pass for PowerPC.
145  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
146
147  return false;
148}
149