X86MCTargetDesc.cpp revision 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides X86 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86MCTargetDesc.h"
15#include "X86MCAsmInfo.h"
16#include "InstPrinter/X86ATTInstPrinter.h"
17#include "InstPrinter/X86IntelInstPrinter.h"
18#include "llvm/MC/MachineLocation.h"
19#include "llvm/MC/MCCodeGenInfo.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/ADT/Triple.h"
26#include "llvm/Support/Host.h"
27#include "llvm/Support/TargetRegistry.h"
28
29#define GET_REGINFO_MC_DESC
30#include "X86GenRegisterInfo.inc"
31
32#define GET_INSTRINFO_MC_DESC
33#include "X86GenInstrInfo.inc"
34
35#define GET_SUBTARGETINFO_MC_DESC
36#include "X86GenSubtargetInfo.inc"
37
38using namespace llvm;
39
40
41std::string X86_MC::ParseX86Triple(StringRef TT) {
42  Triple TheTriple(TT);
43  if (TheTriple.getArch() == Triple::x86_64)
44    return "+64bit-mode";
45  return "-64bit-mode";
46}
47
48/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
49/// specified arguments.  If we can't run cpuid on the host, return true.
50bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
51                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
52#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
53  #if defined(__GNUC__)
54    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
55    asm ("movq\t%%rbx, %%rsi\n\t"
56         "cpuid\n\t"
57         "xchgq\t%%rbx, %%rsi\n\t"
58         : "=a" (*rEAX),
59           "=S" (*rEBX),
60           "=c" (*rECX),
61           "=d" (*rEDX)
62         :  "a" (value));
63    return false;
64  #elif defined(_MSC_VER)
65    int registers[4];
66    __cpuid(registers, value);
67    *rEAX = registers[0];
68    *rEBX = registers[1];
69    *rECX = registers[2];
70    *rEDX = registers[3];
71    return false;
72  #endif
73#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
74  #if defined(__GNUC__)
75    asm ("movl\t%%ebx, %%esi\n\t"
76         "cpuid\n\t"
77         "xchgl\t%%ebx, %%esi\n\t"
78         : "=a" (*rEAX),
79           "=S" (*rEBX),
80           "=c" (*rECX),
81           "=d" (*rEDX)
82         :  "a" (value));
83    return false;
84  #elif defined(_MSC_VER)
85    __asm {
86      mov   eax,value
87      cpuid
88      mov   esi,rEAX
89      mov   dword ptr [esi],eax
90      mov   esi,rEBX
91      mov   dword ptr [esi],ebx
92      mov   esi,rECX
93      mov   dword ptr [esi],ecx
94      mov   esi,rEDX
95      mov   dword ptr [esi],edx
96    }
97    return false;
98  #endif
99#endif
100  return true;
101}
102
103void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
104                               unsigned &Model) {
105  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
106  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
107  if (Family == 6 || Family == 0xf) {
108    if (Family == 0xf)
109      // Examine extended family ID if family ID is F.
110      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
111    // Examine extended model ID if family ID is 6 or F.
112    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
113  }
114}
115
116unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
117  Triple TheTriple(TT);
118  if (TheTriple.getArch() == Triple::x86_64)
119    return DWARFFlavour::X86_64;
120
121  if (TheTriple.isOSDarwin())
122    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
123  if (TheTriple.getOS() == Triple::MinGW32 ||
124      TheTriple.getOS() == Triple::Cygwin)
125    // Unsupported by now, just quick fallback
126    return DWARFFlavour::X86_32_Generic;
127  return DWARFFlavour::X86_32_Generic;
128}
129
130/// getX86RegNum - This function maps LLVM register identifiers to their X86
131/// specific numbering, which is used in various places encoding instructions.
132unsigned X86_MC::getX86RegNum(unsigned RegNo) {
133  switch(RegNo) {
134  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
135  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
136  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
137  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
138  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
139    return N86::ESP;
140  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
141    return N86::EBP;
142  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
143    return N86::ESI;
144  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
145    return N86::EDI;
146
147  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
148    return N86::EAX;
149  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
150    return N86::ECX;
151  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
152    return N86::EDX;
153  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
154    return N86::EBX;
155  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
156    return N86::ESP;
157  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
158    return N86::EBP;
159  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
160    return N86::ESI;
161  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
162    return N86::EDI;
163
164  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
165  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
166    return RegNo-X86::ST0;
167
168  case X86::XMM0: case X86::XMM8:
169  case X86::YMM0: case X86::YMM8: case X86::MM0:
170    return 0;
171  case X86::XMM1: case X86::XMM9:
172  case X86::YMM1: case X86::YMM9: case X86::MM1:
173    return 1;
174  case X86::XMM2: case X86::XMM10:
175  case X86::YMM2: case X86::YMM10: case X86::MM2:
176    return 2;
177  case X86::XMM3: case X86::XMM11:
178  case X86::YMM3: case X86::YMM11: case X86::MM3:
179    return 3;
180  case X86::XMM4: case X86::XMM12:
181  case X86::YMM4: case X86::YMM12: case X86::MM4:
182    return 4;
183  case X86::XMM5: case X86::XMM13:
184  case X86::YMM5: case X86::YMM13: case X86::MM5:
185    return 5;
186  case X86::XMM6: case X86::XMM14:
187  case X86::YMM6: case X86::YMM14: case X86::MM6:
188    return 6;
189  case X86::XMM7: case X86::XMM15:
190  case X86::YMM7: case X86::YMM15: case X86::MM7:
191    return 7;
192
193  case X86::ES: return 0;
194  case X86::CS: return 1;
195  case X86::SS: return 2;
196  case X86::DS: return 3;
197  case X86::FS: return 4;
198  case X86::GS: return 5;
199
200  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
201  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
202  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
203  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
204  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
205  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
206  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
207  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
208
209  // Pseudo index registers are equivalent to a "none"
210  // scaled index (See Intel Manual 2A, table 2-3)
211  case X86::EIZ:
212  case X86::RIZ:
213    return 4;
214
215  default:
216    assert((int(RegNo) > 0) && "Unknown physical register!");
217    return 0;
218  }
219}
220
221void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
222  // FIXME: TableGen these.
223  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
224    int SEH = X86_MC::getX86RegNum(Reg);
225    switch (Reg) {
226    case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
227    case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
228    case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
229    case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
230    case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
231    case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
232    case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
233    case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
234    case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
235    case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
236    case X86::YMM8:  case X86::YMM9:  case X86::YMM10: case X86::YMM11:
237    case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
238      SEH += 8;
239      break;
240    }
241    MRI->mapLLVMRegToSEHReg(Reg, SEH);
242  }
243}
244
245MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
246                                                  StringRef FS) {
247  std::string ArchFS = X86_MC::ParseX86Triple(TT);
248  if (!FS.empty()) {
249    if (!ArchFS.empty())
250      ArchFS = ArchFS + "," + FS.str();
251    else
252      ArchFS = FS;
253  }
254
255  std::string CPUName = CPU;
256  if (CPUName.empty()) {
257#if defined (__x86_64__) || defined(__i386__)
258    CPUName = sys::getHostCPUName();
259#else
260    CPUName = "generic";
261#endif
262  }
263
264  MCSubtargetInfo *X = new MCSubtargetInfo();
265  InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
266  return X;
267}
268
269static MCInstrInfo *createX86MCInstrInfo() {
270  MCInstrInfo *X = new MCInstrInfo();
271  InitX86MCInstrInfo(X);
272  return X;
273}
274
275static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
276  Triple TheTriple(TT);
277  unsigned RA = (TheTriple.getArch() == Triple::x86_64)
278    ? X86::RIP     // Should have dwarf #16.
279    : X86::EIP;    // Should have dwarf #8.
280
281  MCRegisterInfo *X = new MCRegisterInfo();
282  InitX86MCRegisterInfo(X, RA,
283                        X86_MC::getDwarfRegFlavour(TT, false),
284                        X86_MC::getDwarfRegFlavour(TT, true));
285  X86_MC::InitLLVM2SEHRegisterMapping(X);
286  return X;
287}
288
289static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
290  Triple TheTriple(TT);
291  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
292
293  MCAsmInfo *MAI;
294  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
295    if (is64Bit)
296      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
297    else
298      MAI = new X86MCAsmInfoDarwin(TheTriple);
299  } else if (TheTriple.isOSWindows()) {
300    MAI = new X86MCAsmInfoCOFF(TheTriple);
301  } else {
302    MAI = new X86ELFMCAsmInfo(TheTriple);
303  }
304
305  // Initialize initial frame state.
306  // Calculate amount of bytes used for return address storing
307  int stackGrowth = is64Bit ? -8 : -4;
308
309  // Initial state of the frame pointer is esp+stackGrowth.
310  MachineLocation Dst(MachineLocation::VirtualFP);
311  MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
312  MAI->addInitialFrameState(0, Dst, Src);
313
314  // Add return address to move list
315  MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
316  MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
317  MAI->addInitialFrameState(0, CSDst, CSSrc);
318
319  return MAI;
320}
321
322static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
323                                             CodeModel::Model CM) {
324  MCCodeGenInfo *X = new MCCodeGenInfo();
325
326  Triple T(TT);
327  bool is64Bit = T.getArch() == Triple::x86_64;
328
329  if (RM == Reloc::Default) {
330    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
331    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
332    // use static relocation model by default.
333    if (T.isOSDarwin()) {
334      if (is64Bit)
335        RM = Reloc::PIC_;
336      else
337        RM = Reloc::DynamicNoPIC;
338    } else if (T.isOSWindows() && is64Bit)
339      RM = Reloc::PIC_;
340    else
341      RM = Reloc::Static;
342  }
343
344  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
345  // is defined as a model for code which may be used in static or dynamic
346  // executables but not necessarily a shared library. On X86-32 we just
347  // compile in -static mode, in x86-64 we use PIC.
348  if (RM == Reloc::DynamicNoPIC) {
349    if (is64Bit)
350      RM = Reloc::PIC_;
351    else if (!T.isOSDarwin())
352      RM = Reloc::Static;
353  }
354
355  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
356  // the Mach-O file format doesn't support it.
357  if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
358    RM = Reloc::PIC_;
359
360  // For static codegen, if we're not already set, use Small codegen.
361  if (CM == CodeModel::Default)
362    CM = CodeModel::Small;
363  else if (CM == CodeModel::JITDefault)
364    // 64-bit JIT places everything in the same buffer except external funcs.
365    CM = is64Bit ? CodeModel::Large : CodeModel::Small;
366
367  X->InitMCCodeGenInfo(RM, CM);
368  return X;
369}
370
371static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
372                                    MCContext &Ctx, MCAsmBackend &MAB,
373                                    raw_ostream &_OS,
374                                    MCCodeEmitter *_Emitter,
375                                    bool RelaxAll,
376                                    bool NoExecStack) {
377  Triple TheTriple(TT);
378
379  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
380    return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
381
382  if (TheTriple.isOSWindows())
383    return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
384
385  return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
386}
387
388static MCInstPrinter *createX86MCInstPrinter(const Target &T,
389                                             unsigned SyntaxVariant,
390                                             const MCAsmInfo &MAI) {
391  if (SyntaxVariant == 0)
392    return new X86ATTInstPrinter(MAI);
393  if (SyntaxVariant == 1)
394    return new X86IntelInstPrinter(MAI);
395  return 0;
396}
397
398static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
399  return new MCInstrAnalysis(Info);
400}
401
402// Force static initialization.
403extern "C" void LLVMInitializeX86TargetMC() {
404  // Register the MC asm info.
405  RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
406  RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
407
408  // Register the MC codegen info.
409  RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
410  RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
411
412  // Register the MC instruction info.
413  TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
414  TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
415
416  // Register the MC register info.
417  TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
418  TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
419
420  // Register the MC subtarget info.
421  TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
422                                          X86_MC::createX86MCSubtargetInfo);
423  TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
424                                          X86_MC::createX86MCSubtargetInfo);
425
426  // Register the MC instruction analyzer.
427  TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
428                                          createX86MCInstrAnalysis);
429  TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
430                                          createX86MCInstrAnalysis);
431
432  // Register the code emitter.
433  TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
434                                        createX86MCCodeEmitter);
435  TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
436                                        createX86MCCodeEmitter);
437
438  // Register the asm backend.
439  TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
440                                       createX86_32AsmBackend);
441  TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
442                                       createX86_64AsmBackend);
443
444  // Register the object streamer.
445  TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
446                                           createMCStreamer);
447  TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
448                                           createMCStreamer);
449
450  // Register the MCInstPrinter.
451  TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
452                                        createX86MCInstPrinter);
453  TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
454                                        createX86MCInstPrinter);
455}
456