X86MCTargetDesc.cpp revision 893a045cdbdc08fdaa5a62a24838be2df35cb628 
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides X86 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86MCTargetDesc.h"
15#include "X86MCAsmInfo.h"
16#include "InstPrinter/X86ATTInstPrinter.h"
17#include "InstPrinter/X86IntelInstPrinter.h"
18#include "llvm/MC/MachineLocation.h"
19#include "llvm/MC/MCCodeGenInfo.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/ADT/Triple.h"
26#include "llvm/Support/Host.h"
27#include "llvm/Support/TargetRegistry.h"
28
29#define GET_REGINFO_MC_DESC
30#include "X86GenRegisterInfo.inc"
31
32#define GET_INSTRINFO_MC_DESC
33#include "X86GenInstrInfo.inc"
34
35#define GET_SUBTARGETINFO_MC_DESC
36#include "X86GenSubtargetInfo.inc"
37
38using namespace llvm;
39
40
41std::string X86_MC::ParseX86Triple(StringRef TT) {
42  Triple TheTriple(TT);
43  std::string FS;
44  if (TheTriple.getArch() == Triple::x86_64)
45    FS = "+64bit-mode";
46  else
47    FS = "-64bit-mode";
48  return FS;
49}
50
51/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
52/// specified arguments.  If we can't run cpuid on the host, return true.
53bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
54                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
55#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
56  #if defined(__GNUC__)
57    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
58    asm ("movq\t%%rbx, %%rsi\n\t"
59         "cpuid\n\t"
60         "xchgq\t%%rbx, %%rsi\n\t"
61         : "=a" (*rEAX),
62           "=S" (*rEBX),
63           "=c" (*rECX),
64           "=d" (*rEDX)
65         :  "a" (value));
66    return false;
67  #elif defined(_MSC_VER)
68    int registers[4];
69    __cpuid(registers, value);
70    *rEAX = registers[0];
71    *rEBX = registers[1];
72    *rECX = registers[2];
73    *rEDX = registers[3];
74    return false;
75  #else
76    return true;
77  #endif
78#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
79  #if defined(__GNUC__)
80    asm ("movl\t%%ebx, %%esi\n\t"
81         "cpuid\n\t"
82         "xchgl\t%%ebx, %%esi\n\t"
83         : "=a" (*rEAX),
84           "=S" (*rEBX),
85           "=c" (*rECX),
86           "=d" (*rEDX)
87         :  "a" (value));
88    return false;
89  #elif defined(_MSC_VER)
90    __asm {
91      mov   eax,value
92      cpuid
93      mov   esi,rEAX
94      mov   dword ptr [esi],eax
95      mov   esi,rEBX
96      mov   dword ptr [esi],ebx
97      mov   esi,rECX
98      mov   dword ptr [esi],ecx
99      mov   esi,rEDX
100      mov   dword ptr [esi],edx
101    }
102    return false;
103  #else
104    return true;
105  #endif
106#else
107  return true;
108#endif
109}
110
111/// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
112/// 4 values in the specified arguments.  If we can't run cpuid on the host,
113/// return true.
114bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
115                               unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
116#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
117  #if defined(__GNUC__)
118    // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
119    asm ("movq\t%%rbx, %%rsi\n\t"
120         "cpuid\n\t"
121         "xchgq\t%%rbx, %%rsi\n\t"
122         : "=a" (*rEAX),
123           "=S" (*rEBX),
124           "=c" (*rECX),
125           "=d" (*rEDX)
126         :  "a" (value),
127            "c" (subleaf));
128    return false;
129  #elif defined(_MSC_VER)
130    // __cpuidex was added in MSVC++ 9.0 SP1
131    #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
132      int registers[4];
133      __cpuidex(registers, value, subleaf);
134      *rEAX = registers[0];
135      *rEBX = registers[1];
136      *rECX = registers[2];
137      *rEDX = registers[3];
138      return false;
139    #else
140      return true;
141    #endif
142  #else
143    return true;
144  #endif
145#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
146  #if defined(__GNUC__)
147    asm ("movl\t%%ebx, %%esi\n\t"
148         "cpuid\n\t"
149         "xchgl\t%%ebx, %%esi\n\t"
150         : "=a" (*rEAX),
151           "=S" (*rEBX),
152           "=c" (*rECX),
153           "=d" (*rEDX)
154         :  "a" (value),
155            "c" (subleaf));
156    return false;
157  #elif defined(_MSC_VER)
158    __asm {
159      mov   eax,value
160      mov   ecx,subleaf
161      cpuid
162      mov   esi,rEAX
163      mov   dword ptr [esi],eax
164      mov   esi,rEBX
165      mov   dword ptr [esi],ebx
166      mov   esi,rECX
167      mov   dword ptr [esi],ecx
168      mov   esi,rEDX
169      mov   dword ptr [esi],edx
170    }
171    return false;
172  #else
173    return true;
174  #endif
175#else
176  return true;
177#endif
178}
179
180void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
181                               unsigned &Model) {
182  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
183  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
184  if (Family == 6 || Family == 0xf) {
185    if (Family == 0xf)
186      // Examine extended family ID if family ID is F.
187      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
188    // Examine extended model ID if family ID is 6 or F.
189    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
190  }
191}
192
193unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
194  Triple TheTriple(TT);
195  if (TheTriple.getArch() == Triple::x86_64)
196    return DWARFFlavour::X86_64;
197
198  if (TheTriple.isOSDarwin())
199    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
200  if (TheTriple.getOS() == Triple::MinGW32 ||
201      TheTriple.getOS() == Triple::Cygwin)
202    // Unsupported by now, just quick fallback
203    return DWARFFlavour::X86_32_Generic;
204  return DWARFFlavour::X86_32_Generic;
205}
206
207/// getX86RegNum - This function maps LLVM register identifiers to their X86
208/// specific numbering, which is used in various places encoding instructions.
209unsigned X86_MC::getX86RegNum(unsigned RegNo) {
210  switch(RegNo) {
211  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
212  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
213  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
214  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
215  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
216    return N86::ESP;
217  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
218    return N86::EBP;
219  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
220    return N86::ESI;
221  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
222    return N86::EDI;
223
224  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
225    return N86::EAX;
226  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
227    return N86::ECX;
228  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
229    return N86::EDX;
230  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
231    return N86::EBX;
232  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
233    return N86::ESP;
234  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
235    return N86::EBP;
236  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
237    return N86::ESI;
238  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
239    return N86::EDI;
240
241  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
242  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
243    return RegNo-X86::ST0;
244
245  case X86::XMM0: case X86::XMM8:
246  case X86::YMM0: case X86::YMM8: case X86::MM0:
247    return 0;
248  case X86::XMM1: case X86::XMM9:
249  case X86::YMM1: case X86::YMM9: case X86::MM1:
250    return 1;
251  case X86::XMM2: case X86::XMM10:
252  case X86::YMM2: case X86::YMM10: case X86::MM2:
253    return 2;
254  case X86::XMM3: case X86::XMM11:
255  case X86::YMM3: case X86::YMM11: case X86::MM3:
256    return 3;
257  case X86::XMM4: case X86::XMM12:
258  case X86::YMM4: case X86::YMM12: case X86::MM4:
259    return 4;
260  case X86::XMM5: case X86::XMM13:
261  case X86::YMM5: case X86::YMM13: case X86::MM5:
262    return 5;
263  case X86::XMM6: case X86::XMM14:
264  case X86::YMM6: case X86::YMM14: case X86::MM6:
265    return 6;
266  case X86::XMM7: case X86::XMM15:
267  case X86::YMM7: case X86::YMM15: case X86::MM7:
268    return 7;
269
270  case X86::ES: return 0;
271  case X86::CS: return 1;
272  case X86::SS: return 2;
273  case X86::DS: return 3;
274  case X86::FS: return 4;
275  case X86::GS: return 5;
276
277  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
278  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
279  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
280  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
281  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
282  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
283  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
284  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
285
286  // Pseudo index registers are equivalent to a "none"
287  // scaled index (See Intel Manual 2A, table 2-3)
288  case X86::EIZ:
289  case X86::RIZ:
290    return 4;
291
292  default:
293    assert((int(RegNo) > 0) && "Unknown physical register!");
294    return 0;
295  }
296}
297
298void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
299  // FIXME: TableGen these.
300  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
301    int SEH = X86_MC::getX86RegNum(Reg);
302    switch (Reg) {
303    case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
304    case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
305    case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
306    case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
307    case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
308    case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
309    case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
310    case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
311    case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
312    case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
313    case X86::YMM8:  case X86::YMM9:  case X86::YMM10: case X86::YMM11:
314    case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
315      SEH += 8;
316      break;
317    }
318    MRI->mapLLVMRegToSEHReg(Reg, SEH);
319  }
320}
321
322MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
323                                                  StringRef FS) {
324  std::string ArchFS = X86_MC::ParseX86Triple(TT);
325  if (!FS.empty()) {
326    if (!ArchFS.empty())
327      ArchFS = ArchFS + "," + FS.str();
328    else
329      ArchFS = FS;
330  }
331
332  std::string CPUName = CPU;
333  if (CPUName.empty()) {
334#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
335    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
336    CPUName = sys::getHostCPUName();
337#else
338    CPUName = "generic";
339#endif
340  }
341
342  MCSubtargetInfo *X = new MCSubtargetInfo();
343  InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
344  return X;
345}
346
347static MCInstrInfo *createX86MCInstrInfo() {
348  MCInstrInfo *X = new MCInstrInfo();
349  InitX86MCInstrInfo(X);
350  return X;
351}
352
353static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
354  Triple TheTriple(TT);
355  unsigned RA = (TheTriple.getArch() == Triple::x86_64)
356    ? X86::RIP     // Should have dwarf #16.
357    : X86::EIP;    // Should have dwarf #8.
358
359  MCRegisterInfo *X = new MCRegisterInfo();
360  InitX86MCRegisterInfo(X, RA,
361                        X86_MC::getDwarfRegFlavour(TT, false),
362                        X86_MC::getDwarfRegFlavour(TT, true));
363  X86_MC::InitLLVM2SEHRegisterMapping(X);
364  return X;
365}
366
367static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
368  Triple TheTriple(TT);
369  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
370
371  MCAsmInfo *MAI;
372  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
373    if (is64Bit)
374      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
375    else
376      MAI = new X86MCAsmInfoDarwin(TheTriple);
377  } else if (TheTriple.getOS() == Triple::Win32) {
378    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
379  } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
380    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
381  } else {
382    MAI = new X86ELFMCAsmInfo(TheTriple);
383  }
384
385  // Initialize initial frame state.
386  // Calculate amount of bytes used for return address storing
387  int stackGrowth = is64Bit ? -8 : -4;
388
389  // Initial state of the frame pointer is esp+stackGrowth.
390  MachineLocation Dst(MachineLocation::VirtualFP);
391  MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
392  MAI->addInitialFrameState(0, Dst, Src);
393
394  // Add return address to move list
395  MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
396  MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
397  MAI->addInitialFrameState(0, CSDst, CSSrc);
398
399  return MAI;
400}
401
402static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
403                                             CodeModel::Model CM,
404                                             CodeGenOpt::Level OL) {
405  MCCodeGenInfo *X = new MCCodeGenInfo();
406
407  Triple T(TT);
408  bool is64Bit = T.getArch() == Triple::x86_64;
409
410  if (RM == Reloc::Default) {
411    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
412    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
413    // use static relocation model by default.
414    if (T.isOSDarwin()) {
415      if (is64Bit)
416        RM = Reloc::PIC_;
417      else
418        RM = Reloc::DynamicNoPIC;
419    } else if (T.isOSWindows() && is64Bit)
420      RM = Reloc::PIC_;
421    else
422      RM = Reloc::Static;
423  }
424
425  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
426  // is defined as a model for code which may be used in static or dynamic
427  // executables but not necessarily a shared library. On X86-32 we just
428  // compile in -static mode, in x86-64 we use PIC.
429  if (RM == Reloc::DynamicNoPIC) {
430    if (is64Bit)
431      RM = Reloc::PIC_;
432    else if (!T.isOSDarwin())
433      RM = Reloc::Static;
434  }
435
436  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
437  // the Mach-O file format doesn't support it.
438  if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
439    RM = Reloc::PIC_;
440
441  // For static codegen, if we're not already set, use Small codegen.
442  if (CM == CodeModel::Default)
443    CM = CodeModel::Small;
444  else if (CM == CodeModel::JITDefault)
445    // 64-bit JIT places everything in the same buffer except external funcs.
446    CM = is64Bit ? CodeModel::Large : CodeModel::Small;
447
448  X->InitMCCodeGenInfo(RM, CM, OL);
449  return X;
450}
451
452static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
453                                    MCContext &Ctx, MCAsmBackend &MAB,
454                                    raw_ostream &_OS,
455                                    MCCodeEmitter *_Emitter,
456                                    bool RelaxAll,
457                                    bool NoExecStack) {
458  Triple TheTriple(TT);
459
460  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
461    return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
462
463  if (TheTriple.isOSWindows())
464    return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
465
466  return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
467}
468
469static MCInstPrinter *createX86MCInstPrinter(const Target &T,
470                                             unsigned SyntaxVariant,
471                                             const MCAsmInfo &MAI,
472                                             const MCSubtargetInfo &STI) {
473  if (SyntaxVariant == 0)
474    return new X86ATTInstPrinter(MAI);
475  if (SyntaxVariant == 1)
476    return new X86IntelInstPrinter(MAI);
477  return 0;
478}
479
480static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
481  return new MCInstrAnalysis(Info);
482}
483
484// Force static initialization.
485extern "C" void LLVMInitializeX86TargetMC() {
486  // Register the MC asm info.
487  RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
488  RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
489
490  // Register the MC codegen info.
491  RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
492  RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
493
494  // Register the MC instruction info.
495  TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
496  TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
497
498  // Register the MC register info.
499  TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
500  TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
501
502  // Register the MC subtarget info.
503  TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
504                                          X86_MC::createX86MCSubtargetInfo);
505  TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
506                                          X86_MC::createX86MCSubtargetInfo);
507
508  // Register the MC instruction analyzer.
509  TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
510                                          createX86MCInstrAnalysis);
511  TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
512                                          createX86MCInstrAnalysis);
513
514  // Register the code emitter.
515  TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
516                                        createX86MCCodeEmitter);
517  TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
518                                        createX86MCCodeEmitter);
519
520  // Register the asm backend.
521  TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
522                                       createX86_32AsmBackend);
523  TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
524                                       createX86_64AsmBackend);
525
526  // Register the object streamer.
527  TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
528                                           createMCStreamer);
529  TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
530                                           createMCStreamer);
531
532  // Register the MCInstPrinter.
533  TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
534                                        createX86MCInstPrinter);
535  TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
536                                        createX86MCInstPrinter);
537}
538