X86MCTargetDesc.cpp revision a87e40f16f1c3117412e01107807e490d6fb29bc 
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides X86 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86MCTargetDesc.h"
15#include "X86MCAsmInfo.h"
16#include "llvm/MC/MachineLocation.h"
17#include "llvm/MC/MCInstrInfo.h"
18#include "llvm/MC/MCRegisterInfo.h"
19#include "llvm/MC/MCStreamer.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/Target/TargetRegistry.h"
22#include "llvm/ADT/Triple.h"
23#include "llvm/Support/Host.h"
24
25#define GET_REGINFO_MC_DESC
26#include "X86GenRegisterInfo.inc"
27
28#define GET_INSTRINFO_MC_DESC
29#include "X86GenInstrInfo.inc"
30
31#define GET_SUBTARGETINFO_MC_DESC
32#include "X86GenSubtargetInfo.inc"
33
34using namespace llvm;
35
36
37std::string X86_MC::ParseX86Triple(StringRef TT) {
38  Triple TheTriple(TT);
39  if (TheTriple.getArch() == Triple::x86_64)
40    return "+64bit-mode";
41  return "-64bit-mode";
42}
43
44/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
45/// specified arguments.  If we can't run cpuid on the host, return true.
46bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
47                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
48#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
49  #if defined(__GNUC__)
50    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
51    asm ("movq\t%%rbx, %%rsi\n\t"
52         "cpuid\n\t"
53         "xchgq\t%%rbx, %%rsi\n\t"
54         : "=a" (*rEAX),
55           "=S" (*rEBX),
56           "=c" (*rECX),
57           "=d" (*rEDX)
58         :  "a" (value));
59    return false;
60  #elif defined(_MSC_VER)
61    int registers[4];
62    __cpuid(registers, value);
63    *rEAX = registers[0];
64    *rEBX = registers[1];
65    *rECX = registers[2];
66    *rEDX = registers[3];
67    return false;
68  #endif
69#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
70  #if defined(__GNUC__)
71    asm ("movl\t%%ebx, %%esi\n\t"
72         "cpuid\n\t"
73         "xchgl\t%%ebx, %%esi\n\t"
74         : "=a" (*rEAX),
75           "=S" (*rEBX),
76           "=c" (*rECX),
77           "=d" (*rEDX)
78         :  "a" (value));
79    return false;
80  #elif defined(_MSC_VER)
81    __asm {
82      mov   eax,value
83      cpuid
84      mov   esi,rEAX
85      mov   dword ptr [esi],eax
86      mov   esi,rEBX
87      mov   dword ptr [esi],ebx
88      mov   esi,rECX
89      mov   dword ptr [esi],ecx
90      mov   esi,rEDX
91      mov   dword ptr [esi],edx
92    }
93    return false;
94  #endif
95#endif
96  return true;
97}
98
99void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
100                               unsigned &Model) {
101  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
102  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
103  if (Family == 6 || Family == 0xf) {
104    if (Family == 0xf)
105      // Examine extended family ID if family ID is F.
106      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
107    // Examine extended model ID if family ID is 6 or F.
108    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
109  }
110}
111
112unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
113  Triple TheTriple(TT);
114  if (TheTriple.getArch() == Triple::x86_64)
115    return DWARFFlavour::X86_64;
116
117  if (TheTriple.isOSDarwin())
118    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
119  if (TheTriple.getOS() == Triple::MinGW32 ||
120      TheTriple.getOS() == Triple::Cygwin)
121    // Unsupported by now, just quick fallback
122    return DWARFFlavour::X86_32_Generic;
123  return DWARFFlavour::X86_32_Generic;
124}
125
126/// getX86RegNum - This function maps LLVM register identifiers to their X86
127/// specific numbering, which is used in various places encoding instructions.
128unsigned X86_MC::getX86RegNum(unsigned RegNo) {
129  switch(RegNo) {
130  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
131  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
132  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
133  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
134  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
135    return N86::ESP;
136  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
137    return N86::EBP;
138  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
139    return N86::ESI;
140  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
141    return N86::EDI;
142
143  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
144    return N86::EAX;
145  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
146    return N86::ECX;
147  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
148    return N86::EDX;
149  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
150    return N86::EBX;
151  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
152    return N86::ESP;
153  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
154    return N86::EBP;
155  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
156    return N86::ESI;
157  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
158    return N86::EDI;
159
160  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
161  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
162    return RegNo-X86::ST0;
163
164  case X86::XMM0: case X86::XMM8:
165  case X86::YMM0: case X86::YMM8: case X86::MM0:
166    return 0;
167  case X86::XMM1: case X86::XMM9:
168  case X86::YMM1: case X86::YMM9: case X86::MM1:
169    return 1;
170  case X86::XMM2: case X86::XMM10:
171  case X86::YMM2: case X86::YMM10: case X86::MM2:
172    return 2;
173  case X86::XMM3: case X86::XMM11:
174  case X86::YMM3: case X86::YMM11: case X86::MM3:
175    return 3;
176  case X86::XMM4: case X86::XMM12:
177  case X86::YMM4: case X86::YMM12: case X86::MM4:
178    return 4;
179  case X86::XMM5: case X86::XMM13:
180  case X86::YMM5: case X86::YMM13: case X86::MM5:
181    return 5;
182  case X86::XMM6: case X86::XMM14:
183  case X86::YMM6: case X86::YMM14: case X86::MM6:
184    return 6;
185  case X86::XMM7: case X86::XMM15:
186  case X86::YMM7: case X86::YMM15: case X86::MM7:
187    return 7;
188
189  case X86::ES: return 0;
190  case X86::CS: return 1;
191  case X86::SS: return 2;
192  case X86::DS: return 3;
193  case X86::FS: return 4;
194  case X86::GS: return 5;
195
196  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
197  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
198  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
199  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
200  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
201  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
202  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
203  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
204
205  // Pseudo index registers are equivalent to a "none"
206  // scaled index (See Intel Manual 2A, table 2-3)
207  case X86::EIZ:
208  case X86::RIZ:
209    return 4;
210
211  default:
212    assert((int(RegNo) > 0) && "Unknown physical register!");
213    return 0;
214  }
215}
216
217void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
218  // FIXME: TableGen these.
219  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
220    int SEH = X86_MC::getX86RegNum(Reg);
221    switch (Reg) {
222    case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
223    case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
224    case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
225    case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
226    case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
227    case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
228    case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
229    case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
230    case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
231    case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
232    case X86::YMM8:  case X86::YMM9:  case X86::YMM10: case X86::YMM11:
233    case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
234      SEH += 8;
235      break;
236    }
237    MRI->mapLLVMRegToSEHReg(Reg, SEH);
238  }
239}
240
241MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
242                                                  StringRef FS) {
243  std::string ArchFS = X86_MC::ParseX86Triple(TT);
244  if (!FS.empty()) {
245    if (!ArchFS.empty())
246      ArchFS = ArchFS + "," + FS.str();
247    else
248      ArchFS = FS;
249  }
250
251  std::string CPUName = CPU;
252  if (CPUName.empty()) {
253#if defined (__x86_64__) || defined(__i386__)
254    CPUName = sys::getHostCPUName();
255#else
256    CPUName = "generic";
257#endif
258  }
259
260  MCSubtargetInfo *X = new MCSubtargetInfo();
261  InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
262  return X;
263}
264
265static MCInstrInfo *createX86MCInstrInfo() {
266  MCInstrInfo *X = new MCInstrInfo();
267  InitX86MCInstrInfo(X);
268  return X;
269}
270
271static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
272  Triple TheTriple(TT);
273  unsigned RA = (TheTriple.getArch() == Triple::x86_64)
274    ? X86::RIP     // Should have dwarf #16.
275    : X86::EIP;    // Should have dwarf #8.
276
277  MCRegisterInfo *X = new MCRegisterInfo();
278  InitX86MCRegisterInfo(X, RA,
279                        X86_MC::getDwarfRegFlavour(TT, false),
280                        X86_MC::getDwarfRegFlavour(TT, true));
281  X86_MC::InitLLVM2SEHRegisterMapping(X);
282  return X;
283}
284
285static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
286  Triple TheTriple(TT);
287  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
288
289  MCAsmInfo *MAI;
290  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
291    if (is64Bit)
292      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
293    else
294      MAI = new X86MCAsmInfoDarwin(TheTriple);
295  } else if (TheTriple.isOSWindows()) {
296    MAI = new X86MCAsmInfoCOFF(TheTriple);
297  } else {
298    MAI = new X86ELFMCAsmInfo(TheTriple);
299  }
300
301  // Initialize initial frame state.
302  // Calculate amount of bytes used for return address storing
303  int stackGrowth = is64Bit ? -8 : -4;
304
305  // Initial state of the frame pointer is esp+stackGrowth.
306  MachineLocation Dst(MachineLocation::VirtualFP);
307  MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
308  MAI->addInitialFrameState(0, Dst, Src);
309
310  // Add return address to move list
311  MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
312  MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
313  MAI->addInitialFrameState(0, CSDst, CSSrc);
314
315  return MAI;
316}
317
318static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
319                                             CodeModel::Model CM) {
320  MCCodeGenInfo *X = new MCCodeGenInfo();
321
322  Triple T(TT);
323  bool is64Bit = T.getArch() == Triple::x86_64;
324
325  if (RM == Reloc::Default) {
326    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
327    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
328    // use static relocation model by default.
329    if (T.isOSDarwin()) {
330      if (is64Bit)
331        RM = Reloc::PIC_;
332      else
333        RM = Reloc::DynamicNoPIC;
334    } else if (T.isOSWindows() && is64Bit)
335      RM = Reloc::PIC_;
336    else
337      RM = Reloc::Static;
338  }
339
340  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
341  // is defined as a model for code which may be used in static or dynamic
342  // executables but not necessarily a shared library. On X86-32 we just
343  // compile in -static mode, in x86-64 we use PIC.
344  if (RM == Reloc::DynamicNoPIC) {
345    if (is64Bit)
346      RM = Reloc::PIC_;
347    else if (!T.isOSDarwin())
348      RM = Reloc::Static;
349  }
350
351  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
352  // the Mach-O file format doesn't support it.
353  if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
354    RM = Reloc::PIC_;
355
356  // For static codegen, if we're not already set, use Small codegen.
357  if (CM == CodeModel::Default)
358    CM = CodeModel::Small;
359  else if (CM == CodeModel::JITDefault)
360    // 64-bit JIT places everything in the same buffer except external funcs.
361    CM = is64Bit ? CodeModel::Large : CodeModel::Small;
362
363  X->InitMCCodeGenInfo(RM, CM);
364  return X;
365}
366
367static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
368                                    MCContext &Ctx, TargetAsmBackend &TAB,
369                                    raw_ostream &_OS,
370                                    MCCodeEmitter *_Emitter,
371                                    bool RelaxAll,
372                                    bool NoExecStack) {
373  Triple TheTriple(TT);
374
375  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
376    return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
377
378  if (TheTriple.isOSWindows())
379    return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
380
381  return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack);
382}
383
384// Force static initialization.
385extern "C" void LLVMInitializeX86TargetMC() {
386  // Register the MC asm info.
387  RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
388  RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
389
390  // Register the MC codegen info.
391  RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
392  RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
393
394  // Register the MC instruction info.
395  TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
396  TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
397
398  // Register the MC register info.
399  TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
400  TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
401
402  // Register the MC subtarget info.
403  TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
404                                          X86_MC::createX86MCSubtargetInfo);
405  TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
406                                          X86_MC::createX86MCSubtargetInfo);
407
408  // Register the code emitter.
409  TargetRegistry::RegisterCodeEmitter(TheX86_32Target,
410                                      createX86MCCodeEmitter);
411  TargetRegistry::RegisterCodeEmitter(TheX86_64Target,
412                                      createX86MCCodeEmitter);
413
414  // Register the asm backend.
415  TargetRegistry::RegisterAsmBackend(TheX86_32Target,
416                                     createX86_32AsmBackend);
417  TargetRegistry::RegisterAsmBackend(TheX86_64Target,
418                                     createX86_64AsmBackend);
419
420  // Register the object streamer.
421  TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
422                                         createMCStreamer);
423  TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
424                                         createMCStreamer);
425}
426