X86FloatingPoint.cpp revision 1087f54ddb70bd2a7ab62608161e4a3f0c345935
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// virtual registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// This pass is hampered by the lack of decent CFG manipulation routines for 16// machine code. In particular, this wants to be able to split critical edges 17// as necessary, traverse the machine basic block CFG in depth-first order, and 18// allow there to be multiple machine basic blocks for each LLVM basicblock 19// (needed for critical edge splitting). 20// 21// In particular, this pass currently barfs on critical edges. Because of this, 22// it requires the instruction selector to insert FP_REG_KILL instructions on 23// the exits of any basic block that has critical edges going from it, or which 24// branch to a critical basic block. 25// 26// FIXME: this is not implemented yet. The stackifier pass only works on local 27// basic blocks. 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "x86-codegen" 32#include "X86.h" 33#include "X86InstrInfo.h" 34#include "llvm/ADT/DepthFirstIterator.h" 35#include "llvm/ADT/SmallPtrSet.h" 36#include "llvm/ADT/SmallVector.h" 37#include "llvm/ADT/Statistic.h" 38#include "llvm/ADT/STLExtras.h" 39#include "llvm/CodeGen/MachineFunctionPass.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineRegisterInfo.h" 42#include "llvm/CodeGen/Passes.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/ErrorHandling.h" 45#include "llvm/Support/raw_ostream.h" 46#include "llvm/Target/TargetInstrInfo.h" 47#include "llvm/Target/TargetMachine.h" 48#include <algorithm> 49using namespace llvm; 50 51STATISTIC(NumFXCH, "Number of fxch instructions inserted"); 52STATISTIC(NumFP , "Number of floating point instructions"); 53 54namespace { 55 struct FPS : public MachineFunctionPass { 56 static char ID; 57 FPS() : MachineFunctionPass(&ID) {} 58 59 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 60 AU.setPreservesCFG(); 61 AU.addPreservedID(MachineLoopInfoID); 62 AU.addPreservedID(MachineDominatorsID); 63 MachineFunctionPass::getAnalysisUsage(AU); 64 } 65 66 virtual bool runOnMachineFunction(MachineFunction &MF); 67 68 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 69 70 private: 71 const TargetInstrInfo *TII; // Machine instruction info. 72 MachineBasicBlock *MBB; // Current basic block 73 unsigned Stack[8]; // FP<n> Registers in each stack slot... 74 unsigned RegMap[8]; // Track which stack slot contains each register 75 unsigned StackTop; // The current top of the FP stack. 76 77 void dumpStack() const { 78 dbgs() << "Stack contents:"; 79 for (unsigned i = 0; i != StackTop; ++i) { 80 dbgs() << " FP" << Stack[i]; 81 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 82 } 83 dbgs() << "\n"; 84 } 85 private: 86 /// isStackEmpty - Return true if the FP stack is empty. 87 bool isStackEmpty() const { 88 return StackTop == 0; 89 } 90 91 // getSlot - Return the stack slot number a particular register number is 92 // in. 93 unsigned getSlot(unsigned RegNo) const { 94 assert(RegNo < 8 && "Regno out of range!"); 95 return RegMap[RegNo]; 96 } 97 98 // getStackEntry - Return the X86::FP<n> register in register ST(i). 99 unsigned getStackEntry(unsigned STi) const { 100 assert(STi < StackTop && "Access past stack top!"); 101 return Stack[StackTop-1-STi]; 102 } 103 104 // getSTReg - Return the X86::ST(i) register which contains the specified 105 // FP<RegNo> register. 106 unsigned getSTReg(unsigned RegNo) const { 107 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 108 } 109 110 // pushReg - Push the specified FP<n> register onto the stack. 111 void pushReg(unsigned Reg) { 112 assert(Reg < 8 && "Register number out of range!"); 113 assert(StackTop < 8 && "Stack overflow!"); 114 Stack[StackTop] = Reg; 115 RegMap[Reg] = StackTop++; 116 } 117 118 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 119 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 120 MachineInstr *MI = I; 121 DebugLoc dl = MI->getDebugLoc(); 122 if (isAtTop(RegNo)) return; 123 124 unsigned STReg = getSTReg(RegNo); 125 unsigned RegOnTop = getStackEntry(0); 126 127 // Swap the slots the regs are in. 128 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 129 130 // Swap stack slot contents. 131 assert(RegMap[RegOnTop] < StackTop); 132 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 133 134 // Emit an fxch to update the runtime processors version of the state. 135 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 136 NumFXCH++; 137 } 138 139 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 140 DebugLoc dl = I->getDebugLoc(); 141 unsigned STReg = getSTReg(RegNo); 142 pushReg(AsReg); // New register on top of stack 143 144 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 145 } 146 147 // popStackAfter - Pop the current value off of the top of the FP stack 148 // after the specified instruction. 149 void popStackAfter(MachineBasicBlock::iterator &I); 150 151 // freeStackSlotAfter - Free the specified register from the register stack, 152 // so that it is no longer in a register. If the register is currently at 153 // the top of the stack, we just pop the current instruction, otherwise we 154 // store the current top-of-stack into the specified slot, then pop the top 155 // of stack. 156 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 157 158 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 159 160 void handleZeroArgFP(MachineBasicBlock::iterator &I); 161 void handleOneArgFP(MachineBasicBlock::iterator &I); 162 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 163 void handleTwoArgFP(MachineBasicBlock::iterator &I); 164 void handleCompareFP(MachineBasicBlock::iterator &I); 165 void handleCondMovFP(MachineBasicBlock::iterator &I); 166 void handleSpecialFP(MachineBasicBlock::iterator &I); 167 }; 168 char FPS::ID = 0; 169} 170 171FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 172 173/// getFPReg - Return the X86::FPx register number for the specified operand. 174/// For example, this returns 3 for X86::FP3. 175static unsigned getFPReg(const MachineOperand &MO) { 176 assert(MO.isReg() && "Expected an FP register!"); 177 unsigned Reg = MO.getReg(); 178 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 179 return Reg - X86::FP0; 180} 181 182 183/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 184/// register references into FP stack references. 185/// 186bool FPS::runOnMachineFunction(MachineFunction &MF) { 187 // We only need to run this pass if there are any FP registers used in this 188 // function. If it is all integer, there is nothing for us to do! 189 bool FPIsUsed = false; 190 191 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 192 for (unsigned i = 0; i <= 6; ++i) 193 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { 194 FPIsUsed = true; 195 break; 196 } 197 198 // Early exit. 199 if (!FPIsUsed) return false; 200 201 TII = MF.getTarget().getInstrInfo(); 202 StackTop = 0; 203 204 // Process the function in depth first order so that we process at least one 205 // of the predecessors for every reachable block in the function. 206 SmallPtrSet<MachineBasicBlock*, 8> Processed; 207 MachineBasicBlock *Entry = MF.begin(); 208 209 bool Changed = false; 210 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> > 211 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 212 I != E; ++I) 213 Changed |= processBasicBlock(MF, **I); 214 215 // Process any unreachable blocks in arbitrary order now. 216 if (MF.size() == Processed.size()) 217 return Changed; 218 219 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 220 if (Processed.insert(BB)) 221 Changed |= processBasicBlock(MF, *BB); 222 223 return Changed; 224} 225 226/// processBasicBlock - Loop over all of the instructions in the basic block, 227/// transforming FP instructions into their stack form. 228/// 229bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 230 bool Changed = false; 231 MBB = &BB; 232 233 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 234 MachineInstr *MI = I; 235 unsigned Flags = MI->getDesc().TSFlags; 236 237 unsigned FPInstClass = Flags & X86II::FPTypeMask; 238 if (MI->isInlineAsm()) 239 FPInstClass = X86II::SpecialFP; 240 241 if (FPInstClass == X86II::NotFP) 242 continue; // Efficiently ignore non-fp insts! 243 244 MachineInstr *PrevMI = 0; 245 if (I != BB.begin()) 246 PrevMI = prior(I); 247 248 ++NumFP; // Keep track of # of pseudo instrs 249 DEBUG(dbgs() << "\nFPInst:\t" << *MI); 250 251 // Get dead variables list now because the MI pointer may be deleted as part 252 // of processing! 253 SmallVector<unsigned, 8> DeadRegs; 254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 255 const MachineOperand &MO = MI->getOperand(i); 256 if (MO.isReg() && MO.isDead()) 257 DeadRegs.push_back(MO.getReg()); 258 } 259 260 switch (FPInstClass) { 261 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 262 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 263 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 264 case X86II::TwoArgFP: handleTwoArgFP(I); break; 265 case X86II::CompareFP: handleCompareFP(I); break; 266 case X86II::CondMovFP: handleCondMovFP(I); break; 267 case X86II::SpecialFP: handleSpecialFP(I); break; 268 default: llvm_unreachable("Unknown FP Type!"); 269 } 270 271 // Check to see if any of the values defined by this instruction are dead 272 // after definition. If so, pop them. 273 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 274 unsigned Reg = DeadRegs[i]; 275 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 276 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 277 freeStackSlotAfter(I, Reg-X86::FP0); 278 } 279 } 280 281 // Print out all of the instructions expanded to if -debug 282 DEBUG( 283 MachineBasicBlock::iterator PrevI(PrevMI); 284 if (I == PrevI) { 285 dbgs() << "Just deleted pseudo instruction\n"; 286 } else { 287 MachineBasicBlock::iterator Start = I; 288 // Rewind to first instruction newly inserted. 289 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 290 dbgs() << "Inserted instructions:\n\t"; 291 Start->print(dbgs(), &MF.getTarget()); 292 while (++Start != llvm::next(I)) {} 293 } 294 dumpStack(); 295 ); 296 297 Changed = true; 298 } 299 300 assert(isStackEmpty() && "Stack not empty at end of basic block?"); 301 return Changed; 302} 303 304//===----------------------------------------------------------------------===// 305// Efficient Lookup Table Support 306//===----------------------------------------------------------------------===// 307 308namespace { 309 struct TableEntry { 310 unsigned from; 311 unsigned to; 312 bool operator<(const TableEntry &TE) const { return from < TE.from; } 313 friend bool operator<(const TableEntry &TE, unsigned V) { 314 return TE.from < V; 315 } 316 friend bool operator<(unsigned V, const TableEntry &TE) { 317 return V < TE.from; 318 } 319 }; 320} 321 322#ifndef NDEBUG 323static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 324 for (unsigned i = 0; i != NumEntries-1; ++i) 325 if (!(Table[i] < Table[i+1])) return false; 326 return true; 327} 328#endif 329 330static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 331 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 332 if (I != Table+N && I->from == Opcode) 333 return I->to; 334 return -1; 335} 336 337#ifdef NDEBUG 338#define ASSERT_SORTED(TABLE) 339#else 340#define ASSERT_SORTED(TABLE) \ 341 { static bool TABLE##Checked = false; \ 342 if (!TABLE##Checked) { \ 343 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ 344 "All lookup tables must be sorted for efficient access!"); \ 345 TABLE##Checked = true; \ 346 } \ 347 } 348#endif 349 350//===----------------------------------------------------------------------===// 351// Register File -> Register Stack Mapping Methods 352//===----------------------------------------------------------------------===// 353 354// OpcodeTable - Sorted map of register instructions to their stack version. 355// The first element is an register file pseudo instruction, the second is the 356// concrete X86 instruction which uses the register stack. 357// 358static const TableEntry OpcodeTable[] = { 359 { X86::ABS_Fp32 , X86::ABS_F }, 360 { X86::ABS_Fp64 , X86::ABS_F }, 361 { X86::ABS_Fp80 , X86::ABS_F }, 362 { X86::ADD_Fp32m , X86::ADD_F32m }, 363 { X86::ADD_Fp64m , X86::ADD_F64m }, 364 { X86::ADD_Fp64m32 , X86::ADD_F32m }, 365 { X86::ADD_Fp80m32 , X86::ADD_F32m }, 366 { X86::ADD_Fp80m64 , X86::ADD_F64m }, 367 { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 368 { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 369 { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 370 { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 371 { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 372 { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 373 { X86::CHS_Fp32 , X86::CHS_F }, 374 { X86::CHS_Fp64 , X86::CHS_F }, 375 { X86::CHS_Fp80 , X86::CHS_F }, 376 { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 377 { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 378 { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 379 { X86::CMOVB_Fp32 , X86::CMOVB_F }, 380 { X86::CMOVB_Fp64 , X86::CMOVB_F }, 381 { X86::CMOVB_Fp80 , X86::CMOVB_F }, 382 { X86::CMOVE_Fp32 , X86::CMOVE_F }, 383 { X86::CMOVE_Fp64 , X86::CMOVE_F }, 384 { X86::CMOVE_Fp80 , X86::CMOVE_F }, 385 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 386 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 387 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 388 { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 389 { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 390 { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 391 { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 392 { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 393 { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 394 { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 395 { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 396 { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 397 { X86::CMOVP_Fp32 , X86::CMOVP_F }, 398 { X86::CMOVP_Fp64 , X86::CMOVP_F }, 399 { X86::CMOVP_Fp80 , X86::CMOVP_F }, 400 { X86::COS_Fp32 , X86::COS_F }, 401 { X86::COS_Fp64 , X86::COS_F }, 402 { X86::COS_Fp80 , X86::COS_F }, 403 { X86::DIVR_Fp32m , X86::DIVR_F32m }, 404 { X86::DIVR_Fp64m , X86::DIVR_F64m }, 405 { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 406 { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 407 { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 408 { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 409 { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 410 { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 411 { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 412 { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 413 { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 414 { X86::DIV_Fp32m , X86::DIV_F32m }, 415 { X86::DIV_Fp64m , X86::DIV_F64m }, 416 { X86::DIV_Fp64m32 , X86::DIV_F32m }, 417 { X86::DIV_Fp80m32 , X86::DIV_F32m }, 418 { X86::DIV_Fp80m64 , X86::DIV_F64m }, 419 { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 420 { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 421 { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 422 { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 423 { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 424 { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 425 { X86::ILD_Fp16m32 , X86::ILD_F16m }, 426 { X86::ILD_Fp16m64 , X86::ILD_F16m }, 427 { X86::ILD_Fp16m80 , X86::ILD_F16m }, 428 { X86::ILD_Fp32m32 , X86::ILD_F32m }, 429 { X86::ILD_Fp32m64 , X86::ILD_F32m }, 430 { X86::ILD_Fp32m80 , X86::ILD_F32m }, 431 { X86::ILD_Fp64m32 , X86::ILD_F64m }, 432 { X86::ILD_Fp64m64 , X86::ILD_F64m }, 433 { X86::ILD_Fp64m80 , X86::ILD_F64m }, 434 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 435 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 436 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 437 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 438 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 439 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 440 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 441 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 442 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 443 { X86::IST_Fp16m32 , X86::IST_F16m }, 444 { X86::IST_Fp16m64 , X86::IST_F16m }, 445 { X86::IST_Fp16m80 , X86::IST_F16m }, 446 { X86::IST_Fp32m32 , X86::IST_F32m }, 447 { X86::IST_Fp32m64 , X86::IST_F32m }, 448 { X86::IST_Fp32m80 , X86::IST_F32m }, 449 { X86::IST_Fp64m32 , X86::IST_FP64m }, 450 { X86::IST_Fp64m64 , X86::IST_FP64m }, 451 { X86::IST_Fp64m80 , X86::IST_FP64m }, 452 { X86::LD_Fp032 , X86::LD_F0 }, 453 { X86::LD_Fp064 , X86::LD_F0 }, 454 { X86::LD_Fp080 , X86::LD_F0 }, 455 { X86::LD_Fp132 , X86::LD_F1 }, 456 { X86::LD_Fp164 , X86::LD_F1 }, 457 { X86::LD_Fp180 , X86::LD_F1 }, 458 { X86::LD_Fp32m , X86::LD_F32m }, 459 { X86::LD_Fp32m64 , X86::LD_F32m }, 460 { X86::LD_Fp32m80 , X86::LD_F32m }, 461 { X86::LD_Fp64m , X86::LD_F64m }, 462 { X86::LD_Fp64m80 , X86::LD_F64m }, 463 { X86::LD_Fp80m , X86::LD_F80m }, 464 { X86::MUL_Fp32m , X86::MUL_F32m }, 465 { X86::MUL_Fp64m , X86::MUL_F64m }, 466 { X86::MUL_Fp64m32 , X86::MUL_F32m }, 467 { X86::MUL_Fp80m32 , X86::MUL_F32m }, 468 { X86::MUL_Fp80m64 , X86::MUL_F64m }, 469 { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 470 { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 471 { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 472 { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 473 { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 474 { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 475 { X86::SIN_Fp32 , X86::SIN_F }, 476 { X86::SIN_Fp64 , X86::SIN_F }, 477 { X86::SIN_Fp80 , X86::SIN_F }, 478 { X86::SQRT_Fp32 , X86::SQRT_F }, 479 { X86::SQRT_Fp64 , X86::SQRT_F }, 480 { X86::SQRT_Fp80 , X86::SQRT_F }, 481 { X86::ST_Fp32m , X86::ST_F32m }, 482 { X86::ST_Fp64m , X86::ST_F64m }, 483 { X86::ST_Fp64m32 , X86::ST_F32m }, 484 { X86::ST_Fp80m32 , X86::ST_F32m }, 485 { X86::ST_Fp80m64 , X86::ST_F64m }, 486 { X86::ST_FpP80m , X86::ST_FP80m }, 487 { X86::SUBR_Fp32m , X86::SUBR_F32m }, 488 { X86::SUBR_Fp64m , X86::SUBR_F64m }, 489 { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 490 { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 491 { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 492 { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 493 { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 494 { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 495 { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 496 { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 497 { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 498 { X86::SUB_Fp32m , X86::SUB_F32m }, 499 { X86::SUB_Fp64m , X86::SUB_F64m }, 500 { X86::SUB_Fp64m32 , X86::SUB_F32m }, 501 { X86::SUB_Fp80m32 , X86::SUB_F32m }, 502 { X86::SUB_Fp80m64 , X86::SUB_F64m }, 503 { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 504 { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 505 { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 506 { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 507 { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 508 { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 509 { X86::TST_Fp32 , X86::TST_F }, 510 { X86::TST_Fp64 , X86::TST_F }, 511 { X86::TST_Fp80 , X86::TST_F }, 512 { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 513 { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 514 { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 515 { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 516 { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 517 { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 518}; 519 520static unsigned getConcreteOpcode(unsigned Opcode) { 521 ASSERT_SORTED(OpcodeTable); 522 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode); 523 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 524 return Opc; 525} 526 527//===----------------------------------------------------------------------===// 528// Helper Methods 529//===----------------------------------------------------------------------===// 530 531// PopTable - Sorted map of instructions to their popping version. The first 532// element is an instruction, the second is the version which pops. 533// 534static const TableEntry PopTable[] = { 535 { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 536 537 { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 538 { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 539 540 { X86::IST_F16m , X86::IST_FP16m }, 541 { X86::IST_F32m , X86::IST_FP32m }, 542 543 { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 544 545 { X86::ST_F32m , X86::ST_FP32m }, 546 { X86::ST_F64m , X86::ST_FP64m }, 547 { X86::ST_Frr , X86::ST_FPrr }, 548 549 { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 550 { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 551 552 { X86::UCOM_FIr , X86::UCOM_FIPr }, 553 554 { X86::UCOM_FPr , X86::UCOM_FPPr }, 555 { X86::UCOM_Fr , X86::UCOM_FPr }, 556}; 557 558/// popStackAfter - Pop the current value off of the top of the FP stack after 559/// the specified instruction. This attempts to be sneaky and combine the pop 560/// into the instruction itself if possible. The iterator is left pointing to 561/// the last instruction, be it a new pop instruction inserted, or the old 562/// instruction if it was modified in place. 563/// 564void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 565 MachineInstr* MI = I; 566 DebugLoc dl = MI->getDebugLoc(); 567 ASSERT_SORTED(PopTable); 568 assert(StackTop > 0 && "Cannot pop empty stack!"); 569 RegMap[Stack[--StackTop]] = ~0; // Update state 570 571 // Check to see if there is a popping version of this instruction... 572 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); 573 if (Opcode != -1) { 574 I->setDesc(TII->get(Opcode)); 575 if (Opcode == X86::UCOM_FPPr) 576 I->RemoveOperand(0); 577 } else { // Insert an explicit pop 578 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 579 } 580} 581 582/// freeStackSlotAfter - Free the specified register from the register stack, so 583/// that it is no longer in a register. If the register is currently at the top 584/// of the stack, we just pop the current instruction, otherwise we store the 585/// current top-of-stack into the specified slot, then pop the top of stack. 586void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 587 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 588 popStackAfter(I); 589 return; 590 } 591 592 // Otherwise, store the top of stack into the dead slot, killing the operand 593 // without having to add in an explicit xchg then pop. 594 // 595 unsigned STReg = getSTReg(FPRegNo); 596 unsigned OldSlot = getSlot(FPRegNo); 597 unsigned TopReg = Stack[StackTop-1]; 598 Stack[OldSlot] = TopReg; 599 RegMap[TopReg] = OldSlot; 600 RegMap[FPRegNo] = ~0; 601 Stack[--StackTop] = ~0; 602 MachineInstr *MI = I; 603 DebugLoc dl = MI->getDebugLoc(); 604 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg); 605} 606 607 608//===----------------------------------------------------------------------===// 609// Instruction transformation implementation 610//===----------------------------------------------------------------------===// 611 612/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 613/// 614void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 615 MachineInstr *MI = I; 616 unsigned DestReg = getFPReg(MI->getOperand(0)); 617 618 // Change from the pseudo instruction to the concrete instruction. 619 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 620 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 621 622 // Result gets pushed on the stack. 623 pushReg(DestReg); 624} 625 626/// handleOneArgFP - fst <mem>, ST(0) 627/// 628void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 629 MachineInstr *MI = I; 630 unsigned NumOps = MI->getDesc().getNumOperands(); 631 assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) && 632 "Can only handle fst* & ftst instructions!"); 633 634 // Is this the last use of the source register? 635 unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); 636 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 637 638 // FISTP64m is strange because there isn't a non-popping versions. 639 // If we have one _and_ we don't want to pop the operand, duplicate the value 640 // on the stack instead of moving it. This ensure that popping the value is 641 // always ok. 642 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 643 // 644 if (!KillsSrc && 645 (MI->getOpcode() == X86::IST_Fp64m32 || 646 MI->getOpcode() == X86::ISTT_Fp16m32 || 647 MI->getOpcode() == X86::ISTT_Fp32m32 || 648 MI->getOpcode() == X86::ISTT_Fp64m32 || 649 MI->getOpcode() == X86::IST_Fp64m64 || 650 MI->getOpcode() == X86::ISTT_Fp16m64 || 651 MI->getOpcode() == X86::ISTT_Fp32m64 || 652 MI->getOpcode() == X86::ISTT_Fp64m64 || 653 MI->getOpcode() == X86::IST_Fp64m80 || 654 MI->getOpcode() == X86::ISTT_Fp16m80 || 655 MI->getOpcode() == X86::ISTT_Fp32m80 || 656 MI->getOpcode() == X86::ISTT_Fp64m80 || 657 MI->getOpcode() == X86::ST_FpP80m)) { 658 duplicateToTop(Reg, 7 /*temp register*/, I); 659 } else { 660 moveToTop(Reg, I); // Move to the top of the stack... 661 } 662 663 // Convert from the pseudo instruction to the concrete instruction. 664 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand 665 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 666 667 if (MI->getOpcode() == X86::IST_FP64m || 668 MI->getOpcode() == X86::ISTT_FP16m || 669 MI->getOpcode() == X86::ISTT_FP32m || 670 MI->getOpcode() == X86::ISTT_FP64m || 671 MI->getOpcode() == X86::ST_FP80m) { 672 assert(StackTop > 0 && "Stack empty??"); 673 --StackTop; 674 } else if (KillsSrc) { // Last use of operand? 675 popStackAfter(I); 676 } 677} 678 679 680/// handleOneArgFPRW: Handle instructions that read from the top of stack and 681/// replace the value with a newly computed value. These instructions may have 682/// non-fp operands after their FP operands. 683/// 684/// Examples: 685/// R1 = fchs R2 686/// R1 = fadd R2, [mem] 687/// 688void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 689 MachineInstr *MI = I; 690#ifndef NDEBUG 691 unsigned NumOps = MI->getDesc().getNumOperands(); 692 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 693#endif 694 695 // Is this the last use of the source register? 696 unsigned Reg = getFPReg(MI->getOperand(1)); 697 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 698 699 if (KillsSrc) { 700 // If this is the last use of the source register, just make sure it's on 701 // the top of the stack. 702 moveToTop(Reg, I); 703 assert(StackTop > 0 && "Stack cannot be empty!"); 704 --StackTop; 705 pushReg(getFPReg(MI->getOperand(0))); 706 } else { 707 // If this is not the last use of the source register, _copy_ it to the top 708 // of the stack. 709 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 710 } 711 712 // Change from the pseudo instruction to the concrete instruction. 713 MI->RemoveOperand(1); // Drop the source operand. 714 MI->RemoveOperand(0); // Drop the destination operand. 715 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 716} 717 718 719//===----------------------------------------------------------------------===// 720// Define tables of various ways to map pseudo instructions 721// 722 723// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 724static const TableEntry ForwardST0Table[] = { 725 { X86::ADD_Fp32 , X86::ADD_FST0r }, 726 { X86::ADD_Fp64 , X86::ADD_FST0r }, 727 { X86::ADD_Fp80 , X86::ADD_FST0r }, 728 { X86::DIV_Fp32 , X86::DIV_FST0r }, 729 { X86::DIV_Fp64 , X86::DIV_FST0r }, 730 { X86::DIV_Fp80 , X86::DIV_FST0r }, 731 { X86::MUL_Fp32 , X86::MUL_FST0r }, 732 { X86::MUL_Fp64 , X86::MUL_FST0r }, 733 { X86::MUL_Fp80 , X86::MUL_FST0r }, 734 { X86::SUB_Fp32 , X86::SUB_FST0r }, 735 { X86::SUB_Fp64 , X86::SUB_FST0r }, 736 { X86::SUB_Fp80 , X86::SUB_FST0r }, 737}; 738 739// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 740static const TableEntry ReverseST0Table[] = { 741 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 742 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 743 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 744 { X86::DIV_Fp32 , X86::DIVR_FST0r }, 745 { X86::DIV_Fp64 , X86::DIVR_FST0r }, 746 { X86::DIV_Fp80 , X86::DIVR_FST0r }, 747 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 748 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 749 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 750 { X86::SUB_Fp32 , X86::SUBR_FST0r }, 751 { X86::SUB_Fp64 , X86::SUBR_FST0r }, 752 { X86::SUB_Fp80 , X86::SUBR_FST0r }, 753}; 754 755// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 756static const TableEntry ForwardSTiTable[] = { 757 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 758 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 759 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 760 { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 761 { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 762 { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 763 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 764 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 765 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 766 { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 767 { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 768 { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 769}; 770 771// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 772static const TableEntry ReverseSTiTable[] = { 773 { X86::ADD_Fp32 , X86::ADD_FrST0 }, 774 { X86::ADD_Fp64 , X86::ADD_FrST0 }, 775 { X86::ADD_Fp80 , X86::ADD_FrST0 }, 776 { X86::DIV_Fp32 , X86::DIV_FrST0 }, 777 { X86::DIV_Fp64 , X86::DIV_FrST0 }, 778 { X86::DIV_Fp80 , X86::DIV_FrST0 }, 779 { X86::MUL_Fp32 , X86::MUL_FrST0 }, 780 { X86::MUL_Fp64 , X86::MUL_FrST0 }, 781 { X86::MUL_Fp80 , X86::MUL_FrST0 }, 782 { X86::SUB_Fp32 , X86::SUB_FrST0 }, 783 { X86::SUB_Fp64 , X86::SUB_FrST0 }, 784 { X86::SUB_Fp80 , X86::SUB_FrST0 }, 785}; 786 787 788/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 789/// instructions which need to be simplified and possibly transformed. 790/// 791/// Result: ST(0) = fsub ST(0), ST(i) 792/// ST(i) = fsub ST(0), ST(i) 793/// ST(0) = fsubr ST(0), ST(i) 794/// ST(i) = fsubr ST(0), ST(i) 795/// 796void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 797 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 798 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 799 MachineInstr *MI = I; 800 801 unsigned NumOperands = MI->getDesc().getNumOperands(); 802 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 803 unsigned Dest = getFPReg(MI->getOperand(0)); 804 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 805 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 806 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 807 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 808 DebugLoc dl = MI->getDebugLoc(); 809 810 unsigned TOS = getStackEntry(0); 811 812 // One of our operands must be on the top of the stack. If neither is yet, we 813 // need to move one. 814 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 815 // We can choose to move either operand to the top of the stack. If one of 816 // the operands is killed by this instruction, we want that one so that we 817 // can update right on top of the old version. 818 if (KillsOp0) { 819 moveToTop(Op0, I); // Move dead operand to TOS. 820 TOS = Op0; 821 } else if (KillsOp1) { 822 moveToTop(Op1, I); 823 TOS = Op1; 824 } else { 825 // All of the operands are live after this instruction executes, so we 826 // cannot update on top of any operand. Because of this, we must 827 // duplicate one of the stack elements to the top. It doesn't matter 828 // which one we pick. 829 // 830 duplicateToTop(Op0, Dest, I); 831 Op0 = TOS = Dest; 832 KillsOp0 = true; 833 } 834 } else if (!KillsOp0 && !KillsOp1) { 835 // If we DO have one of our operands at the top of the stack, but we don't 836 // have a dead operand, we must duplicate one of the operands to a new slot 837 // on the stack. 838 duplicateToTop(Op0, Dest, I); 839 Op0 = TOS = Dest; 840 KillsOp0 = true; 841 } 842 843 // Now we know that one of our operands is on the top of the stack, and at 844 // least one of our operands is killed by this instruction. 845 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 846 "Stack conditions not set up right!"); 847 848 // We decide which form to use based on what is on the top of the stack, and 849 // which operand is killed by this instruction. 850 const TableEntry *InstTable; 851 bool isForward = TOS == Op0; 852 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 853 if (updateST0) { 854 if (isForward) 855 InstTable = ForwardST0Table; 856 else 857 InstTable = ReverseST0Table; 858 } else { 859 if (isForward) 860 InstTable = ForwardSTiTable; 861 else 862 InstTable = ReverseSTiTable; 863 } 864 865 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table), 866 MI->getOpcode()); 867 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 868 869 // NotTOS - The register which is not on the top of stack... 870 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 871 872 // Replace the old instruction with a new instruction 873 MBB->remove(I++); 874 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 875 876 // If both operands are killed, pop one off of the stack in addition to 877 // overwriting the other one. 878 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 879 assert(!updateST0 && "Should have updated other operand!"); 880 popStackAfter(I); // Pop the top of stack 881 } 882 883 // Update stack information so that we know the destination register is now on 884 // the stack. 885 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 886 assert(UpdatedSlot < StackTop && Dest < 7); 887 Stack[UpdatedSlot] = Dest; 888 RegMap[Dest] = UpdatedSlot; 889 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction 890} 891 892/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 893/// register arguments and no explicit destinations. 894/// 895void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 896 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 897 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 898 MachineInstr *MI = I; 899 900 unsigned NumOperands = MI->getDesc().getNumOperands(); 901 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 902 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 903 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 904 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 905 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 906 907 // Make sure the first operand is on the top of stack, the other one can be 908 // anywhere. 909 moveToTop(Op0, I); 910 911 // Change from the pseudo instruction to the concrete instruction. 912 MI->getOperand(0).setReg(getSTReg(Op1)); 913 MI->RemoveOperand(1); 914 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 915 916 // If any of the operands are killed by this instruction, free them. 917 if (KillsOp0) freeStackSlotAfter(I, Op0); 918 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 919} 920 921/// handleCondMovFP - Handle two address conditional move instructions. These 922/// instructions move a st(i) register to st(0) iff a condition is true. These 923/// instructions require that the first operand is at the top of the stack, but 924/// otherwise don't modify the stack at all. 925void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 926 MachineInstr *MI = I; 927 928 unsigned Op0 = getFPReg(MI->getOperand(0)); 929 unsigned Op1 = getFPReg(MI->getOperand(2)); 930 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 931 932 // The first operand *must* be on the top of the stack. 933 moveToTop(Op0, I); 934 935 // Change the second operand to the stack register that the operand is in. 936 // Change from the pseudo instruction to the concrete instruction. 937 MI->RemoveOperand(0); 938 MI->RemoveOperand(1); 939 MI->getOperand(0).setReg(getSTReg(Op1)); 940 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 941 942 // If we kill the second operand, make sure to pop it from the stack. 943 if (Op0 != Op1 && KillsOp1) { 944 // Get this value off of the register stack. 945 freeStackSlotAfter(I, Op1); 946 } 947} 948 949 950/// handleSpecialFP - Handle special instructions which behave unlike other 951/// floating point instructions. This is primarily intended for use by pseudo 952/// instructions. 953/// 954void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 955 MachineInstr *MI = I; 956 DebugLoc dl = MI->getDebugLoc(); 957 switch (MI->getOpcode()) { 958 default: llvm_unreachable("Unknown SpecialFP instruction!"); 959 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! 960 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! 961 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! 962 assert(StackTop == 0 && "Stack should be empty after a call!"); 963 pushReg(getFPReg(MI->getOperand(0))); 964 break; 965 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type! 966 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type! 967 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type! 968 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm. 969 // The pattern we expect is: 970 // CALL 971 // FP1 = FpGET_ST0 972 // FP4 = FpGET_ST1 973 // 974 // At this point, we've pushed FP1 on the top of stack, so it should be 975 // present if it isn't dead. If it was dead, we already emitted a pop to 976 // remove it from the stack and StackTop = 0. 977 978 // Push FP4 as top of stack next. 979 pushReg(getFPReg(MI->getOperand(0))); 980 981 // If StackTop was 0 before we pushed our operand, then ST(0) must have been 982 // dead. In this case, the ST(1) value is the only thing that is live, so 983 // it should be on the TOS (after the pop that was emitted) and is. Just 984 // continue in this case. 985 if (StackTop == 1) 986 break; 987 988 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top 989 // elements so that our accounting is correct. 990 unsigned RegOnTop = getStackEntry(0); 991 unsigned RegNo = getStackEntry(1); 992 993 // Swap the slots the regs are in. 994 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 995 996 // Swap stack slot contents. 997 assert(RegMap[RegOnTop] < StackTop); 998 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 999 break; 1000 } 1001 case X86::FpSET_ST0_32: 1002 case X86::FpSET_ST0_64: 1003 case X86::FpSET_ST0_80: { 1004 unsigned Op0 = getFPReg(MI->getOperand(0)); 1005 1006 // FpSET_ST0_80 is generated by copyRegToReg for both function return 1007 // and inline assembly with the "st" constrain. In the latter case, 1008 // it is possible for ST(0) to be alive after this instruction. 1009 if (!MI->killsRegister(X86::FP0 + Op0)) { 1010 // Duplicate Op0 1011 duplicateToTop(0, 7 /*temp register*/, I); 1012 } else { 1013 moveToTop(Op0, I); 1014 } 1015 --StackTop; // "Forget" we have something on the top of stack! 1016 break; 1017 } 1018 case X86::FpSET_ST1_32: 1019 case X86::FpSET_ST1_64: 1020 case X86::FpSET_ST1_80: 1021 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. 1022 if (StackTop == 1) { 1023 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); 1024 NumFXCH++; 1025 StackTop = 0; 1026 break; 1027 } 1028 assert(StackTop == 2 && "Stack should have two element on it to return!"); 1029 --StackTop; // "Forget" we have something on the top of stack! 1030 break; 1031 case X86::MOV_Fp3232: 1032 case X86::MOV_Fp3264: 1033 case X86::MOV_Fp6432: 1034 case X86::MOV_Fp6464: 1035 case X86::MOV_Fp3280: 1036 case X86::MOV_Fp6480: 1037 case X86::MOV_Fp8032: 1038 case X86::MOV_Fp8064: 1039 case X86::MOV_Fp8080: { 1040 const MachineOperand &MO1 = MI->getOperand(1); 1041 unsigned SrcReg = getFPReg(MO1); 1042 1043 const MachineOperand &MO0 = MI->getOperand(0); 1044 // These can be created due to inline asm. Two address pass can introduce 1045 // copies from RFP registers to virtual registers. 1046 if (MO0.getReg() == X86::ST0 && SrcReg == 0) { 1047 assert(MO1.isKill()); 1048 // Treat %ST0<def> = MOV_Fp8080 %FP0<kill> 1049 // like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def> 1050 assert((StackTop == 1 || StackTop == 2) 1051 && "Stack should have one or two element on it to return!"); 1052 --StackTop; // "Forget" we have something on the top of stack! 1053 break; 1054 } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) { 1055 assert(MO1.isKill()); 1056 // Treat %ST1<def> = MOV_Fp8080 %FP1<kill> 1057 // like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def> 1058 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. 1059 if (StackTop == 1) { 1060 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); 1061 NumFXCH++; 1062 StackTop = 0; 1063 break; 1064 } 1065 assert(StackTop == 2 && "Stack should have two element on it to return!"); 1066 --StackTop; // "Forget" we have something on the top of stack! 1067 break; 1068 } 1069 1070 unsigned DestReg = getFPReg(MO0); 1071 if (MI->killsRegister(X86::FP0+SrcReg)) { 1072 // If the input operand is killed, we can just change the owner of the 1073 // incoming stack slot into the result. 1074 unsigned Slot = getSlot(SrcReg); 1075 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 1076 Stack[Slot] = DestReg; 1077 RegMap[DestReg] = Slot; 1078 1079 } else { 1080 // For FMOV we just duplicate the specified value to a new stack slot. 1081 // This could be made better, but would require substantial changes. 1082 duplicateToTop(SrcReg, DestReg, I); 1083 } 1084 } 1085 break; 1086 case TargetOpcode::INLINEASM: { 1087 // The inline asm MachineInstr currently only *uses* FP registers for the 1088 // 'f' constraint. These should be turned into the current ST(x) register 1089 // in the machine instr. Also, any kills should be explicitly popped after 1090 // the inline asm. 1091 unsigned Kills = 0; 1092 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1093 MachineOperand &Op = MI->getOperand(i); 1094 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1095 continue; 1096 assert(Op.isUse() && "Only handle inline asm uses right now"); 1097 1098 unsigned FPReg = getFPReg(Op); 1099 Op.setReg(getSTReg(FPReg)); 1100 1101 // If we kill this operand, make sure to pop it from the stack after the 1102 // asm. We just remember it for now, and pop them all off at the end in 1103 // a batch. 1104 if (Op.isKill()) 1105 Kills |= 1U << FPReg; 1106 } 1107 1108 // If this asm kills any FP registers (is the last use of them) we must 1109 // explicitly emit pop instructions for them. Do this now after the asm has 1110 // executed so that the ST(x) numbers are not off (which would happen if we 1111 // did this inline with operand rewriting). 1112 // 1113 // Note: this might be a non-optimal pop sequence. We might be able to do 1114 // better by trying to pop in stack order or something. 1115 MachineBasicBlock::iterator InsertPt = MI; 1116 while (Kills) { 1117 unsigned FPReg = CountTrailingZeros_32(Kills); 1118 freeStackSlotAfter(InsertPt, FPReg); 1119 Kills &= ~(1U << FPReg); 1120 } 1121 // Don't delete the inline asm! 1122 return; 1123 } 1124 1125 case X86::RET: 1126 case X86::RETI: 1127 // If RET has an FP register use operand, pass the first one in ST(0) and 1128 // the second one in ST(1). 1129 if (isStackEmpty()) return; // Quick check to see if any are possible. 1130 1131 // Find the register operands. 1132 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 1133 1134 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1135 MachineOperand &Op = MI->getOperand(i); 1136 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1137 continue; 1138 // FP Register uses must be kills unless there are two uses of the same 1139 // register, in which case only one will be a kill. 1140 assert(Op.isUse() && 1141 (Op.isKill() || // Marked kill. 1142 getFPReg(Op) == FirstFPRegOp || // Second instance. 1143 MI->killsRegister(Op.getReg())) && // Later use is marked kill. 1144 "Ret only defs operands, and values aren't live beyond it"); 1145 1146 if (FirstFPRegOp == ~0U) 1147 FirstFPRegOp = getFPReg(Op); 1148 else { 1149 assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 1150 SecondFPRegOp = getFPReg(Op); 1151 } 1152 1153 // Remove the operand so that later passes don't see it. 1154 MI->RemoveOperand(i); 1155 --i, --e; 1156 } 1157 1158 // There are only four possibilities here: 1159 // 1) we are returning a single FP value. In this case, it has to be in 1160 // ST(0) already, so just declare success by removing the value from the 1161 // FP Stack. 1162 if (SecondFPRegOp == ~0U) { 1163 // Assert that the top of stack contains the right FP register. 1164 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1165 "Top of stack not the right register for RET!"); 1166 1167 // Ok, everything is good, mark the value as not being on the stack 1168 // anymore so that our assertion about the stack being empty at end of 1169 // block doesn't fire. 1170 StackTop = 0; 1171 return; 1172 } 1173 1174 // Otherwise, we are returning two values: 1175 // 2) If returning the same value for both, we only have one thing in the FP 1176 // stack. Consider: RET FP1, FP1 1177 if (StackTop == 1) { 1178 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1179 "Stack misconfiguration for RET!"); 1180 1181 // Duplicate the TOS so that we return it twice. Just pick some other FPx 1182 // register to hold it. 1183 unsigned NewReg = (FirstFPRegOp+1)%7; 1184 duplicateToTop(FirstFPRegOp, NewReg, MI); 1185 FirstFPRegOp = NewReg; 1186 } 1187 1188 /// Okay we know we have two different FPx operands now: 1189 assert(StackTop == 2 && "Must have two values live!"); 1190 1191 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1192 /// in ST(1). In this case, emit an fxch. 1193 if (getStackEntry(0) == SecondFPRegOp) { 1194 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1195 moveToTop(FirstFPRegOp, MI); 1196 } 1197 1198 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1199 /// ST(1). Just remove both from our understanding of the stack and return. 1200 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1201 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1202 StackTop = 0; 1203 return; 1204 } 1205 1206 I = MBB->erase(I); // Remove the pseudo instruction 1207 --I; 1208} 1209