X86FloatingPoint.cpp revision 86556a5f42c549a7a13c82fb65330ab53826fb17
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// virtual registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// This pass is hampered by the lack of decent CFG manipulation routines for 16// machine code. In particular, this wants to be able to split critical edges 17// as necessary, traverse the machine basic block CFG in depth-first order, and 18// allow there to be multiple machine basic blocks for each LLVM basicblock 19// (needed for critical edge splitting). 20// 21// In particular, this pass currently barfs on critical edges. Because of this, 22// it requires the instruction selector to insert FP_REG_KILL instructions on 23// the exits of any basic block that has critical edges going from it, or which 24// branch to a critical basic block. 25// 26// FIXME: this is not implemented yet. The stackifier pass only works on local 27// basic blocks. 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "fp" 32#include "X86.h" 33#include "X86InstrInfo.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/LiveVariables.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Support/Debug.h" 41#include "llvm/ADT/DepthFirstIterator.h" 42#include "llvm/ADT/Statistic.h" 43#include "llvm/ADT/STLExtras.h" 44#include <algorithm> 45#include <set> 46using namespace llvm; 47 48namespace { 49 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); 50 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); 51 52 struct FPS : public MachineFunctionPass { 53 virtual bool runOnMachineFunction(MachineFunction &MF); 54 55 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 56 57 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 58 AU.addRequired<LiveVariables>(); 59 MachineFunctionPass::getAnalysisUsage(AU); 60 } 61 private: 62 LiveVariables *LV; // Live variable info for current function... 63 MachineBasicBlock *MBB; // Current basic block 64 unsigned Stack[8]; // FP<n> Registers in each stack slot... 65 unsigned RegMap[8]; // Track which stack slot contains each register 66 unsigned StackTop; // The current top of the FP stack. 67 68 void dumpStack() const { 69 std::cerr << "Stack contents:"; 70 for (unsigned i = 0; i != StackTop; ++i) { 71 std::cerr << " FP" << Stack[i]; 72 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 73 } 74 std::cerr << "\n"; 75 } 76 private: 77 // getSlot - Return the stack slot number a particular register number is 78 // in... 79 unsigned getSlot(unsigned RegNo) const { 80 assert(RegNo < 8 && "Regno out of range!"); 81 return RegMap[RegNo]; 82 } 83 84 // getStackEntry - Return the X86::FP<n> register in register ST(i) 85 unsigned getStackEntry(unsigned STi) const { 86 assert(STi < StackTop && "Access past stack top!"); 87 return Stack[StackTop-1-STi]; 88 } 89 90 // getSTReg - Return the X86::ST(i) register which contains the specified 91 // FP<RegNo> register 92 unsigned getSTReg(unsigned RegNo) const { 93 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 94 } 95 96 // pushReg - Push the specified FP<n> register onto the stack 97 void pushReg(unsigned Reg) { 98 assert(Reg < 8 && "Register number out of range!"); 99 assert(StackTop < 8 && "Stack overflow!"); 100 Stack[StackTop] = Reg; 101 RegMap[Reg] = StackTop++; 102 } 103 104 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 105 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { 106 if (!isAtTop(RegNo)) { 107 unsigned Slot = getSlot(RegNo); 108 unsigned STReg = getSTReg(RegNo); 109 unsigned RegOnTop = getStackEntry(0); 110 111 // Swap the slots the regs are in 112 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 113 114 // Swap stack slot contents 115 assert(RegMap[RegOnTop] < StackTop); 116 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 117 118 // Emit an fxch to update the runtime processors version of the state 119 BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg); 120 NumFXCH++; 121 } 122 } 123 124 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 125 unsigned STReg = getSTReg(RegNo); 126 pushReg(AsReg); // New register on top of stack 127 128 BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg); 129 } 130 131 // popStackAfter - Pop the current value off of the top of the FP stack 132 // after the specified instruction. 133 void popStackAfter(MachineBasicBlock::iterator &I); 134 135 // freeStackSlotAfter - Free the specified register from the register stack, 136 // so that it is no longer in a register. If the register is currently at 137 // the top of the stack, we just pop the current instruction, otherwise we 138 // store the current top-of-stack into the specified slot, then pop the top 139 // of stack. 140 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 141 142 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 143 144 void handleZeroArgFP(MachineBasicBlock::iterator &I); 145 void handleOneArgFP(MachineBasicBlock::iterator &I); 146 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 147 void handleTwoArgFP(MachineBasicBlock::iterator &I); 148 void handleCompareFP(MachineBasicBlock::iterator &I); 149 void handleCondMovFP(MachineBasicBlock::iterator &I); 150 void handleSpecialFP(MachineBasicBlock::iterator &I); 151 }; 152} 153 154FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 155 156/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 157/// register references into FP stack references. 158/// 159bool FPS::runOnMachineFunction(MachineFunction &MF) { 160 // We only need to run this pass if there are any FP registers used in this 161 // function. If it is all integer, there is nothing for us to do! 162 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 163 bool FPIsUsed = false; 164 165 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 166 for (unsigned i = 0; i <= 6; ++i) 167 if (PhysRegsUsed[X86::FP0+i]) { 168 FPIsUsed = true; 169 break; 170 } 171 172 // Early exit. 173 if (!FPIsUsed) return false; 174 175 LV = &getAnalysis<LiveVariables>(); 176 StackTop = 0; 177 178 // Process the function in depth first order so that we process at least one 179 // of the predecessors for every reachable block in the function. 180 std::set<MachineBasicBlock*> Processed; 181 MachineBasicBlock *Entry = MF.begin(); 182 183 bool Changed = false; 184 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> > 185 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 186 I != E; ++I) 187 Changed |= processBasicBlock(MF, **I); 188 189 return Changed; 190} 191 192/// processBasicBlock - Loop over all of the instructions in the basic block, 193/// transforming FP instructions into their stack form. 194/// 195bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 196 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 197 bool Changed = false; 198 MBB = &BB; 199 200 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 201 MachineInstr *MI = I; 202 unsigned Flags = TII.get(MI->getOpcode()).TSFlags; 203 if ((Flags & X86II::FPTypeMask) == X86II::NotFP) 204 continue; // Efficiently ignore non-fp insts! 205 206 MachineInstr *PrevMI = 0; 207 if (I != BB.begin()) 208 PrevMI = prior(I); 209 210 ++NumFP; // Keep track of # of pseudo instrs 211 DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget()))); 212 213 // Get dead variables list now because the MI pointer may be deleted as part 214 // of processing! 215 LiveVariables::killed_iterator IB, IE; 216 tie(IB, IE) = LV->dead_range(MI); 217 218 DEBUG( 219 const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo(); 220 LiveVariables::killed_iterator I = LV->killed_begin(MI); 221 LiveVariables::killed_iterator E = LV->killed_end(MI); 222 if (I != E) { 223 std::cerr << "Killed Operands:"; 224 for (; I != E; ++I) 225 std::cerr << " %" << MRI->getName(*I); 226 std::cerr << "\n"; 227 } 228 ); 229 230 switch (Flags & X86II::FPTypeMask) { 231 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 232 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 233 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 234 case X86II::TwoArgFP: handleTwoArgFP(I); break; 235 case X86II::CompareFP: handleCompareFP(I); break; 236 case X86II::CondMovFP: handleCondMovFP(I); break; 237 case X86II::SpecialFP: handleSpecialFP(I); break; 238 default: assert(0 && "Unknown FP Type!"); 239 } 240 241 // Check to see if any of the values defined by this instruction are dead 242 // after definition. If so, pop them. 243 for (; IB != IE; ++IB) { 244 unsigned Reg = *IB; 245 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 246 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 247 freeStackSlotAfter(I, Reg-X86::FP0); 248 } 249 } 250 251 // Print out all of the instructions expanded to if -debug 252 DEBUG( 253 MachineBasicBlock::iterator PrevI(PrevMI); 254 if (I == PrevI) { 255 std::cerr << "Just deleted pseudo instruction\n"; 256 } else { 257 MachineBasicBlock::iterator Start = I; 258 // Rewind to first instruction newly inserted. 259 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 260 std::cerr << "Inserted instructions:\n\t"; 261 Start->print(std::cerr, &MF.getTarget()); 262 while (++Start != next(I)); 263 } 264 dumpStack(); 265 ); 266 267 Changed = true; 268 } 269 270 assert(StackTop == 0 && "Stack not empty at end of basic block?"); 271 return Changed; 272} 273 274//===----------------------------------------------------------------------===// 275// Efficient Lookup Table Support 276//===----------------------------------------------------------------------===// 277 278namespace { 279 struct TableEntry { 280 unsigned from; 281 unsigned to; 282 bool operator<(const TableEntry &TE) const { return from < TE.from; } 283 bool operator<(unsigned V) const { return from < V; } 284 }; 285} 286 287static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 288 for (unsigned i = 0; i != NumEntries-1; ++i) 289 if (!(Table[i] < Table[i+1])) return false; 290 return true; 291} 292 293static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 294 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 295 if (I != Table+N && I->from == Opcode) 296 return I->to; 297 return -1; 298} 299 300#define ARRAY_SIZE(TABLE) \ 301 (sizeof(TABLE)/sizeof(TABLE[0])) 302 303#ifdef NDEBUG 304#define ASSERT_SORTED(TABLE) 305#else 306#define ASSERT_SORTED(TABLE) \ 307 { static bool TABLE##Checked = false; \ 308 if (!TABLE##Checked) \ 309 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ 310 "All lookup tables must be sorted for efficient access!"); \ 311 } 312#endif 313 314//===----------------------------------------------------------------------===// 315// Register File -> Register Stack Mapping Methods 316//===----------------------------------------------------------------------===// 317 318// OpcodeTable - Sorted map of register instructions to their stack version. 319// The first element is an register file pseudo instruction, the second is the 320// concrete X86 instruction which uses the register stack. 321// 322static const TableEntry OpcodeTable[] = { 323 { X86::FpABS , X86::FABS }, 324 { X86::FpADD32m , X86::FADD32m }, 325 { X86::FpADD64m , X86::FADD64m }, 326 { X86::FpCHS , X86::FCHS }, 327 { X86::FpCMOVB , X86::FCMOVB }, 328 { X86::FpCMOVBE , X86::FCMOVBE }, 329 { X86::FpCMOVE , X86::FCMOVE }, 330 { X86::FpCMOVNB , X86::FCMOVNB }, 331 { X86::FpCMOVNBE , X86::FCMOVNBE }, 332 { X86::FpCMOVNE , X86::FCMOVNE }, 333 { X86::FpCMOVNP , X86::FCMOVNP }, 334 { X86::FpCMOVP , X86::FCMOVP }, 335 { X86::FpCOS , X86::FCOS }, 336 { X86::FpDIV32m , X86::FDIV32m }, 337 { X86::FpDIV64m , X86::FDIV64m }, 338 { X86::FpDIVR32m , X86::FDIVR32m }, 339 { X86::FpDIVR64m , X86::FDIVR64m }, 340 { X86::FpIADD16m , X86::FIADD16m }, 341 { X86::FpIADD32m , X86::FIADD32m }, 342 { X86::FpIDIV16m , X86::FIDIV16m }, 343 { X86::FpIDIV32m , X86::FIDIV32m }, 344 { X86::FpIDIVR16m, X86::FIDIVR16m}, 345 { X86::FpIDIVR32m, X86::FIDIVR32m}, 346 { X86::FpILD16m , X86::FILD16m }, 347 { X86::FpILD32m , X86::FILD32m }, 348 { X86::FpILD64m , X86::FILD64m }, 349 { X86::FpIMUL16m , X86::FIMUL16m }, 350 { X86::FpIMUL32m , X86::FIMUL32m }, 351 { X86::FpIST16m , X86::FIST16m }, 352 { X86::FpIST32m , X86::FIST32m }, 353 { X86::FpIST64m , X86::FISTP64m }, 354 { X86::FpISUB16m , X86::FISUB16m }, 355 { X86::FpISUB32m , X86::FISUB32m }, 356 { X86::FpISUBR16m, X86::FISUBR16m}, 357 { X86::FpISUBR32m, X86::FISUBR32m}, 358 { X86::FpLD0 , X86::FLD0 }, 359 { X86::FpLD1 , X86::FLD1 }, 360 { X86::FpLD32m , X86::FLD32m }, 361 { X86::FpLD64m , X86::FLD64m }, 362 { X86::FpMUL32m , X86::FMUL32m }, 363 { X86::FpMUL64m , X86::FMUL64m }, 364 { X86::FpSIN , X86::FSIN }, 365 { X86::FpSQRT , X86::FSQRT }, 366 { X86::FpST32m , X86::FST32m }, 367 { X86::FpST64m , X86::FST64m }, 368 { X86::FpSUB32m , X86::FSUB32m }, 369 { X86::FpSUB64m , X86::FSUB64m }, 370 { X86::FpSUBR32m , X86::FSUBR32m }, 371 { X86::FpSUBR64m , X86::FSUBR64m }, 372 { X86::FpTST , X86::FTST }, 373 { X86::FpUCOMIr , X86::FUCOMIr }, 374 { X86::FpUCOMr , X86::FUCOMr }, 375}; 376 377static unsigned getConcreteOpcode(unsigned Opcode) { 378 ASSERT_SORTED(OpcodeTable); 379 int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode); 380 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 381 return Opc; 382} 383 384//===----------------------------------------------------------------------===// 385// Helper Methods 386//===----------------------------------------------------------------------===// 387 388// PopTable - Sorted map of instructions to their popping version. The first 389// element is an instruction, the second is the version which pops. 390// 391static const TableEntry PopTable[] = { 392 { X86::FADDrST0 , X86::FADDPrST0 }, 393 394 { X86::FDIVRrST0, X86::FDIVRPrST0 }, 395 { X86::FDIVrST0 , X86::FDIVPrST0 }, 396 397 { X86::FIST16m , X86::FISTP16m }, 398 { X86::FIST32m , X86::FISTP32m }, 399 400 { X86::FMULrST0 , X86::FMULPrST0 }, 401 402 { X86::FST32m , X86::FSTP32m }, 403 { X86::FST64m , X86::FSTP64m }, 404 { X86::FSTrr , X86::FSTPrr }, 405 406 { X86::FSUBRrST0, X86::FSUBRPrST0 }, 407 { X86::FSUBrST0 , X86::FSUBPrST0 }, 408 409 { X86::FUCOMIr , X86::FUCOMIPr }, 410 411 { X86::FUCOMPr , X86::FUCOMPPr }, 412 { X86::FUCOMr , X86::FUCOMPr }, 413}; 414 415/// popStackAfter - Pop the current value off of the top of the FP stack after 416/// the specified instruction. This attempts to be sneaky and combine the pop 417/// into the instruction itself if possible. The iterator is left pointing to 418/// the last instruction, be it a new pop instruction inserted, or the old 419/// instruction if it was modified in place. 420/// 421void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 422 ASSERT_SORTED(PopTable); 423 assert(StackTop > 0 && "Cannot pop empty stack!"); 424 RegMap[Stack[--StackTop]] = ~0; // Update state 425 426 // Check to see if there is a popping version of this instruction... 427 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); 428 if (Opcode != -1) { 429 I->setOpcode(Opcode); 430 if (Opcode == X86::FUCOMPPr) 431 I->RemoveOperand(0); 432 433 } else { // Insert an explicit pop 434 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0); 435 } 436} 437 438/// freeStackSlotAfter - Free the specified register from the register stack, so 439/// that it is no longer in a register. If the register is currently at the top 440/// of the stack, we just pop the current instruction, otherwise we store the 441/// current top-of-stack into the specified slot, then pop the top of stack. 442void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 443 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 444 popStackAfter(I); 445 return; 446 } 447 448 // Otherwise, store the top of stack into the dead slot, killing the operand 449 // without having to add in an explicit xchg then pop. 450 // 451 unsigned STReg = getSTReg(FPRegNo); 452 unsigned OldSlot = getSlot(FPRegNo); 453 unsigned TopReg = Stack[StackTop-1]; 454 Stack[OldSlot] = TopReg; 455 RegMap[TopReg] = OldSlot; 456 RegMap[FPRegNo] = ~0; 457 Stack[--StackTop] = ~0; 458 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg); 459} 460 461 462static unsigned getFPReg(const MachineOperand &MO) { 463 assert(MO.isRegister() && "Expected an FP register!"); 464 unsigned Reg = MO.getReg(); 465 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 466 return Reg - X86::FP0; 467} 468 469 470//===----------------------------------------------------------------------===// 471// Instruction transformation implementation 472//===----------------------------------------------------------------------===// 473 474/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 475/// 476void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 477 MachineInstr *MI = I; 478 unsigned DestReg = getFPReg(MI->getOperand(0)); 479 480 // Change from the pseudo instruction to the concrete instruction. 481 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 482 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 483 484 // Result gets pushed on the stack. 485 pushReg(DestReg); 486} 487 488/// handleOneArgFP - fst <mem>, ST(0) 489/// 490void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 491 MachineInstr *MI = I; 492 assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) && 493 "Can only handle fst* & ftst instructions!"); 494 495 // Is this the last use of the source register? 496 unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1)); 497 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 498 499 // FISTP64r is strange because there isn't a non-popping versions. 500 // If we have one _and_ we don't want to pop the operand, duplicate the value 501 // on the stack instead of moving it. This ensure that popping the value is 502 // always ok. 503 // 504 if (MI->getOpcode() == X86::FpIST64m && !KillsSrc) { 505 duplicateToTop(Reg, 7 /*temp register*/, I); 506 } else { 507 moveToTop(Reg, I); // Move to the top of the stack... 508 } 509 510 // Convert from the pseudo instruction to the concrete instruction. 511 MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand 512 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 513 514 if (MI->getOpcode() == X86::FISTP64m) { 515 assert(StackTop > 0 && "Stack empty??"); 516 --StackTop; 517 } else if (KillsSrc) { // Last use of operand? 518 popStackAfter(I); 519 } 520} 521 522 523/// handleOneArgFPRW: Handle instructions that read from the top of stack and 524/// replace the value with a newly computed value. These instructions may have 525/// non-fp operands after their FP operands. 526/// 527/// Examples: 528/// R1 = fchs R2 529/// R1 = fadd R2, [mem] 530/// 531void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 532 MachineInstr *MI = I; 533 assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!"); 534 535 // Is this the last use of the source register? 536 unsigned Reg = getFPReg(MI->getOperand(1)); 537 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 538 539 if (KillsSrc) { 540 // If this is the last use of the source register, just make sure it's on 541 // the top of the stack. 542 moveToTop(Reg, I); 543 assert(StackTop > 0 && "Stack cannot be empty!"); 544 --StackTop; 545 pushReg(getFPReg(MI->getOperand(0))); 546 } else { 547 // If this is not the last use of the source register, _copy_ it to the top 548 // of the stack. 549 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 550 } 551 552 // Change from the pseudo instruction to the concrete instruction. 553 MI->RemoveOperand(1); // Drop the source operand. 554 MI->RemoveOperand(0); // Drop the destination operand. 555 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 556} 557 558 559//===----------------------------------------------------------------------===// 560// Define tables of various ways to map pseudo instructions 561// 562 563// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 564static const TableEntry ForwardST0Table[] = { 565 { X86::FpADD , X86::FADDST0r }, 566 { X86::FpDIV , X86::FDIVST0r }, 567 { X86::FpMUL , X86::FMULST0r }, 568 { X86::FpSUB , X86::FSUBST0r }, 569}; 570 571// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 572static const TableEntry ReverseST0Table[] = { 573 { X86::FpADD , X86::FADDST0r }, // commutative 574 { X86::FpDIV , X86::FDIVRST0r }, 575 { X86::FpMUL , X86::FMULST0r }, // commutative 576 { X86::FpSUB , X86::FSUBRST0r }, 577}; 578 579// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 580static const TableEntry ForwardSTiTable[] = { 581 { X86::FpADD , X86::FADDrST0 }, // commutative 582 { X86::FpDIV , X86::FDIVRrST0 }, 583 { X86::FpMUL , X86::FMULrST0 }, // commutative 584 { X86::FpSUB , X86::FSUBRrST0 }, 585}; 586 587// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 588static const TableEntry ReverseSTiTable[] = { 589 { X86::FpADD , X86::FADDrST0 }, 590 { X86::FpDIV , X86::FDIVrST0 }, 591 { X86::FpMUL , X86::FMULrST0 }, 592 { X86::FpSUB , X86::FSUBrST0 }, 593}; 594 595 596/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 597/// instructions which need to be simplified and possibly transformed. 598/// 599/// Result: ST(0) = fsub ST(0), ST(i) 600/// ST(i) = fsub ST(0), ST(i) 601/// ST(0) = fsubr ST(0), ST(i) 602/// ST(i) = fsubr ST(0), ST(i) 603/// 604void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 605 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 606 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 607 MachineInstr *MI = I; 608 609 unsigned NumOperands = MI->getNumOperands(); 610 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 611 unsigned Dest = getFPReg(MI->getOperand(0)); 612 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 613 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 614 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 615 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 616 617 unsigned TOS = getStackEntry(0); 618 619 // One of our operands must be on the top of the stack. If neither is yet, we 620 // need to move one. 621 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 622 // We can choose to move either operand to the top of the stack. If one of 623 // the operands is killed by this instruction, we want that one so that we 624 // can update right on top of the old version. 625 if (KillsOp0) { 626 moveToTop(Op0, I); // Move dead operand to TOS. 627 TOS = Op0; 628 } else if (KillsOp1) { 629 moveToTop(Op1, I); 630 TOS = Op1; 631 } else { 632 // All of the operands are live after this instruction executes, so we 633 // cannot update on top of any operand. Because of this, we must 634 // duplicate one of the stack elements to the top. It doesn't matter 635 // which one we pick. 636 // 637 duplicateToTop(Op0, Dest, I); 638 Op0 = TOS = Dest; 639 KillsOp0 = true; 640 } 641 } else if (!KillsOp0 && !KillsOp1) { 642 // If we DO have one of our operands at the top of the stack, but we don't 643 // have a dead operand, we must duplicate one of the operands to a new slot 644 // on the stack. 645 duplicateToTop(Op0, Dest, I); 646 Op0 = TOS = Dest; 647 KillsOp0 = true; 648 } 649 650 // Now we know that one of our operands is on the top of the stack, and at 651 // least one of our operands is killed by this instruction. 652 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 653 "Stack conditions not set up right!"); 654 655 // We decide which form to use based on what is on the top of the stack, and 656 // which operand is killed by this instruction. 657 const TableEntry *InstTable; 658 bool isForward = TOS == Op0; 659 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 660 if (updateST0) { 661 if (isForward) 662 InstTable = ForwardST0Table; 663 else 664 InstTable = ReverseST0Table; 665 } else { 666 if (isForward) 667 InstTable = ForwardSTiTable; 668 else 669 InstTable = ReverseSTiTable; 670 } 671 672 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode()); 673 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 674 675 // NotTOS - The register which is not on the top of stack... 676 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 677 678 // Replace the old instruction with a new instruction 679 MBB->remove(I++); 680 I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS)); 681 682 // If both operands are killed, pop one off of the stack in addition to 683 // overwriting the other one. 684 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 685 assert(!updateST0 && "Should have updated other operand!"); 686 popStackAfter(I); // Pop the top of stack 687 } 688 689 // Update stack information so that we know the destination register is now on 690 // the stack. 691 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 692 assert(UpdatedSlot < StackTop && Dest < 7); 693 Stack[UpdatedSlot] = Dest; 694 RegMap[Dest] = UpdatedSlot; 695 delete MI; // Remove the old instruction 696} 697 698/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 699/// register arguments and no explicit destinations. 700/// 701void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 702 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 703 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 704 MachineInstr *MI = I; 705 706 unsigned NumOperands = MI->getNumOperands(); 707 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 708 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 709 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 710 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 711 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 712 713 // Make sure the first operand is on the top of stack, the other one can be 714 // anywhere. 715 moveToTop(Op0, I); 716 717 // Change from the pseudo instruction to the concrete instruction. 718 MI->getOperand(0).setReg(getSTReg(Op1)); 719 MI->RemoveOperand(1); 720 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 721 722 // If any of the operands are killed by this instruction, free them. 723 if (KillsOp0) freeStackSlotAfter(I, Op0); 724 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 725} 726 727/// handleCondMovFP - Handle two address conditional move instructions. These 728/// instructions move a st(i) register to st(0) iff a condition is true. These 729/// instructions require that the first operand is at the top of the stack, but 730/// otherwise don't modify the stack at all. 731void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 732 MachineInstr *MI = I; 733 734 unsigned Op0 = getFPReg(MI->getOperand(0)); 735 unsigned Op1 = getFPReg(MI->getOperand(1)); 736 737 // The first operand *must* be on the top of the stack. 738 moveToTop(Op0, I); 739 740 // Change the second operand to the stack register that the operand is in. 741 // Change from the pseudo instruction to the concrete instruction. 742 MI->RemoveOperand(0); 743 MI->getOperand(0).setReg(getSTReg(Op1)); 744 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 745 746 747 // If we kill the second operand, make sure to pop it from the stack. 748 if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) { 749 // Get this value off of the register stack. 750 freeStackSlotAfter(I, Op1); 751 } 752} 753 754 755/// handleSpecialFP - Handle special instructions which behave unlike other 756/// floating point instructions. This is primarily intended for use by pseudo 757/// instructions. 758/// 759void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 760 MachineInstr *MI = I; 761 switch (MI->getOpcode()) { 762 default: assert(0 && "Unknown SpecialFP instruction!"); 763 case X86::FpGETRESULT: // Appears immediately after a call returning FP type! 764 assert(StackTop == 0 && "Stack should be empty after a call!"); 765 pushReg(getFPReg(MI->getOperand(0))); 766 break; 767 case X86::FpSETRESULT: 768 assert(StackTop == 1 && "Stack should have one element on it to return!"); 769 --StackTop; // "Forget" we have something on the top of stack! 770 break; 771 case X86::FpMOV: { 772 unsigned SrcReg = getFPReg(MI->getOperand(1)); 773 unsigned DestReg = getFPReg(MI->getOperand(0)); 774 775 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) { 776 // If the input operand is killed, we can just change the owner of the 777 // incoming stack slot into the result. 778 unsigned Slot = getSlot(SrcReg); 779 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 780 Stack[Slot] = DestReg; 781 RegMap[DestReg] = Slot; 782 783 } else { 784 // For FMOV we just duplicate the specified value to a new stack slot. 785 // This could be made better, but would require substantial changes. 786 duplicateToTop(SrcReg, DestReg, I); 787 } 788 break; 789 } 790 } 791 792 I = MBB->erase(I); // Remove the pseudo instruction 793 --I; 794} 795