X86FloatingPoint.cpp revision ac0b6ae358944ae8b2b5a11dc08f52c3ed89f2da
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// virtual registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// This pass is hampered by the lack of decent CFG manipulation routines for 16// machine code. In particular, this wants to be able to split critical edges 17// as necessary, traverse the machine basic block CFG in depth-first order, and 18// allow there to be multiple machine basic blocks for each LLVM basicblock 19// (needed for critical edge splitting). 20// 21// In particular, this pass currently barfs on critical edges. Because of this, 22// it requires the instruction selector to insert FP_REG_KILL instructions on 23// the exits of any basic block that has critical edges going from it, or which 24// branch to a critical basic block. 25// 26// FIXME: this is not implemented yet. The stackifier pass only works on local 27// basic blocks. 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "fp" 32#include "X86.h" 33#include "X86InstrInfo.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/LiveVariables.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Support/Debug.h" 41#include "llvm/Support/Compiler.h" 42#include "llvm/ADT/DepthFirstIterator.h" 43#include "llvm/ADT/SmallVector.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/STLExtras.h" 46#include <algorithm> 47#include <iostream> 48#include <set> 49using namespace llvm; 50 51namespace { 52 Statistic NumFXCH("x86-codegen", "Number of fxch instructions inserted"); 53 Statistic NumFP ("x86-codegen", "Number of floating point instructions"); 54 55 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass { 56 virtual bool runOnMachineFunction(MachineFunction &MF); 57 58 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 59 60 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<LiveVariables>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 private: 65 const TargetInstrInfo *TII; // Machine instruction info. 66 LiveVariables *LV; // Live variable info for current function... 67 MachineBasicBlock *MBB; // Current basic block 68 unsigned Stack[8]; // FP<n> Registers in each stack slot... 69 unsigned RegMap[8]; // Track which stack slot contains each register 70 unsigned StackTop; // The current top of the FP stack. 71 72 void dumpStack() const { 73 std::cerr << "Stack contents:"; 74 for (unsigned i = 0; i != StackTop; ++i) { 75 std::cerr << " FP" << Stack[i]; 76 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 77 } 78 std::cerr << "\n"; 79 } 80 private: 81 // getSlot - Return the stack slot number a particular register number is 82 // in... 83 unsigned getSlot(unsigned RegNo) const { 84 assert(RegNo < 8 && "Regno out of range!"); 85 return RegMap[RegNo]; 86 } 87 88 // getStackEntry - Return the X86::FP<n> register in register ST(i) 89 unsigned getStackEntry(unsigned STi) const { 90 assert(STi < StackTop && "Access past stack top!"); 91 return Stack[StackTop-1-STi]; 92 } 93 94 // getSTReg - Return the X86::ST(i) register which contains the specified 95 // FP<RegNo> register 96 unsigned getSTReg(unsigned RegNo) const { 97 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 98 } 99 100 // pushReg - Push the specified FP<n> register onto the stack 101 void pushReg(unsigned Reg) { 102 assert(Reg < 8 && "Register number out of range!"); 103 assert(StackTop < 8 && "Stack overflow!"); 104 Stack[StackTop] = Reg; 105 RegMap[Reg] = StackTop++; 106 } 107 108 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 109 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { 110 if (!isAtTop(RegNo)) { 111 unsigned STReg = getSTReg(RegNo); 112 unsigned RegOnTop = getStackEntry(0); 113 114 // Swap the slots the regs are in 115 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 116 117 // Swap stack slot contents 118 assert(RegMap[RegOnTop] < StackTop); 119 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 120 121 // Emit an fxch to update the runtime processors version of the state 122 BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg); 123 NumFXCH++; 124 } 125 } 126 127 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 128 unsigned STReg = getSTReg(RegNo); 129 pushReg(AsReg); // New register on top of stack 130 131 BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg); 132 } 133 134 // popStackAfter - Pop the current value off of the top of the FP stack 135 // after the specified instruction. 136 void popStackAfter(MachineBasicBlock::iterator &I); 137 138 // freeStackSlotAfter - Free the specified register from the register stack, 139 // so that it is no longer in a register. If the register is currently at 140 // the top of the stack, we just pop the current instruction, otherwise we 141 // store the current top-of-stack into the specified slot, then pop the top 142 // of stack. 143 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 144 145 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 146 147 void handleZeroArgFP(MachineBasicBlock::iterator &I); 148 void handleOneArgFP(MachineBasicBlock::iterator &I); 149 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 150 void handleTwoArgFP(MachineBasicBlock::iterator &I); 151 void handleCompareFP(MachineBasicBlock::iterator &I); 152 void handleCondMovFP(MachineBasicBlock::iterator &I); 153 void handleSpecialFP(MachineBasicBlock::iterator &I); 154 }; 155} 156 157FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 158 159/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 160/// register references into FP stack references. 161/// 162bool FPS::runOnMachineFunction(MachineFunction &MF) { 163 // We only need to run this pass if there are any FP registers used in this 164 // function. If it is all integer, there is nothing for us to do! 165 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 166 bool FPIsUsed = false; 167 168 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 169 for (unsigned i = 0; i <= 6; ++i) 170 if (PhysRegsUsed[X86::FP0+i]) { 171 FPIsUsed = true; 172 break; 173 } 174 175 // Early exit. 176 if (!FPIsUsed) return false; 177 178 TII = MF.getTarget().getInstrInfo(); 179 LV = &getAnalysis<LiveVariables>(); 180 StackTop = 0; 181 182 // Process the function in depth first order so that we process at least one 183 // of the predecessors for every reachable block in the function. 184 std::set<MachineBasicBlock*> Processed; 185 MachineBasicBlock *Entry = MF.begin(); 186 187 bool Changed = false; 188 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> > 189 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 190 I != E; ++I) 191 Changed |= processBasicBlock(MF, **I); 192 193 return Changed; 194} 195 196/// processBasicBlock - Loop over all of the instructions in the basic block, 197/// transforming FP instructions into their stack form. 198/// 199bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 200 bool Changed = false; 201 MBB = &BB; 202 203 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 204 MachineInstr *MI = I; 205 unsigned Flags = MI->getInstrDescriptor()->TSFlags; 206 if ((Flags & X86II::FPTypeMask) == X86II::NotFP) 207 continue; // Efficiently ignore non-fp insts! 208 209 MachineInstr *PrevMI = 0; 210 if (I != BB.begin()) 211 PrevMI = prior(I); 212 213 ++NumFP; // Keep track of # of pseudo instrs 214 DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget()))); 215 216 // Get dead variables list now because the MI pointer may be deleted as part 217 // of processing! 218 SmallVector<unsigned, 8> DeadRegs; 219 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 220 const MachineOperand &MO = MI->getOperand(i); 221 if (MO.isReg() && MO.isDead()) 222 DeadRegs.push_back(MO.getReg()); 223 } 224 225 switch (Flags & X86II::FPTypeMask) { 226 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 227 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 228 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 229 case X86II::TwoArgFP: handleTwoArgFP(I); break; 230 case X86II::CompareFP: handleCompareFP(I); break; 231 case X86II::CondMovFP: handleCondMovFP(I); break; 232 case X86II::SpecialFP: handleSpecialFP(I); break; 233 default: assert(0 && "Unknown FP Type!"); 234 } 235 236 // Check to see if any of the values defined by this instruction are dead 237 // after definition. If so, pop them. 238 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 239 unsigned Reg = DeadRegs[i]; 240 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 241 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 242 freeStackSlotAfter(I, Reg-X86::FP0); 243 } 244 } 245 246 // Print out all of the instructions expanded to if -debug 247 DEBUG( 248 MachineBasicBlock::iterator PrevI(PrevMI); 249 if (I == PrevI) { 250 std::cerr << "Just deleted pseudo instruction\n"; 251 } else { 252 MachineBasicBlock::iterator Start = I; 253 // Rewind to first instruction newly inserted. 254 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 255 std::cerr << "Inserted instructions:\n\t"; 256 Start->print(std::cerr, &MF.getTarget()); 257 while (++Start != next(I)); 258 } 259 dumpStack(); 260 ); 261 262 Changed = true; 263 } 264 265 assert(StackTop == 0 && "Stack not empty at end of basic block?"); 266 return Changed; 267} 268 269//===----------------------------------------------------------------------===// 270// Efficient Lookup Table Support 271//===----------------------------------------------------------------------===// 272 273namespace { 274 struct TableEntry { 275 unsigned from; 276 unsigned to; 277 bool operator<(const TableEntry &TE) const { return from < TE.from; } 278 friend bool operator<(const TableEntry &TE, unsigned V) { 279 return TE.from < V; 280 } 281 friend bool operator<(unsigned V, const TableEntry &TE) { 282 return V < TE.from; 283 } 284 }; 285} 286 287static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 288 for (unsigned i = 0; i != NumEntries-1; ++i) 289 if (!(Table[i] < Table[i+1])) return false; 290 return true; 291} 292 293static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 294 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 295 if (I != Table+N && I->from == Opcode) 296 return I->to; 297 return -1; 298} 299 300#define ARRAY_SIZE(TABLE) \ 301 (sizeof(TABLE)/sizeof(TABLE[0])) 302 303#ifdef NDEBUG 304#define ASSERT_SORTED(TABLE) 305#else 306#define ASSERT_SORTED(TABLE) \ 307 { static bool TABLE##Checked = false; \ 308 if (!TABLE##Checked) { \ 309 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ 310 "All lookup tables must be sorted for efficient access!"); \ 311 TABLE##Checked = true; \ 312 } \ 313 } 314#endif 315 316//===----------------------------------------------------------------------===// 317// Register File -> Register Stack Mapping Methods 318//===----------------------------------------------------------------------===// 319 320// OpcodeTable - Sorted map of register instructions to their stack version. 321// The first element is an register file pseudo instruction, the second is the 322// concrete X86 instruction which uses the register stack. 323// 324static const TableEntry OpcodeTable[] = { 325 { X86::FpABS , X86::FABS }, 326 { X86::FpADD32m , X86::FADD32m }, 327 { X86::FpADD64m , X86::FADD64m }, 328 { X86::FpCHS , X86::FCHS }, 329 { X86::FpCMOVB , X86::FCMOVB }, 330 { X86::FpCMOVBE , X86::FCMOVBE }, 331 { X86::FpCMOVE , X86::FCMOVE }, 332 { X86::FpCMOVNB , X86::FCMOVNB }, 333 { X86::FpCMOVNBE , X86::FCMOVNBE }, 334 { X86::FpCMOVNE , X86::FCMOVNE }, 335 { X86::FpCMOVNP , X86::FCMOVNP }, 336 { X86::FpCMOVP , X86::FCMOVP }, 337 { X86::FpCOS , X86::FCOS }, 338 { X86::FpDIV32m , X86::FDIV32m }, 339 { X86::FpDIV64m , X86::FDIV64m }, 340 { X86::FpDIVR32m , X86::FDIVR32m }, 341 { X86::FpDIVR64m , X86::FDIVR64m }, 342 { X86::FpIADD16m , X86::FIADD16m }, 343 { X86::FpIADD32m , X86::FIADD32m }, 344 { X86::FpIDIV16m , X86::FIDIV16m }, 345 { X86::FpIDIV32m , X86::FIDIV32m }, 346 { X86::FpIDIVR16m, X86::FIDIVR16m}, 347 { X86::FpIDIVR32m, X86::FIDIVR32m}, 348 { X86::FpILD16m , X86::FILD16m }, 349 { X86::FpILD32m , X86::FILD32m }, 350 { X86::FpILD64m , X86::FILD64m }, 351 { X86::FpIMUL16m , X86::FIMUL16m }, 352 { X86::FpIMUL32m , X86::FIMUL32m }, 353 { X86::FpIST16m , X86::FIST16m }, 354 { X86::FpIST32m , X86::FIST32m }, 355 { X86::FpIST64m , X86::FISTP64m }, 356 { X86::FpISTT16m , X86::FISTTP16m}, 357 { X86::FpISTT32m , X86::FISTTP32m}, 358 { X86::FpISTT64m , X86::FISTTP64m}, 359 { X86::FpISUB16m , X86::FISUB16m }, 360 { X86::FpISUB32m , X86::FISUB32m }, 361 { X86::FpISUBR16m, X86::FISUBR16m}, 362 { X86::FpISUBR32m, X86::FISUBR32m}, 363 { X86::FpLD0 , X86::FLD0 }, 364 { X86::FpLD1 , X86::FLD1 }, 365 { X86::FpLD32m , X86::FLD32m }, 366 { X86::FpLD64m , X86::FLD64m }, 367 { X86::FpMUL32m , X86::FMUL32m }, 368 { X86::FpMUL64m , X86::FMUL64m }, 369 { X86::FpSIN , X86::FSIN }, 370 { X86::FpSQRT , X86::FSQRT }, 371 { X86::FpST32m , X86::FST32m }, 372 { X86::FpST64m , X86::FST64m }, 373 { X86::FpSUB32m , X86::FSUB32m }, 374 { X86::FpSUB64m , X86::FSUB64m }, 375 { X86::FpSUBR32m , X86::FSUBR32m }, 376 { X86::FpSUBR64m , X86::FSUBR64m }, 377 { X86::FpTST , X86::FTST }, 378 { X86::FpUCOMIr , X86::FUCOMIr }, 379 { X86::FpUCOMr , X86::FUCOMr }, 380}; 381 382static unsigned getConcreteOpcode(unsigned Opcode) { 383 ASSERT_SORTED(OpcodeTable); 384 int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode); 385 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 386 return Opc; 387} 388 389//===----------------------------------------------------------------------===// 390// Helper Methods 391//===----------------------------------------------------------------------===// 392 393// PopTable - Sorted map of instructions to their popping version. The first 394// element is an instruction, the second is the version which pops. 395// 396static const TableEntry PopTable[] = { 397 { X86::FADDrST0 , X86::FADDPrST0 }, 398 399 { X86::FDIVRrST0, X86::FDIVRPrST0 }, 400 { X86::FDIVrST0 , X86::FDIVPrST0 }, 401 402 { X86::FIST16m , X86::FISTP16m }, 403 { X86::FIST32m , X86::FISTP32m }, 404 405 { X86::FMULrST0 , X86::FMULPrST0 }, 406 407 { X86::FST32m , X86::FSTP32m }, 408 { X86::FST64m , X86::FSTP64m }, 409 { X86::FSTrr , X86::FSTPrr }, 410 411 { X86::FSUBRrST0, X86::FSUBRPrST0 }, 412 { X86::FSUBrST0 , X86::FSUBPrST0 }, 413 414 { X86::FUCOMIr , X86::FUCOMIPr }, 415 416 { X86::FUCOMPr , X86::FUCOMPPr }, 417 { X86::FUCOMr , X86::FUCOMPr }, 418}; 419 420/// popStackAfter - Pop the current value off of the top of the FP stack after 421/// the specified instruction. This attempts to be sneaky and combine the pop 422/// into the instruction itself if possible. The iterator is left pointing to 423/// the last instruction, be it a new pop instruction inserted, or the old 424/// instruction if it was modified in place. 425/// 426void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 427 ASSERT_SORTED(PopTable); 428 assert(StackTop > 0 && "Cannot pop empty stack!"); 429 RegMap[Stack[--StackTop]] = ~0; // Update state 430 431 // Check to see if there is a popping version of this instruction... 432 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); 433 if (Opcode != -1) { 434 I->setInstrDescriptor(TII->get(Opcode)); 435 if (Opcode == X86::FUCOMPPr) 436 I->RemoveOperand(0); 437 } else { // Insert an explicit pop 438 I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0); 439 } 440} 441 442/// freeStackSlotAfter - Free the specified register from the register stack, so 443/// that it is no longer in a register. If the register is currently at the top 444/// of the stack, we just pop the current instruction, otherwise we store the 445/// current top-of-stack into the specified slot, then pop the top of stack. 446void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 447 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 448 popStackAfter(I); 449 return; 450 } 451 452 // Otherwise, store the top of stack into the dead slot, killing the operand 453 // without having to add in an explicit xchg then pop. 454 // 455 unsigned STReg = getSTReg(FPRegNo); 456 unsigned OldSlot = getSlot(FPRegNo); 457 unsigned TopReg = Stack[StackTop-1]; 458 Stack[OldSlot] = TopReg; 459 RegMap[TopReg] = OldSlot; 460 RegMap[FPRegNo] = ~0; 461 Stack[--StackTop] = ~0; 462 I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg); 463} 464 465 466static unsigned getFPReg(const MachineOperand &MO) { 467 assert(MO.isRegister() && "Expected an FP register!"); 468 unsigned Reg = MO.getReg(); 469 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 470 return Reg - X86::FP0; 471} 472 473 474//===----------------------------------------------------------------------===// 475// Instruction transformation implementation 476//===----------------------------------------------------------------------===// 477 478/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 479/// 480void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 481 MachineInstr *MI = I; 482 unsigned DestReg = getFPReg(MI->getOperand(0)); 483 484 // Change from the pseudo instruction to the concrete instruction. 485 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 486 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); 487 488 // Result gets pushed on the stack. 489 pushReg(DestReg); 490} 491 492/// handleOneArgFP - fst <mem>, ST(0) 493/// 494void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 495 MachineInstr *MI = I; 496 unsigned NumOps = MI->getInstrDescriptor()->numOperands; 497 assert((NumOps == 5 || NumOps == 1) && 498 "Can only handle fst* & ftst instructions!"); 499 500 // Is this the last use of the source register? 501 unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); 502 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 503 504 // FISTP64m is strange because there isn't a non-popping versions. 505 // If we have one _and_ we don't want to pop the operand, duplicate the value 506 // on the stack instead of moving it. This ensure that popping the value is 507 // always ok. 508 // Ditto FISTTP16m, FISTTP32m, FISTTP64m. 509 // 510 if (!KillsSrc && 511 (MI->getOpcode() == X86::FpIST64m || 512 MI->getOpcode() == X86::FpISTT16m || 513 MI->getOpcode() == X86::FpISTT32m || 514 MI->getOpcode() == X86::FpISTT64m)) { 515 duplicateToTop(Reg, 7 /*temp register*/, I); 516 } else { 517 moveToTop(Reg, I); // Move to the top of the stack... 518 } 519 520 // Convert from the pseudo instruction to the concrete instruction. 521 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand 522 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); 523 524 if (MI->getOpcode() == X86::FISTP64m || 525 MI->getOpcode() == X86::FISTTP16m || 526 MI->getOpcode() == X86::FISTTP32m || 527 MI->getOpcode() == X86::FISTTP64m) { 528 assert(StackTop > 0 && "Stack empty??"); 529 --StackTop; 530 } else if (KillsSrc) { // Last use of operand? 531 popStackAfter(I); 532 } 533} 534 535 536/// handleOneArgFPRW: Handle instructions that read from the top of stack and 537/// replace the value with a newly computed value. These instructions may have 538/// non-fp operands after their FP operands. 539/// 540/// Examples: 541/// R1 = fchs R2 542/// R1 = fadd R2, [mem] 543/// 544void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 545 MachineInstr *MI = I; 546 unsigned NumOps = MI->getInstrDescriptor()->numOperands; 547 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 548 549 // Is this the last use of the source register? 550 unsigned Reg = getFPReg(MI->getOperand(1)); 551 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 552 553 if (KillsSrc) { 554 // If this is the last use of the source register, just make sure it's on 555 // the top of the stack. 556 moveToTop(Reg, I); 557 assert(StackTop > 0 && "Stack cannot be empty!"); 558 --StackTop; 559 pushReg(getFPReg(MI->getOperand(0))); 560 } else { 561 // If this is not the last use of the source register, _copy_ it to the top 562 // of the stack. 563 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 564 } 565 566 // Change from the pseudo instruction to the concrete instruction. 567 MI->RemoveOperand(1); // Drop the source operand. 568 MI->RemoveOperand(0); // Drop the destination operand. 569 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); 570} 571 572 573//===----------------------------------------------------------------------===// 574// Define tables of various ways to map pseudo instructions 575// 576 577// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 578static const TableEntry ForwardST0Table[] = { 579 { X86::FpADD , X86::FADDST0r }, 580 { X86::FpDIV , X86::FDIVST0r }, 581 { X86::FpMUL , X86::FMULST0r }, 582 { X86::FpSUB , X86::FSUBST0r }, 583}; 584 585// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 586static const TableEntry ReverseST0Table[] = { 587 { X86::FpADD , X86::FADDST0r }, // commutative 588 { X86::FpDIV , X86::FDIVRST0r }, 589 { X86::FpMUL , X86::FMULST0r }, // commutative 590 { X86::FpSUB , X86::FSUBRST0r }, 591}; 592 593// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 594static const TableEntry ForwardSTiTable[] = { 595 { X86::FpADD , X86::FADDrST0 }, // commutative 596 { X86::FpDIV , X86::FDIVRrST0 }, 597 { X86::FpMUL , X86::FMULrST0 }, // commutative 598 { X86::FpSUB , X86::FSUBRrST0 }, 599}; 600 601// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 602static const TableEntry ReverseSTiTable[] = { 603 { X86::FpADD , X86::FADDrST0 }, 604 { X86::FpDIV , X86::FDIVrST0 }, 605 { X86::FpMUL , X86::FMULrST0 }, 606 { X86::FpSUB , X86::FSUBrST0 }, 607}; 608 609 610/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 611/// instructions which need to be simplified and possibly transformed. 612/// 613/// Result: ST(0) = fsub ST(0), ST(i) 614/// ST(i) = fsub ST(0), ST(i) 615/// ST(0) = fsubr ST(0), ST(i) 616/// ST(i) = fsubr ST(0), ST(i) 617/// 618void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 619 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 620 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 621 MachineInstr *MI = I; 622 623 unsigned NumOperands = MI->getInstrDescriptor()->numOperands; 624 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 625 unsigned Dest = getFPReg(MI->getOperand(0)); 626 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 627 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 628 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 629 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 630 631 unsigned TOS = getStackEntry(0); 632 633 // One of our operands must be on the top of the stack. If neither is yet, we 634 // need to move one. 635 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 636 // We can choose to move either operand to the top of the stack. If one of 637 // the operands is killed by this instruction, we want that one so that we 638 // can update right on top of the old version. 639 if (KillsOp0) { 640 moveToTop(Op0, I); // Move dead operand to TOS. 641 TOS = Op0; 642 } else if (KillsOp1) { 643 moveToTop(Op1, I); 644 TOS = Op1; 645 } else { 646 // All of the operands are live after this instruction executes, so we 647 // cannot update on top of any operand. Because of this, we must 648 // duplicate one of the stack elements to the top. It doesn't matter 649 // which one we pick. 650 // 651 duplicateToTop(Op0, Dest, I); 652 Op0 = TOS = Dest; 653 KillsOp0 = true; 654 } 655 } else if (!KillsOp0 && !KillsOp1) { 656 // If we DO have one of our operands at the top of the stack, but we don't 657 // have a dead operand, we must duplicate one of the operands to a new slot 658 // on the stack. 659 duplicateToTop(Op0, Dest, I); 660 Op0 = TOS = Dest; 661 KillsOp0 = true; 662 } 663 664 // Now we know that one of our operands is on the top of the stack, and at 665 // least one of our operands is killed by this instruction. 666 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 667 "Stack conditions not set up right!"); 668 669 // We decide which form to use based on what is on the top of the stack, and 670 // which operand is killed by this instruction. 671 const TableEntry *InstTable; 672 bool isForward = TOS == Op0; 673 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 674 if (updateST0) { 675 if (isForward) 676 InstTable = ForwardST0Table; 677 else 678 InstTable = ReverseST0Table; 679 } else { 680 if (isForward) 681 InstTable = ForwardSTiTable; 682 else 683 InstTable = ReverseSTiTable; 684 } 685 686 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode()); 687 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 688 689 // NotTOS - The register which is not on the top of stack... 690 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 691 692 // Replace the old instruction with a new instruction 693 MBB->remove(I++); 694 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 695 696 // If both operands are killed, pop one off of the stack in addition to 697 // overwriting the other one. 698 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 699 assert(!updateST0 && "Should have updated other operand!"); 700 popStackAfter(I); // Pop the top of stack 701 } 702 703 // Update stack information so that we know the destination register is now on 704 // the stack. 705 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 706 assert(UpdatedSlot < StackTop && Dest < 7); 707 Stack[UpdatedSlot] = Dest; 708 RegMap[Dest] = UpdatedSlot; 709 delete MI; // Remove the old instruction 710} 711 712/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 713/// register arguments and no explicit destinations. 714/// 715void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 716 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 717 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 718 MachineInstr *MI = I; 719 720 unsigned NumOperands = MI->getInstrDescriptor()->numOperands; 721 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 722 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 723 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 724 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 725 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 726 727 // Make sure the first operand is on the top of stack, the other one can be 728 // anywhere. 729 moveToTop(Op0, I); 730 731 // Change from the pseudo instruction to the concrete instruction. 732 MI->getOperand(0).setReg(getSTReg(Op1)); 733 MI->RemoveOperand(1); 734 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); 735 736 // If any of the operands are killed by this instruction, free them. 737 if (KillsOp0) freeStackSlotAfter(I, Op0); 738 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 739} 740 741/// handleCondMovFP - Handle two address conditional move instructions. These 742/// instructions move a st(i) register to st(0) iff a condition is true. These 743/// instructions require that the first operand is at the top of the stack, but 744/// otherwise don't modify the stack at all. 745void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 746 MachineInstr *MI = I; 747 748 unsigned Op0 = getFPReg(MI->getOperand(0)); 749 unsigned Op1 = getFPReg(MI->getOperand(2)); 750 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 751 752 // The first operand *must* be on the top of the stack. 753 moveToTop(Op0, I); 754 755 // Change the second operand to the stack register that the operand is in. 756 // Change from the pseudo instruction to the concrete instruction. 757 MI->RemoveOperand(0); 758 MI->RemoveOperand(1); 759 MI->getOperand(0).setReg(getSTReg(Op1)); 760 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); 761 762 // If we kill the second operand, make sure to pop it from the stack. 763 if (Op0 != Op1 && KillsOp1) { 764 // Get this value off of the register stack. 765 freeStackSlotAfter(I, Op1); 766 } 767} 768 769 770/// handleSpecialFP - Handle special instructions which behave unlike other 771/// floating point instructions. This is primarily intended for use by pseudo 772/// instructions. 773/// 774void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 775 MachineInstr *MI = I; 776 switch (MI->getOpcode()) { 777 default: assert(0 && "Unknown SpecialFP instruction!"); 778 case X86::FpGETRESULT: // Appears immediately after a call returning FP type! 779 assert(StackTop == 0 && "Stack should be empty after a call!"); 780 pushReg(getFPReg(MI->getOperand(0))); 781 break; 782 case X86::FpSETRESULT: 783 assert(StackTop == 1 && "Stack should have one element on it to return!"); 784 --StackTop; // "Forget" we have something on the top of stack! 785 break; 786 case X86::FpMOV: { 787 unsigned SrcReg = getFPReg(MI->getOperand(1)); 788 unsigned DestReg = getFPReg(MI->getOperand(0)); 789 790 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) { 791 // If the input operand is killed, we can just change the owner of the 792 // incoming stack slot into the result. 793 unsigned Slot = getSlot(SrcReg); 794 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 795 Stack[Slot] = DestReg; 796 RegMap[DestReg] = Slot; 797 798 } else { 799 // For FMOV we just duplicate the specified value to a new stack slot. 800 // This could be made better, but would require substantial changes. 801 duplicateToTop(SrcReg, DestReg, I); 802 } 803 break; 804 } 805 } 806 807 I = MBB->erase(I); // Remove the pseudo instruction 808 --I; 809} 810