X86FloatingPoint.cpp revision ae73dc1448d25b02cabc7c64c86c64371453dda8 
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions.  This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code.  In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges.  Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet.  The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/ADT/DepthFirstIterator.h"
43#include "llvm/ADT/SmallPtrSet.h"
44#include "llvm/ADT/SmallVector.h"
45#include "llvm/ADT/Statistic.h"
46#include "llvm/ADT/STLExtras.h"
47#include <algorithm>
48using namespace llvm;
49
50STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51STATISTIC(NumFP  , "Number of floating point instructions");
52
53namespace {
54  struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55    static char ID;
56    FPS() : MachineFunctionPass(&ID) {}
57
58    virtual bool runOnMachineFunction(MachineFunction &MF);
59
60    virtual const char *getPassName() const { return "X86 FP Stackifier"; }
61
62  private:
63    const TargetInstrInfo *TII; // Machine instruction info.
64    MachineBasicBlock *MBB;     // Current basic block
65    unsigned Stack[8];          // FP<n> Registers in each stack slot...
66    unsigned RegMap[8];         // Track which stack slot contains each register
67    unsigned StackTop;          // The current top of the FP stack.
68
69    void dumpStack() const {
70      cerr << "Stack contents:";
71      for (unsigned i = 0; i != StackTop; ++i) {
72        cerr << " FP" << Stack[i];
73        assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
74      }
75      cerr << "\n";
76    }
77  private:
78    /// isStackEmpty - Return true if the FP stack is empty.
79    bool isStackEmpty() const {
80      return StackTop == 0;
81    }
82
83    // getSlot - Return the stack slot number a particular register number is
84    // in.
85    unsigned getSlot(unsigned RegNo) const {
86      assert(RegNo < 8 && "Regno out of range!");
87      return RegMap[RegNo];
88    }
89
90    // getStackEntry - Return the X86::FP<n> register in register ST(i).
91    unsigned getStackEntry(unsigned STi) const {
92      assert(STi < StackTop && "Access past stack top!");
93      return Stack[StackTop-1-STi];
94    }
95
96    // getSTReg - Return the X86::ST(i) register which contains the specified
97    // FP<RegNo> register.
98    unsigned getSTReg(unsigned RegNo) const {
99      return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
100    }
101
102    // pushReg - Push the specified FP<n> register onto the stack.
103    void pushReg(unsigned Reg) {
104      assert(Reg < 8 && "Register number out of range!");
105      assert(StackTop < 8 && "Stack overflow!");
106      Stack[StackTop] = Reg;
107      RegMap[Reg] = StackTop++;
108    }
109
110    bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
111    void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
112      if (isAtTop(RegNo)) return;
113
114      unsigned STReg = getSTReg(RegNo);
115      unsigned RegOnTop = getStackEntry(0);
116
117      // Swap the slots the regs are in.
118      std::swap(RegMap[RegNo], RegMap[RegOnTop]);
119
120      // Swap stack slot contents.
121      assert(RegMap[RegOnTop] < StackTop);
122      std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
123
124      // Emit an fxch to update the runtime processors version of the state.
125      BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
126      NumFXCH++;
127    }
128
129    void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
130      unsigned STReg = getSTReg(RegNo);
131      pushReg(AsReg);   // New register on top of stack
132
133      BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
134    }
135
136    // popStackAfter - Pop the current value off of the top of the FP stack
137    // after the specified instruction.
138    void popStackAfter(MachineBasicBlock::iterator &I);
139
140    // freeStackSlotAfter - Free the specified register from the register stack,
141    // so that it is no longer in a register.  If the register is currently at
142    // the top of the stack, we just pop the current instruction, otherwise we
143    // store the current top-of-stack into the specified slot, then pop the top
144    // of stack.
145    void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
146
147    bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
148
149    void handleZeroArgFP(MachineBasicBlock::iterator &I);
150    void handleOneArgFP(MachineBasicBlock::iterator &I);
151    void handleOneArgFPRW(MachineBasicBlock::iterator &I);
152    void handleTwoArgFP(MachineBasicBlock::iterator &I);
153    void handleCompareFP(MachineBasicBlock::iterator &I);
154    void handleCondMovFP(MachineBasicBlock::iterator &I);
155    void handleSpecialFP(MachineBasicBlock::iterator &I);
156  };
157  char FPS::ID = 0;
158}
159
160FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
161
162/// getFPReg - Return the X86::FPx register number for the specified operand.
163/// For example, this returns 3 for X86::FP3.
164static unsigned getFPReg(const MachineOperand &MO) {
165  assert(MO.isRegister() && "Expected an FP register!");
166  unsigned Reg = MO.getReg();
167  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
168  return Reg - X86::FP0;
169}
170
171
172/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
173/// register references into FP stack references.
174///
175bool FPS::runOnMachineFunction(MachineFunction &MF) {
176  // We only need to run this pass if there are any FP registers used in this
177  // function.  If it is all integer, there is nothing for us to do!
178  bool FPIsUsed = false;
179
180  assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
181  for (unsigned i = 0; i <= 6; ++i)
182    if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
183      FPIsUsed = true;
184      break;
185    }
186
187  // Early exit.
188  if (!FPIsUsed) return false;
189
190  TII = MF.getTarget().getInstrInfo();
191  StackTop = 0;
192
193  // Process the function in depth first order so that we process at least one
194  // of the predecessors for every reachable block in the function.
195  SmallPtrSet<MachineBasicBlock*, 8> Processed;
196  MachineBasicBlock *Entry = MF.begin();
197
198  bool Changed = false;
199  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
200         I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
201       I != E; ++I)
202    Changed |= processBasicBlock(MF, **I);
203
204  return Changed;
205}
206
207/// processBasicBlock - Loop over all of the instructions in the basic block,
208/// transforming FP instructions into their stack form.
209///
210bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
211  bool Changed = false;
212  MBB = &BB;
213
214  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
215    MachineInstr *MI = I;
216    unsigned Flags = MI->getDesc().TSFlags;
217
218    unsigned FPInstClass = Flags & X86II::FPTypeMask;
219    if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
220      FPInstClass = X86II::SpecialFP;
221
222    if (FPInstClass == X86II::NotFP)
223      continue;  // Efficiently ignore non-fp insts!
224
225    MachineInstr *PrevMI = 0;
226    if (I != BB.begin())
227      PrevMI = prior(I);
228
229    ++NumFP;  // Keep track of # of pseudo instrs
230    DOUT << "\nFPInst:\t" << *MI;
231
232    // Get dead variables list now because the MI pointer may be deleted as part
233    // of processing!
234    SmallVector<unsigned, 8> DeadRegs;
235    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236      const MachineOperand &MO = MI->getOperand(i);
237      if (MO.isRegister() && MO.isDead())
238        DeadRegs.push_back(MO.getReg());
239    }
240
241    switch (FPInstClass) {
242    case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
243    case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
244    case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
245    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
246    case X86II::CompareFP:  handleCompareFP(I); break;
247    case X86II::CondMovFP:  handleCondMovFP(I); break;
248    case X86II::SpecialFP:  handleSpecialFP(I); break;
249    default: assert(0 && "Unknown FP Type!");
250    }
251
252    // Check to see if any of the values defined by this instruction are dead
253    // after definition.  If so, pop them.
254    for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
255      unsigned Reg = DeadRegs[i];
256      if (Reg >= X86::FP0 && Reg <= X86::FP6) {
257        DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
258        freeStackSlotAfter(I, Reg-X86::FP0);
259      }
260    }
261
262    // Print out all of the instructions expanded to if -debug
263    DEBUG(
264      MachineBasicBlock::iterator PrevI(PrevMI);
265      if (I == PrevI) {
266        cerr << "Just deleted pseudo instruction\n";
267      } else {
268        MachineBasicBlock::iterator Start = I;
269        // Rewind to first instruction newly inserted.
270        while (Start != BB.begin() && prior(Start) != PrevI) --Start;
271        cerr << "Inserted instructions:\n\t";
272        Start->print(*cerr.stream(), &MF.getTarget());
273        while (++Start != next(I)) {}
274      }
275      dumpStack();
276    );
277
278    Changed = true;
279  }
280
281  assert(isStackEmpty() && "Stack not empty at end of basic block?");
282  return Changed;
283}
284
285//===----------------------------------------------------------------------===//
286// Efficient Lookup Table Support
287//===----------------------------------------------------------------------===//
288
289namespace {
290  struct TableEntry {
291    unsigned from;
292    unsigned to;
293    bool operator<(const TableEntry &TE) const { return from < TE.from; }
294    friend bool operator<(const TableEntry &TE, unsigned V) {
295      return TE.from < V;
296    }
297    friend bool operator<(unsigned V, const TableEntry &TE) {
298      return V < TE.from;
299    }
300  };
301}
302
303#ifndef NDEBUG
304static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
305  for (unsigned i = 0; i != NumEntries-1; ++i)
306    if (!(Table[i] < Table[i+1])) return false;
307  return true;
308}
309#endif
310
311static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
312  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
313  if (I != Table+N && I->from == Opcode)
314    return I->to;
315  return -1;
316}
317
318#ifdef NDEBUG
319#define ASSERT_SORTED(TABLE)
320#else
321#define ASSERT_SORTED(TABLE)                                              \
322  { static bool TABLE##Checked = false;                                   \
323    if (!TABLE##Checked) {                                                \
324       assert(TableIsSorted(TABLE, array_lengthof(TABLE)) &&              \
325              "All lookup tables must be sorted for efficient access!");  \
326       TABLE##Checked = true;                                             \
327    }                                                                     \
328  }
329#endif
330
331//===----------------------------------------------------------------------===//
332// Register File -> Register Stack Mapping Methods
333//===----------------------------------------------------------------------===//
334
335// OpcodeTable - Sorted map of register instructions to their stack version.
336// The first element is an register file pseudo instruction, the second is the
337// concrete X86 instruction which uses the register stack.
338//
339static const TableEntry OpcodeTable[] = {
340  { X86::ABS_Fp32     , X86::ABS_F     },
341  { X86::ABS_Fp64     , X86::ABS_F     },
342  { X86::ABS_Fp80     , X86::ABS_F     },
343  { X86::ADD_Fp32m    , X86::ADD_F32m  },
344  { X86::ADD_Fp64m    , X86::ADD_F64m  },
345  { X86::ADD_Fp64m32  , X86::ADD_F32m  },
346  { X86::ADD_Fp80m32  , X86::ADD_F32m  },
347  { X86::ADD_Fp80m64  , X86::ADD_F64m  },
348  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
349  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
350  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
351  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
352  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
353  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
354  { X86::CHS_Fp32     , X86::CHS_F     },
355  { X86::CHS_Fp64     , X86::CHS_F     },
356  { X86::CHS_Fp80     , X86::CHS_F     },
357  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
358  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
359  { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
360  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
361  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
362  { X86::CMOVB_Fp80   , X86::CMOVB_F  },
363  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
364  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
365  { X86::CMOVE_Fp80   , X86::CMOVE_F   },
366  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
367  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
368  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
369  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
370  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
371  { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
372  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
373  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
374  { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
375  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
376  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
377  { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
378  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
379  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
380  { X86::CMOVP_Fp80   , X86::CMOVP_F   },
381  { X86::COS_Fp32     , X86::COS_F     },
382  { X86::COS_Fp64     , X86::COS_F     },
383  { X86::COS_Fp80     , X86::COS_F     },
384  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
385  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
386  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
387  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
388  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
389  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
390  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
391  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
392  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
393  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
394  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
395  { X86::DIV_Fp32m    , X86::DIV_F32m  },
396  { X86::DIV_Fp64m    , X86::DIV_F64m  },
397  { X86::DIV_Fp64m32  , X86::DIV_F32m  },
398  { X86::DIV_Fp80m32  , X86::DIV_F32m  },
399  { X86::DIV_Fp80m64  , X86::DIV_F64m  },
400  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
401  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
402  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
403  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
404  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
405  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
406  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
407  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
408  { X86::ILD_Fp16m80  , X86::ILD_F16m  },
409  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
410  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
411  { X86::ILD_Fp32m80  , X86::ILD_F32m  },
412  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
413  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
414  { X86::ILD_Fp64m80  , X86::ILD_F64m  },
415  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
416  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
417  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
418  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
419  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
420  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
421  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
422  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
423  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
424  { X86::IST_Fp16m32  , X86::IST_F16m  },
425  { X86::IST_Fp16m64  , X86::IST_F16m  },
426  { X86::IST_Fp16m80  , X86::IST_F16m  },
427  { X86::IST_Fp32m32  , X86::IST_F32m  },
428  { X86::IST_Fp32m64  , X86::IST_F32m  },
429  { X86::IST_Fp32m80  , X86::IST_F32m  },
430  { X86::IST_Fp64m32  , X86::IST_FP64m },
431  { X86::IST_Fp64m64  , X86::IST_FP64m },
432  { X86::IST_Fp64m80  , X86::IST_FP64m },
433  { X86::LD_Fp032     , X86::LD_F0     },
434  { X86::LD_Fp064     , X86::LD_F0     },
435  { X86::LD_Fp080     , X86::LD_F0     },
436  { X86::LD_Fp132     , X86::LD_F1     },
437  { X86::LD_Fp164     , X86::LD_F1     },
438  { X86::LD_Fp180     , X86::LD_F1     },
439  { X86::LD_Fp32m     , X86::LD_F32m   },
440  { X86::LD_Fp32m64   , X86::LD_F32m   },
441  { X86::LD_Fp32m80   , X86::LD_F32m   },
442  { X86::LD_Fp64m     , X86::LD_F64m   },
443  { X86::LD_Fp64m80   , X86::LD_F64m   },
444  { X86::LD_Fp80m     , X86::LD_F80m   },
445  { X86::MUL_Fp32m    , X86::MUL_F32m  },
446  { X86::MUL_Fp64m    , X86::MUL_F64m  },
447  { X86::MUL_Fp64m32  , X86::MUL_F32m  },
448  { X86::MUL_Fp80m32  , X86::MUL_F32m  },
449  { X86::MUL_Fp80m64  , X86::MUL_F64m  },
450  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
451  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
452  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
453  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
454  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
455  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
456  { X86::SIN_Fp32     , X86::SIN_F     },
457  { X86::SIN_Fp64     , X86::SIN_F     },
458  { X86::SIN_Fp80     , X86::SIN_F     },
459  { X86::SQRT_Fp32    , X86::SQRT_F    },
460  { X86::SQRT_Fp64    , X86::SQRT_F    },
461  { X86::SQRT_Fp80    , X86::SQRT_F    },
462  { X86::ST_Fp32m     , X86::ST_F32m   },
463  { X86::ST_Fp64m     , X86::ST_F64m   },
464  { X86::ST_Fp64m32   , X86::ST_F32m   },
465  { X86::ST_Fp80m32   , X86::ST_F32m   },
466  { X86::ST_Fp80m64   , X86::ST_F64m   },
467  { X86::ST_FpP80m    , X86::ST_FP80m  },
468  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
469  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
470  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
471  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
472  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
473  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
474  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
475  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
476  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
477  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
478  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
479  { X86::SUB_Fp32m    , X86::SUB_F32m  },
480  { X86::SUB_Fp64m    , X86::SUB_F64m  },
481  { X86::SUB_Fp64m32  , X86::SUB_F32m  },
482  { X86::SUB_Fp80m32  , X86::SUB_F32m  },
483  { X86::SUB_Fp80m64  , X86::SUB_F64m  },
484  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
485  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
486  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
487  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
488  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
489  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
490  { X86::TST_Fp32     , X86::TST_F     },
491  { X86::TST_Fp64     , X86::TST_F     },
492  { X86::TST_Fp80     , X86::TST_F     },
493  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
494  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
495  { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
496  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
497  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
498  { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
499};
500
501static unsigned getConcreteOpcode(unsigned Opcode) {
502  ASSERT_SORTED(OpcodeTable);
503  int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
504  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
505  return Opc;
506}
507
508//===----------------------------------------------------------------------===//
509// Helper Methods
510//===----------------------------------------------------------------------===//
511
512// PopTable - Sorted map of instructions to their popping version.  The first
513// element is an instruction, the second is the version which pops.
514//
515static const TableEntry PopTable[] = {
516  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
517
518  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
519  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
520
521  { X86::IST_F16m  , X86::IST_FP16m   },
522  { X86::IST_F32m  , X86::IST_FP32m   },
523
524  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
525
526  { X86::ST_F32m   , X86::ST_FP32m    },
527  { X86::ST_F64m   , X86::ST_FP64m    },
528  { X86::ST_Frr    , X86::ST_FPrr     },
529
530  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
531  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
532
533  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
534
535  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
536  { X86::UCOM_Fr   , X86::UCOM_FPr    },
537};
538
539/// popStackAfter - Pop the current value off of the top of the FP stack after
540/// the specified instruction.  This attempts to be sneaky and combine the pop
541/// into the instruction itself if possible.  The iterator is left pointing to
542/// the last instruction, be it a new pop instruction inserted, or the old
543/// instruction if it was modified in place.
544///
545void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
546  ASSERT_SORTED(PopTable);
547  assert(StackTop > 0 && "Cannot pop empty stack!");
548  RegMap[Stack[--StackTop]] = ~0;     // Update state
549
550  // Check to see if there is a popping version of this instruction...
551  int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
552  if (Opcode != -1) {
553    I->setDesc(TII->get(Opcode));
554    if (Opcode == X86::UCOM_FPPr)
555      I->RemoveOperand(0);
556  } else {    // Insert an explicit pop
557    I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
558  }
559}
560
561/// freeStackSlotAfter - Free the specified register from the register stack, so
562/// that it is no longer in a register.  If the register is currently at the top
563/// of the stack, we just pop the current instruction, otherwise we store the
564/// current top-of-stack into the specified slot, then pop the top of stack.
565void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
566  if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
567    popStackAfter(I);
568    return;
569  }
570
571  // Otherwise, store the top of stack into the dead slot, killing the operand
572  // without having to add in an explicit xchg then pop.
573  //
574  unsigned STReg    = getSTReg(FPRegNo);
575  unsigned OldSlot  = getSlot(FPRegNo);
576  unsigned TopReg   = Stack[StackTop-1];
577  Stack[OldSlot]    = TopReg;
578  RegMap[TopReg]    = OldSlot;
579  RegMap[FPRegNo]   = ~0;
580  Stack[--StackTop] = ~0;
581  I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
582}
583
584
585//===----------------------------------------------------------------------===//
586// Instruction transformation implementation
587//===----------------------------------------------------------------------===//
588
589/// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
590///
591void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
592  MachineInstr *MI = I;
593  unsigned DestReg = getFPReg(MI->getOperand(0));
594
595  // Change from the pseudo instruction to the concrete instruction.
596  MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
597  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
598
599  // Result gets pushed on the stack.
600  pushReg(DestReg);
601}
602
603/// handleOneArgFP - fst <mem>, ST(0)
604///
605void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
606  MachineInstr *MI = I;
607  unsigned NumOps = MI->getDesc().getNumOperands();
608  assert((NumOps == 5 || NumOps == 1) &&
609         "Can only handle fst* & ftst instructions!");
610
611  // Is this the last use of the source register?
612  unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
613  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
614
615  // FISTP64m is strange because there isn't a non-popping versions.
616  // If we have one _and_ we don't want to pop the operand, duplicate the value
617  // on the stack instead of moving it.  This ensure that popping the value is
618  // always ok.
619  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
620  //
621  if (!KillsSrc &&
622      (MI->getOpcode() == X86::IST_Fp64m32 ||
623       MI->getOpcode() == X86::ISTT_Fp16m32 ||
624       MI->getOpcode() == X86::ISTT_Fp32m32 ||
625       MI->getOpcode() == X86::ISTT_Fp64m32 ||
626       MI->getOpcode() == X86::IST_Fp64m64 ||
627       MI->getOpcode() == X86::ISTT_Fp16m64 ||
628       MI->getOpcode() == X86::ISTT_Fp32m64 ||
629       MI->getOpcode() == X86::ISTT_Fp64m64 ||
630       MI->getOpcode() == X86::IST_Fp64m80 ||
631       MI->getOpcode() == X86::ISTT_Fp16m80 ||
632       MI->getOpcode() == X86::ISTT_Fp32m80 ||
633       MI->getOpcode() == X86::ISTT_Fp64m80 ||
634       MI->getOpcode() == X86::ST_FpP80m)) {
635    duplicateToTop(Reg, 7 /*temp register*/, I);
636  } else {
637    moveToTop(Reg, I);            // Move to the top of the stack...
638  }
639
640  // Convert from the pseudo instruction to the concrete instruction.
641  MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
642  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
643
644  if (MI->getOpcode() == X86::IST_FP64m ||
645      MI->getOpcode() == X86::ISTT_FP16m ||
646      MI->getOpcode() == X86::ISTT_FP32m ||
647      MI->getOpcode() == X86::ISTT_FP64m ||
648      MI->getOpcode() == X86::ST_FP80m) {
649    assert(StackTop > 0 && "Stack empty??");
650    --StackTop;
651  } else if (KillsSrc) { // Last use of operand?
652    popStackAfter(I);
653  }
654}
655
656
657/// handleOneArgFPRW: Handle instructions that read from the top of stack and
658/// replace the value with a newly computed value.  These instructions may have
659/// non-fp operands after their FP operands.
660///
661///  Examples:
662///     R1 = fchs R2
663///     R1 = fadd R2, [mem]
664///
665void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
666  MachineInstr *MI = I;
667#ifndef NDEBUG
668  unsigned NumOps = MI->getDesc().getNumOperands();
669  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
670#endif
671
672  // Is this the last use of the source register?
673  unsigned Reg = getFPReg(MI->getOperand(1));
674  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
675
676  if (KillsSrc) {
677    // If this is the last use of the source register, just make sure it's on
678    // the top of the stack.
679    moveToTop(Reg, I);
680    assert(StackTop > 0 && "Stack cannot be empty!");
681    --StackTop;
682    pushReg(getFPReg(MI->getOperand(0)));
683  } else {
684    // If this is not the last use of the source register, _copy_ it to the top
685    // of the stack.
686    duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
687  }
688
689  // Change from the pseudo instruction to the concrete instruction.
690  MI->RemoveOperand(1);   // Drop the source operand.
691  MI->RemoveOperand(0);   // Drop the destination operand.
692  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
693}
694
695
696//===----------------------------------------------------------------------===//
697// Define tables of various ways to map pseudo instructions
698//
699
700// ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
701static const TableEntry ForwardST0Table[] = {
702  { X86::ADD_Fp32  , X86::ADD_FST0r },
703  { X86::ADD_Fp64  , X86::ADD_FST0r },
704  { X86::ADD_Fp80  , X86::ADD_FST0r },
705  { X86::DIV_Fp32  , X86::DIV_FST0r },
706  { X86::DIV_Fp64  , X86::DIV_FST0r },
707  { X86::DIV_Fp80  , X86::DIV_FST0r },
708  { X86::MUL_Fp32  , X86::MUL_FST0r },
709  { X86::MUL_Fp64  , X86::MUL_FST0r },
710  { X86::MUL_Fp80  , X86::MUL_FST0r },
711  { X86::SUB_Fp32  , X86::SUB_FST0r },
712  { X86::SUB_Fp64  , X86::SUB_FST0r },
713  { X86::SUB_Fp80  , X86::SUB_FST0r },
714};
715
716// ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
717static const TableEntry ReverseST0Table[] = {
718  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
719  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
720  { X86::ADD_Fp80  , X86::ADD_FST0r  },   // commutative
721  { X86::DIV_Fp32  , X86::DIVR_FST0r },
722  { X86::DIV_Fp64  , X86::DIVR_FST0r },
723  { X86::DIV_Fp80  , X86::DIVR_FST0r },
724  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
725  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
726  { X86::MUL_Fp80  , X86::MUL_FST0r  },   // commutative
727  { X86::SUB_Fp32  , X86::SUBR_FST0r },
728  { X86::SUB_Fp64  , X86::SUBR_FST0r },
729  { X86::SUB_Fp80  , X86::SUBR_FST0r },
730};
731
732// ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
733static const TableEntry ForwardSTiTable[] = {
734  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
735  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
736  { X86::ADD_Fp80  , X86::ADD_FrST0  },   // commutative
737  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
738  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
739  { X86::DIV_Fp80  , X86::DIVR_FrST0 },
740  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
741  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
742  { X86::MUL_Fp80  , X86::MUL_FrST0  },   // commutative
743  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
744  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
745  { X86::SUB_Fp80  , X86::SUBR_FrST0 },
746};
747
748// ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
749static const TableEntry ReverseSTiTable[] = {
750  { X86::ADD_Fp32  , X86::ADD_FrST0 },
751  { X86::ADD_Fp64  , X86::ADD_FrST0 },
752  { X86::ADD_Fp80  , X86::ADD_FrST0 },
753  { X86::DIV_Fp32  , X86::DIV_FrST0 },
754  { X86::DIV_Fp64  , X86::DIV_FrST0 },
755  { X86::DIV_Fp80  , X86::DIV_FrST0 },
756  { X86::MUL_Fp32  , X86::MUL_FrST0 },
757  { X86::MUL_Fp64  , X86::MUL_FrST0 },
758  { X86::MUL_Fp80  , X86::MUL_FrST0 },
759  { X86::SUB_Fp32  , X86::SUB_FrST0 },
760  { X86::SUB_Fp64  , X86::SUB_FrST0 },
761  { X86::SUB_Fp80  , X86::SUB_FrST0 },
762};
763
764
765/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
766/// instructions which need to be simplified and possibly transformed.
767///
768/// Result: ST(0) = fsub  ST(0), ST(i)
769///         ST(i) = fsub  ST(0), ST(i)
770///         ST(0) = fsubr ST(0), ST(i)
771///         ST(i) = fsubr ST(0), ST(i)
772///
773void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
774  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
775  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
776  MachineInstr *MI = I;
777
778  unsigned NumOperands = MI->getDesc().getNumOperands();
779  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
780  unsigned Dest = getFPReg(MI->getOperand(0));
781  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
782  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
783  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
784  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
785
786  unsigned TOS = getStackEntry(0);
787
788  // One of our operands must be on the top of the stack.  If neither is yet, we
789  // need to move one.
790  if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
791    // We can choose to move either operand to the top of the stack.  If one of
792    // the operands is killed by this instruction, we want that one so that we
793    // can update right on top of the old version.
794    if (KillsOp0) {
795      moveToTop(Op0, I);         // Move dead operand to TOS.
796      TOS = Op0;
797    } else if (KillsOp1) {
798      moveToTop(Op1, I);
799      TOS = Op1;
800    } else {
801      // All of the operands are live after this instruction executes, so we
802      // cannot update on top of any operand.  Because of this, we must
803      // duplicate one of the stack elements to the top.  It doesn't matter
804      // which one we pick.
805      //
806      duplicateToTop(Op0, Dest, I);
807      Op0 = TOS = Dest;
808      KillsOp0 = true;
809    }
810  } else if (!KillsOp0 && !KillsOp1) {
811    // If we DO have one of our operands at the top of the stack, but we don't
812    // have a dead operand, we must duplicate one of the operands to a new slot
813    // on the stack.
814    duplicateToTop(Op0, Dest, I);
815    Op0 = TOS = Dest;
816    KillsOp0 = true;
817  }
818
819  // Now we know that one of our operands is on the top of the stack, and at
820  // least one of our operands is killed by this instruction.
821  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
822         "Stack conditions not set up right!");
823
824  // We decide which form to use based on what is on the top of the stack, and
825  // which operand is killed by this instruction.
826  const TableEntry *InstTable;
827  bool isForward = TOS == Op0;
828  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
829  if (updateST0) {
830    if (isForward)
831      InstTable = ForwardST0Table;
832    else
833      InstTable = ReverseST0Table;
834  } else {
835    if (isForward)
836      InstTable = ForwardSTiTable;
837    else
838      InstTable = ReverseSTiTable;
839  }
840
841  int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
842                      MI->getOpcode());
843  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
844
845  // NotTOS - The register which is not on the top of stack...
846  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
847
848  // Replace the old instruction with a new instruction
849  MBB->remove(I++);
850  I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
851
852  // If both operands are killed, pop one off of the stack in addition to
853  // overwriting the other one.
854  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
855    assert(!updateST0 && "Should have updated other operand!");
856    popStackAfter(I);   // Pop the top of stack
857  }
858
859  // Update stack information so that we know the destination register is now on
860  // the stack.
861  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
862  assert(UpdatedSlot < StackTop && Dest < 7);
863  Stack[UpdatedSlot]   = Dest;
864  RegMap[Dest]         = UpdatedSlot;
865  MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
866}
867
868/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
869/// register arguments and no explicit destinations.
870///
871void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
872  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
873  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
874  MachineInstr *MI = I;
875
876  unsigned NumOperands = MI->getDesc().getNumOperands();
877  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
878  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
879  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
880  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
881  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
882
883  // Make sure the first operand is on the top of stack, the other one can be
884  // anywhere.
885  moveToTop(Op0, I);
886
887  // Change from the pseudo instruction to the concrete instruction.
888  MI->getOperand(0).setReg(getSTReg(Op1));
889  MI->RemoveOperand(1);
890  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
891
892  // If any of the operands are killed by this instruction, free them.
893  if (KillsOp0) freeStackSlotAfter(I, Op0);
894  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
895}
896
897/// handleCondMovFP - Handle two address conditional move instructions.  These
898/// instructions move a st(i) register to st(0) iff a condition is true.  These
899/// instructions require that the first operand is at the top of the stack, but
900/// otherwise don't modify the stack at all.
901void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
902  MachineInstr *MI = I;
903
904  unsigned Op0 = getFPReg(MI->getOperand(0));
905  unsigned Op1 = getFPReg(MI->getOperand(2));
906  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
907
908  // The first operand *must* be on the top of the stack.
909  moveToTop(Op0, I);
910
911  // Change the second operand to the stack register that the operand is in.
912  // Change from the pseudo instruction to the concrete instruction.
913  MI->RemoveOperand(0);
914  MI->RemoveOperand(1);
915  MI->getOperand(0).setReg(getSTReg(Op1));
916  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
917
918  // If we kill the second operand, make sure to pop it from the stack.
919  if (Op0 != Op1 && KillsOp1) {
920    // Get this value off of the register stack.
921    freeStackSlotAfter(I, Op1);
922  }
923}
924
925
926/// handleSpecialFP - Handle special instructions which behave unlike other
927/// floating point instructions.  This is primarily intended for use by pseudo
928/// instructions.
929///
930void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
931  MachineInstr *MI = I;
932  switch (MI->getOpcode()) {
933  default: assert(0 && "Unknown SpecialFP instruction!");
934  case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
935  case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
936  case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
937    assert(StackTop == 0 && "Stack should be empty after a call!");
938    pushReg(getFPReg(MI->getOperand(0)));
939    break;
940  case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
941  case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
942  case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
943    // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
944    // The pattern we expect is:
945    //  CALL
946    //  FP1 = FpGET_ST0
947    //  FP4 = FpGET_ST1
948    //
949    // At this point, we've pushed FP1 on the top of stack, so it should be
950    // present if it isn't dead.  If it was dead, we already emitted a pop to
951    // remove it from the stack and StackTop = 0.
952
953    // Push FP4 as top of stack next.
954    pushReg(getFPReg(MI->getOperand(0)));
955
956    // If StackTop was 0 before we pushed our operand, then ST(0) must have been
957    // dead.  In this case, the ST(1) value is the only thing that is live, so
958    // it should be on the TOS (after the pop that was emitted) and is.  Just
959    // continue in this case.
960    if (StackTop == 1)
961      break;
962
963    // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
964    // elements so that our accounting is correct.
965    unsigned RegOnTop = getStackEntry(0);
966    unsigned RegNo = getStackEntry(1);
967
968    // Swap the slots the regs are in.
969    std::swap(RegMap[RegNo], RegMap[RegOnTop]);
970
971    // Swap stack slot contents.
972    assert(RegMap[RegOnTop] < StackTop);
973    std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
974    break;
975  }
976  case X86::FpSET_ST0_32:
977  case X86::FpSET_ST0_64:
978  case X86::FpSET_ST0_80:
979    assert(StackTop == 1 && "Stack should have one element on it to return!");
980    --StackTop;   // "Forget" we have something on the top of stack!
981    break;
982  case X86::MOV_Fp3232:
983  case X86::MOV_Fp3264:
984  case X86::MOV_Fp6432:
985  case X86::MOV_Fp6464:
986  case X86::MOV_Fp3280:
987  case X86::MOV_Fp6480:
988  case X86::MOV_Fp8032:
989  case X86::MOV_Fp8064:
990  case X86::MOV_Fp8080: {
991    unsigned SrcReg = getFPReg(MI->getOperand(1));
992    unsigned DestReg = getFPReg(MI->getOperand(0));
993
994    if (MI->killsRegister(X86::FP0+SrcReg)) {
995      // If the input operand is killed, we can just change the owner of the
996      // incoming stack slot into the result.
997      unsigned Slot = getSlot(SrcReg);
998      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
999      Stack[Slot] = DestReg;
1000      RegMap[DestReg] = Slot;
1001
1002    } else {
1003      // For FMOV we just duplicate the specified value to a new stack slot.
1004      // This could be made better, but would require substantial changes.
1005      duplicateToTop(SrcReg, DestReg, I);
1006    }
1007    }
1008    break;
1009  case TargetInstrInfo::INLINEASM: {
1010    // The inline asm MachineInstr currently only *uses* FP registers for the
1011    // 'f' constraint.  These should be turned into the current ST(x) register
1012    // in the machine instr.  Also, any kills should be explicitly popped after
1013    // the inline asm.
1014    unsigned Kills[7];
1015    unsigned NumKills = 0;
1016    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1017      MachineOperand &Op = MI->getOperand(i);
1018      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1019        continue;
1020      assert(Op.isUse() && "Only handle inline asm uses right now");
1021
1022      unsigned FPReg = getFPReg(Op);
1023      Op.setReg(getSTReg(FPReg));
1024
1025      // If we kill this operand, make sure to pop it from the stack after the
1026      // asm.  We just remember it for now, and pop them all off at the end in
1027      // a batch.
1028      if (Op.isKill())
1029        Kills[NumKills++] = FPReg;
1030    }
1031
1032    // If this asm kills any FP registers (is the last use of them) we must
1033    // explicitly emit pop instructions for them.  Do this now after the asm has
1034    // executed so that the ST(x) numbers are not off (which would happen if we
1035    // did this inline with operand rewriting).
1036    //
1037    // Note: this might be a non-optimal pop sequence.  We might be able to do
1038    // better by trying to pop in stack order or something.
1039    MachineBasicBlock::iterator InsertPt = MI;
1040    while (NumKills)
1041      freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1042
1043    // Don't delete the inline asm!
1044    return;
1045  }
1046
1047  case X86::RET:
1048  case X86::RETI:
1049    // If RET has an FP register use operand, pass the first one in ST(0) and
1050    // the second one in ST(1).
1051    if (isStackEmpty()) return;  // Quick check to see if any are possible.
1052
1053    // Find the register operands.
1054    unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1055
1056    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1057      MachineOperand &Op = MI->getOperand(i);
1058      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1059        continue;
1060      // FP Register uses must be kills unless there are two uses of the same
1061      // register, in which case only one will be a kill.
1062      assert(Op.isUse() &&
1063             (Op.isKill() ||                        // Marked kill.
1064              getFPReg(Op) == FirstFPRegOp ||       // Second instance.
1065              MI->killsRegister(Op.getReg())) &&    // Later use is marked kill.
1066             "Ret only defs operands, and values aren't live beyond it");
1067
1068      if (FirstFPRegOp == ~0U)
1069        FirstFPRegOp = getFPReg(Op);
1070      else {
1071        assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1072        SecondFPRegOp = getFPReg(Op);
1073      }
1074
1075      // Remove the operand so that later passes don't see it.
1076      MI->RemoveOperand(i);
1077      --i, --e;
1078    }
1079
1080    // There are only four possibilities here:
1081    // 1) we are returning a single FP value.  In this case, it has to be in
1082    //    ST(0) already, so just declare success by removing the value from the
1083    //    FP Stack.
1084    if (SecondFPRegOp == ~0U) {
1085      // Assert that the top of stack contains the right FP register.
1086      assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1087             "Top of stack not the right register for RET!");
1088
1089      // Ok, everything is good, mark the value as not being on the stack
1090      // anymore so that our assertion about the stack being empty at end of
1091      // block doesn't fire.
1092      StackTop = 0;
1093      return;
1094    }
1095
1096    // Otherwise, we are returning two values:
1097    // 2) If returning the same value for both, we only have one thing in the FP
1098    //    stack.  Consider:  RET FP1, FP1
1099    if (StackTop == 1) {
1100      assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1101             "Stack misconfiguration for RET!");
1102
1103      // Duplicate the TOS so that we return it twice.  Just pick some other FPx
1104      // register to hold it.
1105      unsigned NewReg = (FirstFPRegOp+1)%7;
1106      duplicateToTop(FirstFPRegOp, NewReg, MI);
1107      FirstFPRegOp = NewReg;
1108    }
1109
1110    /// Okay we know we have two different FPx operands now:
1111    assert(StackTop == 2 && "Must have two values live!");
1112
1113    /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1114    ///    in ST(1).  In this case, emit an fxch.
1115    if (getStackEntry(0) == SecondFPRegOp) {
1116      assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1117      moveToTop(FirstFPRegOp, MI);
1118    }
1119
1120    /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1121    /// ST(1).  Just remove both from our understanding of the stack and return.
1122    assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1123    assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1124    StackTop = 0;
1125    return;
1126  }
1127
1128  I = MBB->erase(I);  // Remove the pseudo instruction
1129  --I;
1130}
1131