X86MCInstLower.cpp revision 3f40b31256b995e05edad1846e8d6c758df09ed8
1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains code to lower X86 MachineInstrs to their corresponding 11// MCInst records. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86MCInstLower.h" 16#include "X86AsmPrinter.h" 17#include "X86COFFMachineModuleInfo.h" 18#include "X86MCAsmInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/MachineModuleInfoImpls.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCExpr.h" 23#include "llvm/MC/MCInst.h" 24#include "llvm/MC/MCStreamer.h" 25#include "llvm/MC/MCSymbol.h" 26#include "llvm/Target/Mangler.h" 27#include "llvm/Support/FormattedStream.h" 28#include "llvm/ADT/SmallString.h" 29#include "llvm/Type.h" 30using namespace llvm; 31 32 33const X86Subtarget &X86MCInstLower::getSubtarget() const { 34 return AsmPrinter.getSubtarget(); 35} 36 37MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 38 assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin"); 39 return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>(); 40} 41 42 43MCSymbol *X86MCInstLower::GetPICBaseSymbol() const { 44 const TargetLowering *TLI = AsmPrinter.TM.getTargetLowering(); 45 return static_cast<const X86TargetLowering*>(TLI)-> 46 getPICBaseSymbol(AsmPrinter.MF, Ctx); 47} 48 49/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 50/// operand to an MCSymbol. 51MCSymbol *X86MCInstLower:: 52GetSymbolFromOperand(const MachineOperand &MO) const { 53 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference"); 54 55 SmallString<128> Name; 56 57 if (!MO.isGlobal()) { 58 assert(MO.isSymbol()); 59 Name += AsmPrinter.MAI->getGlobalPrefix(); 60 Name += MO.getSymbolName(); 61 } else { 62 const GlobalValue *GV = MO.getGlobal(); 63 bool isImplicitlyPrivate = false; 64 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB || 65 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY || 66 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE || 67 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE) 68 isImplicitlyPrivate = true; 69 70 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate); 71 } 72 73 // If the target flags on the operand changes the name of the symbol, do that 74 // before we return the symbol. 75 switch (MO.getTargetFlags()) { 76 default: break; 77 case X86II::MO_DLLIMPORT: { 78 // Handle dllimport linkage. 79 const char *Prefix = "__imp_"; 80 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix)); 81 break; 82 } 83 case X86II::MO_DARWIN_NONLAZY: 84 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 85 Name += "$non_lazy_ptr"; 86 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 87 88 MachineModuleInfoImpl::StubValueTy &StubSym = 89 getMachOMMI().getGVStubEntry(Sym); 90 if (StubSym.getPointer() == 0) { 91 assert(MO.isGlobal() && "Extern symbol not handled yet"); 92 StubSym = 93 MachineModuleInfoImpl:: 94 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()), 95 !MO.getGlobal()->hasInternalLinkage()); 96 } 97 return Sym; 98 } 99 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: { 100 Name += "$non_lazy_ptr"; 101 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 102 MachineModuleInfoImpl::StubValueTy &StubSym = 103 getMachOMMI().getHiddenGVStubEntry(Sym); 104 if (StubSym.getPointer() == 0) { 105 assert(MO.isGlobal() && "Extern symbol not handled yet"); 106 StubSym = 107 MachineModuleInfoImpl:: 108 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()), 109 !MO.getGlobal()->hasInternalLinkage()); 110 } 111 return Sym; 112 } 113 case X86II::MO_DARWIN_STUB: { 114 Name += "$stub"; 115 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 116 MachineModuleInfoImpl::StubValueTy &StubSym = 117 getMachOMMI().getFnStubEntry(Sym); 118 if (StubSym.getPointer()) 119 return Sym; 120 121 if (MO.isGlobal()) { 122 StubSym = 123 MachineModuleInfoImpl:: 124 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()), 125 !MO.getGlobal()->hasInternalLinkage()); 126 } else { 127 Name.erase(Name.end()-5, Name.end()); 128 StubSym = 129 MachineModuleInfoImpl:: 130 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false); 131 } 132 return Sym; 133 } 134 } 135 136 return Ctx.GetOrCreateSymbol(Name.str()); 137} 138 139MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 140 MCSymbol *Sym) const { 141 // FIXME: We would like an efficient form for this, so we don't have to do a 142 // lot of extra uniquing. 143 const MCExpr *Expr = 0; 144 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 145 146 switch (MO.getTargetFlags()) { 147 default: llvm_unreachable("Unknown target flag on GV operand"); 148 case X86II::MO_NO_FLAG: // No flag. 149 // These affect the name of the symbol, not any suffix. 150 case X86II::MO_DARWIN_NONLAZY: 151 case X86II::MO_DLLIMPORT: 152 case X86II::MO_DARWIN_STUB: 153 break; 154 155 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 156 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 157 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 158 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 159 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 160 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 161 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 162 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 163 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 164 case X86II::MO_PIC_BASE_OFFSET: 165 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 166 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 167 Expr = MCSymbolRefExpr::Create(Sym, Ctx); 168 // Subtract the pic base. 169 Expr = MCBinaryExpr::CreateSub(Expr, 170 MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx), 171 Ctx); 172 if (MO.isJTI() && AsmPrinter.MAI->hasSetDirective()) { 173 // If .set directive is supported, use it to reduce the number of 174 // relocations the assembler will generate for differences between 175 // local labels. This is only safe when the symbols are in the same 176 // section so we are restricting it to jumptable references. 177 MCSymbol *Label = Ctx.CreateTempSymbol(); 178 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr); 179 Expr = MCSymbolRefExpr::Create(Label, Ctx); 180 } 181 break; 182 } 183 184 if (Expr == 0) 185 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); 186 187 if (!MO.isJTI() && MO.getOffset()) 188 Expr = MCBinaryExpr::CreateAdd(Expr, 189 MCConstantExpr::Create(MO.getOffset(), Ctx), 190 Ctx); 191 return MCOperand::CreateExpr(Expr); 192} 193 194 195 196static void lower_subreg32(MCInst *MI, unsigned OpNo) { 197 // Convert registers in the addr mode according to subreg32. 198 unsigned Reg = MI->getOperand(OpNo).getReg(); 199 if (Reg != 0) 200 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32)); 201} 202 203static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) { 204 // Convert registers in the addr mode according to subreg64. 205 for (unsigned i = 0; i != 4; ++i) { 206 if (!MI->getOperand(OpNo+i).isReg()) continue; 207 208 unsigned Reg = MI->getOperand(OpNo+i).getReg(); 209 if (Reg == 0) continue; 210 211 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); 212 } 213} 214 215/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8. 216static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { 217 OutMI.setOpcode(NewOpc); 218 lower_subreg32(&OutMI, 0); 219} 220/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R 221static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { 222 OutMI.setOpcode(NewOpc); 223 OutMI.addOperand(OutMI.getOperand(0)); 224 OutMI.addOperand(OutMI.getOperand(0)); 225} 226 227/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 228/// a short fixed-register form. 229static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 230 unsigned ImmOp = Inst.getNumOperands() - 1; 231 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() && 232 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 233 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 234 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 235 236 // Check whether the destination register can be fixed. 237 unsigned Reg = Inst.getOperand(0).getReg(); 238 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 239 return; 240 241 // If so, rewrite the instruction. 242 MCInst New; 243 New.setOpcode(Opcode); 244 New.addOperand(Inst.getOperand(ImmOp)); 245 Inst = New; 246} 247 248void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 249 OutMI.setOpcode(MI->getOpcode()); 250 251 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 252 const MachineOperand &MO = MI->getOperand(i); 253 254 MCOperand MCOp; 255 switch (MO.getType()) { 256 default: 257 MI->dump(); 258 llvm_unreachable("unknown operand type"); 259 case MachineOperand::MO_Register: 260 // Ignore all implicit register operands. 261 if (MO.isImplicit()) continue; 262 MCOp = MCOperand::CreateReg(MO.getReg()); 263 break; 264 case MachineOperand::MO_Immediate: 265 MCOp = MCOperand::CreateImm(MO.getImm()); 266 break; 267 case MachineOperand::MO_MachineBasicBlock: 268 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( 269 MO.getMBB()->getSymbol(), Ctx)); 270 break; 271 case MachineOperand::MO_GlobalAddress: 272 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 273 break; 274 case MachineOperand::MO_ExternalSymbol: 275 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 276 break; 277 case MachineOperand::MO_JumpTableIndex: 278 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 279 break; 280 case MachineOperand::MO_ConstantPoolIndex: 281 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 282 break; 283 case MachineOperand::MO_BlockAddress: 284 MCOp = LowerSymbolOperand(MO, 285 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 286 break; 287 } 288 289 OutMI.addOperand(MCOp); 290 } 291 292 // Handle a few special cases to eliminate operand modifiers. 293 switch (OutMI.getOpcode()) { 294 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand. 295 lower_lea64_32mem(&OutMI, 1); 296 break; 297 case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break; 298 case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; 299 case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break; 300 case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break; 301 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; 302 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break; 303 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break; 304 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break; 305 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; 306 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break; 307 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break; 308 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break; 309 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break; 310 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break; 311 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break; 312 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break; 313 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; 314 case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break; 315 case X86::MMX_V_SETALLONES: 316 LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break; 317 case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break; 318 case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break; 319 case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break; 320 case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break; 321 case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break; 322 case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break; 323 324 case X86::MOV16r0: 325 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0 326 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr 327 break; 328 case X86::MOV64r0: 329 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0 330 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr 331 break; 332 333 334 // The assembler backend wants to see branches in their small form and relax 335 // them to their large form. The JIT can only handle the large form because 336 // it does not do relaxation. For now, translate the large form to the 337 // small one here. 338 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; 339 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; 340 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; 341 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; 342 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; 343 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; 344 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; 345 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; 346 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; 347 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; 348 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; 349 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; 350 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; 351 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; 352 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; 353 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; 354 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; 355 356 // We don't currently select the correct instruction form for instructions 357 // which have a short %eax, etc. form. Handle this by custom lowering, for 358 // now. 359 // 360 // Note, we are currently not handling the following instructions: 361 // MOV8ao8, MOV8o8a 362 // MOV16ao16, MOV16o16a 363 // MOV32ao32, MOV32o32a 364 // MOV64ao64, MOV64ao8 365 // MOV64o64a, MOV64o8a 366 // XCHG16ar, XCHG32ar, XCHG64ar 367 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; 368 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; 369 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; 370 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; 371 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; 372 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; 373 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; 374 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; 375 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; 376 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; 377 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; 378 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; 379 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; 380 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; 381 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; 382 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; 383 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; 384 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; 385 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; 386 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; 387 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; 388 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; 389 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; 390 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; 391 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; 392 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; 393 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; 394 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; 395 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; 396 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; 397 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; 398 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; 399 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; 400 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; 401 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; 402 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; 403 } 404} 405 406void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 407 raw_ostream &O) { 408 // Only the target-dependent form of DBG_VALUE should get here. 409 // Referencing the offset and metadata as NOps-2 and NOps-1 is 410 // probably portable to other targets; frame pointer location is not. 411 unsigned NOps = MI->getNumOperands(); 412 assert(NOps==7); 413 O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; 414 // cast away const; DIetc do not take const operands for some reason. 415 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata())); 416 if (V.getContext().isSubprogram()) 417 O << DISubprogram(V.getContext()).getDisplayName() << ":"; 418 O << V.getName(); 419 O << " <- "; 420 // Frame address. Currently handles register +- offset only. 421 assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); 422 O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); 423 O << ']'; 424 O << "+"; 425 printOperand(MI, NOps-2, O); 426} 427 428MachineLocation 429X86AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const { 430 MachineLocation Location; 431 assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!"); 432 // Frame address. Currently handles register +- offset only. 433 assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); 434 Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); 435 return Location; 436} 437 438 439void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 440 X86MCInstLower MCInstLowering(OutContext, Mang, *this); 441 switch (MI->getOpcode()) { 442 case TargetOpcode::DBG_VALUE: 443 if (isVerbose() && OutStreamer.hasRawTextSupport()) { 444 std::string TmpStr; 445 raw_string_ostream OS(TmpStr); 446 PrintDebugValueComment(MI, OS); 447 OutStreamer.EmitRawText(StringRef(OS.str())); 448 } 449 return; 450 451 case X86::MOVPC32r: { 452 MCInst TmpInst; 453 // This is a pseudo op for a two instruction sequence with a label, which 454 // looks like: 455 // call "L1$pb" 456 // "L1$pb": 457 // popl %esi 458 459 // Emit the call. 460 MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol(); 461 TmpInst.setOpcode(X86::CALLpcrel32); 462 // FIXME: We would like an efficient form for this, so we don't have to do a 463 // lot of extra uniquing. 464 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase, 465 OutContext))); 466 OutStreamer.EmitInstruction(TmpInst); 467 468 // Emit the label. 469 OutStreamer.EmitLabel(PICBase); 470 471 // popl $reg 472 TmpInst.setOpcode(X86::POP32r); 473 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); 474 OutStreamer.EmitInstruction(TmpInst); 475 return; 476 } 477 478 case X86::ADD32ri: { 479 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 480 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 481 break; 482 483 // Okay, we have something like: 484 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 485 486 // For this, we want to print something like: 487 // MYGLOBAL + (. - PICBASE) 488 // However, we can't generate a ".", so just emit a new label here and refer 489 // to it. 490 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 491 OutStreamer.EmitLabel(DotSym); 492 493 // Now that we have emitted the label, lower the complex operand expression. 494 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 495 496 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 497 const MCExpr *PICBase = 498 MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext); 499 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); 500 501 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), 502 DotExpr, OutContext); 503 504 MCInst TmpInst; 505 TmpInst.setOpcode(X86::ADD32ri); 506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 507 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 508 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr)); 509 OutStreamer.EmitInstruction(TmpInst); 510 return; 511 } 512 } 513 514 MCInst TmpInst; 515 MCInstLowering.Lower(MI, TmpInst); 516 517 OutStreamer.EmitInstruction(TmpInst); 518} 519 520