X86RegisterInfo.cpp revision 21b5541814d57d0a31f353948e4e933dbb1af6a4 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/Target/TargetAsmInfo.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/Compiler.h"
41using namespace llvm;
42
43X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44                                 const TargetInstrInfo &tii)
45  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46                         X86::ADJCALLSTACKDOWN64 :
47                         X86::ADJCALLSTACKDOWN32,
48                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
49                         X86::ADJCALLSTACKUP64 :
50                         X86::ADJCALLSTACKUP32),
51    TM(tm), TII(tii) {
52  // Cache some information.
53  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54  Is64Bit = Subtarget->is64Bit();
55  IsWin64 = Subtarget->isTargetWin64();
56  StackAlign = TM.getFrameInfo()->getStackAlignment();
57  if (Is64Bit) {
58    SlotSize = 8;
59    StackPtr = X86::RSP;
60    FramePtr = X86::RBP;
61  } else {
62    SlotSize = 4;
63    StackPtr = X86::ESP;
64    FramePtr = X86::EBP;
65  }
66}
67
68// getDwarfRegNum - This function maps LLVM register identifiers to the
69// Dwarf specific numbering, used in debug info and exception tables.
70
71int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73  unsigned Flavour = DWARFFlavour::X86_64;
74  if (!Subtarget->is64Bit()) {
75    if (Subtarget->isTargetDarwin()) {
76      if (isEH)
77        Flavour = DWARFFlavour::X86_32_DarwinEH;
78      else
79        Flavour = DWARFFlavour::X86_32_Generic;
80    } else if (Subtarget->isTargetCygMing()) {
81      // Unsupported by now, just quick fallback
82      Flavour = DWARFFlavour::X86_32_Generic;
83    } else {
84      Flavour = DWARFFlavour::X86_32_Generic;
85    }
86  }
87
88  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
89}
90
91// getX86RegNum - This function maps LLVM register identifiers to their X86
92// specific numbering, which is used in various places encoding instructions.
93//
94unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
95  switch(RegNo) {
96  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
101    return N86::ESP;
102  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
103    return N86::EBP;
104  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
105    return N86::ESI;
106  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
107    return N86::EDI;
108
109  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
110    return N86::EAX;
111  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
112    return N86::ECX;
113  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
114    return N86::EDX;
115  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
116    return N86::EBX;
117  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
118    return N86::ESP;
119  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
120    return N86::EBP;
121  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
122    return N86::ESI;
123  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
124    return N86::EDI;
125
126  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128    return RegNo-X86::ST0;
129
130  case X86::XMM0: case X86::XMM8: case X86::MM0:
131    return 0;
132  case X86::XMM1: case X86::XMM9: case X86::MM1:
133    return 1;
134  case X86::XMM2: case X86::XMM10: case X86::MM2:
135    return 2;
136  case X86::XMM3: case X86::XMM11: case X86::MM3:
137    return 3;
138  case X86::XMM4: case X86::XMM12: case X86::MM4:
139    return 4;
140  case X86::XMM5: case X86::XMM13: case X86::MM5:
141    return 5;
142  case X86::XMM6: case X86::XMM14: case X86::MM6:
143    return 6;
144  case X86::XMM7: case X86::XMM15: case X86::MM7:
145    return 7;
146
147  default:
148    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
150    return 0;
151  }
152}
153
154const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
155  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
156  if (Subtarget->is64Bit())
157    return &X86::GR64RegClass;
158  else
159    return &X86::GR32RegClass;
160}
161
162const TargetRegisterClass *
163X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
164  if (RC == &X86::CCRRegClass) {
165    if (Is64Bit)
166      return &X86::GR64RegClass;
167    else
168      return &X86::GR32RegClass;
169  }
170  return NULL;
171}
172
173const unsigned *
174X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
175  bool callsEHReturn = false;
176
177  if (MF) {
178    const MachineFrameInfo *MFI = MF->getFrameInfo();
179    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
180    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
181  }
182
183  static const unsigned CalleeSavedRegs32Bit[] = {
184    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
185  };
186
187  static const unsigned CalleeSavedRegs32EHRet[] = {
188    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
189  };
190
191  static const unsigned CalleeSavedRegs64Bit[] = {
192    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
193  };
194
195  static const unsigned CalleeSavedRegs64EHRet[] = {
196    X86::RAX, X86::RDX, X86::RBX, X86::R12,
197    X86::R13, X86::R14, X86::R15, X86::RBP, 0
198  };
199
200  static const unsigned CalleeSavedRegsWin64[] = {
201    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
202    X86::R12,   X86::R13,   X86::R14,   X86::R15,
203    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
204    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
205    X86::XMM14, X86::XMM15, 0
206  };
207
208  if (Is64Bit) {
209    if (IsWin64)
210      return CalleeSavedRegsWin64;
211    else
212      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
213  } else {
214    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
215  }
216}
217
218const TargetRegisterClass* const*
219X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
220  bool callsEHReturn = false;
221
222  if (MF) {
223    const MachineFrameInfo *MFI = MF->getFrameInfo();
224    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
226  }
227
228  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
229    &X86::GR32RegClass, &X86::GR32RegClass,
230    &X86::GR32RegClass, &X86::GR32RegClass,  0
231  };
232  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
233    &X86::GR32RegClass, &X86::GR32RegClass,
234    &X86::GR32RegClass, &X86::GR32RegClass,
235    &X86::GR32RegClass, &X86::GR32RegClass,  0
236  };
237  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
238    &X86::GR64RegClass, &X86::GR64RegClass,
239    &X86::GR64RegClass, &X86::GR64RegClass,
240    &X86::GR64RegClass, &X86::GR64RegClass, 0
241  };
242  static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
243    &X86::GR64RegClass, &X86::GR64RegClass,
244    &X86::GR64RegClass, &X86::GR64RegClass,
245    &X86::GR64RegClass, &X86::GR64RegClass,
246    &X86::GR64RegClass, &X86::GR64RegClass, 0
247  };
248  static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
249    &X86::GR64RegClass,  &X86::GR64RegClass,
250    &X86::GR64RegClass,  &X86::GR64RegClass,
251    &X86::GR64RegClass,  &X86::GR64RegClass,
252    &X86::GR64RegClass,  &X86::GR64RegClass,
253    &X86::VR128RegClass, &X86::VR128RegClass,
254    &X86::VR128RegClass, &X86::VR128RegClass,
255    &X86::VR128RegClass, &X86::VR128RegClass,
256    &X86::VR128RegClass, &X86::VR128RegClass,
257    &X86::VR128RegClass, &X86::VR128RegClass, 0
258  };
259
260  if (Is64Bit) {
261    if (IsWin64)
262      return CalleeSavedRegClassesWin64;
263    else
264      return (callsEHReturn ?
265              CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
266  } else {
267    return (callsEHReturn ?
268            CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
269  }
270}
271
272BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273  BitVector Reserved(getNumRegs());
274  // Set the stack-pointer register and its aliases as reserved.
275  Reserved.set(X86::RSP);
276  Reserved.set(X86::ESP);
277  Reserved.set(X86::SP);
278  Reserved.set(X86::SPL);
279  // Set the frame-pointer register and its aliases as reserved if needed.
280  if (hasFP(MF)) {
281    Reserved.set(X86::RBP);
282    Reserved.set(X86::EBP);
283    Reserved.set(X86::BP);
284    Reserved.set(X86::BPL);
285  }
286  // Mark the x87 stack registers as reserved, since they don't
287  // behave normally with respect to liveness. We don't fully
288  // model the effects of x87 stack pushes and pops after
289  // stackification.
290  Reserved.set(X86::ST0);
291  Reserved.set(X86::ST1);
292  Reserved.set(X86::ST2);
293  Reserved.set(X86::ST3);
294  Reserved.set(X86::ST4);
295  Reserved.set(X86::ST5);
296  Reserved.set(X86::ST6);
297  Reserved.set(X86::ST7);
298  return Reserved;
299}
300
301//===----------------------------------------------------------------------===//
302// Stack Frame Processing methods
303//===----------------------------------------------------------------------===//
304
305static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
306  unsigned MaxAlign = 0;
307  for (int i = FFI->getObjectIndexBegin(),
308         e = FFI->getObjectIndexEnd(); i != e; ++i) {
309    if (FFI->isDeadObjectIndex(i))
310      continue;
311    unsigned Align = FFI->getObjectAlignment(i);
312    MaxAlign = std::max(MaxAlign, Align);
313  }
314
315  return MaxAlign;
316}
317
318// hasFP - Return true if the specified function should have a dedicated frame
319// pointer register.  This is true if the function has variable sized allocas or
320// if frame pointer elimination is disabled.
321//
322bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
323  const MachineFrameInfo *MFI = MF.getFrameInfo();
324  const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
325
326  return (NoFramePointerElim ||
327          needsStackRealignment(MF) ||
328          MFI->hasVarSizedObjects() ||
329          MFI->isFrameAddressTaken() ||
330          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
331          (MMI && MMI->callsUnwindInit()));
332}
333
334bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
335  const MachineFrameInfo *MFI = MF.getFrameInfo();;
336
337  // FIXME: Currently we don't support stack realignment for functions with
338  // variable-sized allocas
339  return (RealignStack &&
340          (MFI->getMaxAlignment() > StackAlign &&
341           !MFI->hasVarSizedObjects()));
342}
343
344bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
345  return !MF.getFrameInfo()->hasVarSizedObjects();
346}
347
348int
349X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
350  int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
351  uint64_t StackSize = MF.getFrameInfo()->getStackSize();
352
353  if (needsStackRealignment(MF)) {
354    if (FI < 0)
355      // Skip the saved EBP
356      Offset += SlotSize;
357    else {
358      unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
359      assert( (-(Offset + StackSize)) % Align == 0);
360      Align = 0;
361      return Offset + StackSize;
362    }
363
364    // FIXME: Support tail calls
365  } else {
366    if (!hasFP(MF))
367      return Offset + StackSize;
368
369    // Skip the saved EBP
370    Offset += SlotSize;
371
372    // Skip the RETADDR move area
373    X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
374    int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
375    if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
376  }
377
378  return Offset;
379}
380
381void X86RegisterInfo::
382eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
383                              MachineBasicBlock::iterator I) const {
384  if (!hasReservedCallFrame(MF)) {
385    // If the stack pointer can be changed after prologue, turn the
386    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
387    // adjcallstackdown instruction into 'add ESP, <amt>'
388    // TODO: consider using push / pop instead of sub + store / add
389    MachineInstr *Old = I;
390    uint64_t Amount = Old->getOperand(0).getImm();
391    if (Amount != 0) {
392      // We need to keep the stack aligned properly.  To do this, we round the
393      // amount of space needed for the outgoing arguments up to the next
394      // alignment boundary.
395      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
396
397      MachineInstr *New = 0;
398      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
399        New = BuildMI(MF, Old->getDebugLoc(),
400                      TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
401                      StackPtr).addReg(StackPtr).addImm(Amount);
402      } else {
403        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
404        // factor out the amount the callee already popped.
405        uint64_t CalleeAmt = Old->getOperand(1).getImm();
406        Amount -= CalleeAmt;
407        if (Amount) {
408          unsigned Opc = (Amount < 128) ?
409            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
410            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
411          New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
412            .addReg(StackPtr).addImm(Amount);
413        }
414      }
415
416      if (New) {
417        // The EFLAGS implicit def is dead.
418        New->getOperand(3).setIsDead();
419
420        // Replace the pseudo instruction with a new instruction...
421        MBB.insert(I, New);
422      }
423    }
424  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
425    // If we are performing frame pointer elimination and if the callee pops
426    // something off the stack pointer, add it back.  We do this until we have
427    // more advanced stack pointer tracking ability.
428    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
429      unsigned Opc = (CalleeAmt < 128) ?
430        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
431        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
432      MachineInstr *Old = I;
433      MachineInstr *New =
434        BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
435                StackPtr).addReg(StackPtr).addImm(CalleeAmt);
436      // The EFLAGS implicit def is dead.
437      New->getOperand(3).setIsDead();
438
439      MBB.insert(I, New);
440    }
441  }
442
443  MBB.erase(I);
444}
445
446void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
447                                          int SPAdj, RegScavenger *RS) const{
448  assert(SPAdj == 0 && "Unexpected");
449
450  unsigned i = 0;
451  MachineInstr &MI = *II;
452  MachineFunction &MF = *MI.getParent()->getParent();
453  while (!MI.getOperand(i).isFI()) {
454    ++i;
455    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
456  }
457
458  int FrameIndex = MI.getOperand(i).getIndex();
459
460  unsigned BasePtr;
461  if (needsStackRealignment(MF))
462    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
463  else
464    BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
465
466  // This must be part of a four operand memory reference.  Replace the
467  // FrameIndex with base register with EBP.  Add an offset to the offset.
468  MI.getOperand(i).ChangeToRegister(BasePtr, false);
469
470  // Now add the frame object offset to the offset from EBP.
471  if (MI.getOperand(i+3).isImm()) {
472    // Offset is a 32-bit integer.
473    int Offset = getFrameIndexOffset(MF, FrameIndex) +
474      (int)(MI.getOperand(i+3).getImm());
475
476     MI.getOperand(i+3).ChangeToImmediate(Offset);
477  } else {
478    // Offset is symbolic. This is extremely rare.
479    uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
480                      (uint64_t)MI.getOperand(i+3).getOffset();
481    MI.getOperand(i+3).setOffset(Offset);
482  }
483}
484
485void
486X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
487                                                      RegScavenger *RS) const {
488  MachineFrameInfo *FFI = MF.getFrameInfo();
489
490  // Calculate and set max stack object alignment early, so we can decide
491  // whether we will need stack realignment (and thus FP).
492  unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
493                               calculateMaxStackAlignment(FFI));
494
495  FFI->setMaxAlignment(MaxAlign);
496}
497
498void
499X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
500  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
501  int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
502  if (TailCallReturnAddrDelta < 0) {
503    // create RETURNADDR area
504    //   arg
505    //   arg
506    //   RETADDR
507    //   { ...
508    //     RETADDR area
509    //     ...
510    //   }
511    //   [EBP]
512    MF.getFrameInfo()->
513      CreateFixedObject(-TailCallReturnAddrDelta,
514                        (-1*SlotSize)+TailCallReturnAddrDelta);
515  }
516  if (hasFP(MF)) {
517    assert((TailCallReturnAddrDelta <= 0) &&
518           "The Delta should always be zero or negative");
519    // Create a frame entry for the EBP register that must be saved.
520    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
521                                                        (int)SlotSize * -2+
522                                                       TailCallReturnAddrDelta);
523    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
524           "Slot for EBP register must be last in order to be found!");
525    FrameIdx = 0;
526  }
527}
528
529/// emitSPUpdate - Emit a series of instructions to increment / decrement the
530/// stack pointer by a constant value.
531static
532void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
533                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
534                  const TargetInstrInfo &TII) {
535  bool isSub = NumBytes < 0;
536  uint64_t Offset = isSub ? -NumBytes : NumBytes;
537  unsigned Opc = isSub
538    ? ((Offset < 128) ?
539       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
540       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
541    : ((Offset < 128) ?
542       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
543       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
544  uint64_t Chunk = (1LL << 31) - 1;
545
546  while (Offset) {
547    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
548    MachineInstr *MI =
549      BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
550    // The EFLAGS implicit def is dead.
551    MI->getOperand(3).setIsDead();
552    Offset -= ThisVal;
553  }
554}
555
556// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
557static
558void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
559                      unsigned StackPtr, uint64_t *NumBytes = NULL) {
560  if (MBBI == MBB.begin()) return;
561
562  MachineBasicBlock::iterator PI = prior(MBBI);
563  unsigned Opc = PI->getOpcode();
564  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
565       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
566      PI->getOperand(0).getReg() == StackPtr) {
567    if (NumBytes)
568      *NumBytes += PI->getOperand(2).getImm();
569    MBB.erase(PI);
570  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
571              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
572             PI->getOperand(0).getReg() == StackPtr) {
573    if (NumBytes)
574      *NumBytes -= PI->getOperand(2).getImm();
575    MBB.erase(PI);
576  }
577}
578
579// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
580static
581void mergeSPUpdatesDown(MachineBasicBlock &MBB,
582                        MachineBasicBlock::iterator &MBBI,
583                        unsigned StackPtr, uint64_t *NumBytes = NULL) {
584  return;
585
586  if (MBBI == MBB.end()) return;
587
588  MachineBasicBlock::iterator NI = next(MBBI);
589  if (NI == MBB.end()) return;
590
591  unsigned Opc = NI->getOpcode();
592  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
593       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
594      NI->getOperand(0).getReg() == StackPtr) {
595    if (NumBytes)
596      *NumBytes -= NI->getOperand(2).getImm();
597    MBB.erase(NI);
598    MBBI = NI;
599  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
600              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
601             NI->getOperand(0).getReg() == StackPtr) {
602    if (NumBytes)
603      *NumBytes += NI->getOperand(2).getImm();
604    MBB.erase(NI);
605    MBBI = NI;
606  }
607}
608
609/// mergeSPUpdates - Checks the instruction before/after the passed
610/// instruction. If it is an ADD/SUB instruction it is deleted
611/// argument and the stack adjustment is returned as a positive value for ADD
612/// and a negative for SUB.
613static int mergeSPUpdates(MachineBasicBlock &MBB,
614                           MachineBasicBlock::iterator &MBBI,
615                           unsigned StackPtr,
616                           bool doMergeWithPrevious) {
617
618  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
619      (!doMergeWithPrevious && MBBI == MBB.end()))
620    return 0;
621
622  int Offset = 0;
623
624  MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
625  MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
626  unsigned Opc = PI->getOpcode();
627  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
628       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
629      PI->getOperand(0).getReg() == StackPtr){
630    Offset += PI->getOperand(2).getImm();
631    MBB.erase(PI);
632    if (!doMergeWithPrevious) MBBI = NI;
633  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
634              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
635             PI->getOperand(0).getReg() == StackPtr) {
636    Offset -= PI->getOperand(2).getImm();
637    MBB.erase(PI);
638    if (!doMergeWithPrevious) MBBI = NI;
639  }
640
641  return Offset;
642}
643
644void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
645                                     unsigned FrameLabelId,
646                                     unsigned ReadyLabelId) const {
647  MachineFrameInfo *MFI = MF.getFrameInfo();
648  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
649  if (!MMI)
650    return;
651
652  uint64_t StackSize = MFI->getStackSize();
653  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
654  const TargetData *TD = MF.getTarget().getTargetData();
655
656  // Calculate amount of bytes used for return address storing
657  int stackGrowth =
658    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
659     TargetFrameInfo::StackGrowsUp ?
660     TD->getPointerSize() : -TD->getPointerSize());
661
662  if (StackSize) {
663    // Show update of SP.
664    if (hasFP(MF)) {
665      // Adjust SP
666      MachineLocation SPDst(MachineLocation::VirtualFP);
667      MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
668      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
669    } else {
670      MachineLocation SPDst(MachineLocation::VirtualFP);
671      MachineLocation SPSrc(MachineLocation::VirtualFP,
672                            -StackSize+stackGrowth);
673      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
674    }
675  } else {
676    //FIXME: Verify & implement for FP
677    MachineLocation SPDst(StackPtr);
678    MachineLocation SPSrc(StackPtr, stackGrowth);
679    Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
680  }
681
682  // Add callee saved registers to move list.
683  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
684
685  // FIXME: This is dirty hack. The code itself is pretty mess right now.
686  // It should be rewritten from scratch and generalized sometimes.
687
688  // Determine maximum offset (minumum due to stack growth)
689  int64_t MaxOffset = 0;
690  for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
691    MaxOffset = std::min(MaxOffset,
692                         MFI->getObjectOffset(CSI[I].getFrameIdx()));
693
694  // Calculate offsets
695  int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
696  for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
697    int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
698    unsigned Reg = CSI[I].getReg();
699    Offset = (MaxOffset-Offset+saveAreaOffset);
700    MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
701    MachineLocation CSSrc(Reg);
702    Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
703  }
704
705  if (hasFP(MF)) {
706    // Save FP
707    MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
708    MachineLocation FPSrc(FramePtr);
709    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
710  }
711
712  MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
713  MachineLocation FPSrc(MachineLocation::VirtualFP);
714  Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
715}
716
717
718void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
719  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
720  MachineFrameInfo *MFI = MF.getFrameInfo();
721  const Function* Fn = MF.getFunction();
722  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
723  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
724  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
725  MachineBasicBlock::iterator MBBI = MBB.begin();
726  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
727                          !Fn->doesNotThrow() ||
728                          UnwindTablesMandatory;
729  DebugLoc DL = DebugLoc::getUnknownLoc();
730  // Prepare for frame info.
731  unsigned FrameLabelId = 0;
732
733  // Get the number of bytes to allocate from the FrameInfo.
734  uint64_t StackSize = MFI->getStackSize();
735  // Get desired stack alignment
736  uint64_t MaxAlign  = MFI->getMaxAlignment();
737
738  // Add RETADDR move area to callee saved frame size.
739  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
740  if (TailCallReturnAddrDelta < 0)
741    X86FI->setCalleeSavedFrameSize(
742          X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
743
744  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
745  // function, and use up to 128 bytes of stack space, don't have a frame
746  // pointer, calls, or dynamic alloca then we do not need to adjust the
747  // stack pointer (we fit in the Red Zone).
748  if (Is64Bit && !DisableRedZone &&
749      !needsStackRealignment(MF) &&
750      !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
751      !MFI->hasCalls()) {                          // No calls.
752    uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
753    if (hasFP(MF)) MinSize += SlotSize;
754    StackSize = std::max(MinSize,
755                         StackSize > 128 ? StackSize - 128 : 0);
756    MFI->setStackSize(StackSize);
757  }
758
759  // Insert stack pointer adjustment for later moving of return addr.  Only
760  // applies to tail call optimized functions where the callee argument stack
761  // size is bigger than the callers.
762  if (TailCallReturnAddrDelta < 0) {
763    MachineInstr *MI =
764      BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
765              StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
766    // The EFLAGS implicit def is dead.
767    MI->getOperand(3).setIsDead();
768  }
769
770  uint64_t NumBytes = 0;
771  if (hasFP(MF)) {
772    // Calculate required stack adjustment
773    uint64_t FrameSize = StackSize - SlotSize;
774    if (needsStackRealignment(MF))
775      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
776
777    NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
778
779    // Get the offset of the stack slot for the EBP register... which is
780    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
781    // Update the frame offset adjustment.
782    MFI->setOffsetAdjustment(-NumBytes);
783
784    // Save EBP into the appropriate stack slot...
785    BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
786      .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
787
788    if (needsFrameMoves) {
789      // Mark effective beginning of when frame pointer becomes valid.
790      FrameLabelId = MMI->NextLabelID();
791      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
792    }
793
794    // Update EBP with the new base value...
795    BuildMI(MBB, MBBI, DL,
796            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
797        .addReg(StackPtr);
798
799    // Mark the FramePtr as live-in in every block except the entry.
800    for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
801         I != E; ++I)
802      I->addLiveIn(FramePtr);
803
804    // Realign stack
805    if (needsStackRealignment(MF)) {
806      MachineInstr *MI =
807        BuildMI(MBB, MBBI, DL,
808                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
809                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
810      // The EFLAGS implicit def is dead.
811      MI->getOperand(3).setIsDead();
812    }
813  } else
814    NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
815
816  unsigned ReadyLabelId = 0;
817  if (needsFrameMoves) {
818    // Mark effective beginning of when frame pointer is ready.
819    ReadyLabelId = MMI->NextLabelID();
820    BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
821  }
822
823  // Skip the callee-saved push instructions.
824  while (MBBI != MBB.end() &&
825         (MBBI->getOpcode() == X86::PUSH32r ||
826          MBBI->getOpcode() == X86::PUSH64r))
827    ++MBBI;
828
829  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
830    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
831      // Check, whether EAX is livein for this function
832      bool isEAXAlive = false;
833      for (MachineRegisterInfo::livein_iterator
834           II = MF.getRegInfo().livein_begin(),
835           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
836        unsigned Reg = II->first;
837        isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
838                      Reg == X86::AH || Reg == X86::AL);
839      }
840
841      // Function prologue calls _alloca to probe the stack when allocating
842      // more than 4k bytes in one go. Touching the stack at 4K increments is
843      // necessary to ensure that the guard pages used by the OS virtual memory
844      // manager are allocated in correct sequence.
845      if (!isEAXAlive) {
846        BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
847        BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
848          .addExternalSymbol("_alloca");
849      } else {
850        // Save EAX
851        BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
852          .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
853        // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
854        // allocated bytes for EAX.
855        BuildMI(MBB, MBBI, DL,
856                TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
857        BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
858          .addExternalSymbol("_alloca");
859        // Restore EAX
860        MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
861                                                X86::EAX),
862                                        StackPtr, false, NumBytes-4);
863        MBB.insert(MBBI, MI);
864      }
865    } else {
866      // If there is an SUB32ri of ESP immediately before this instruction,
867      // merge the two. This can be the case when tail call elimination is
868      // enabled and the callee has more arguments then the caller.
869      NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
870      // If there is an ADD32ri or SUB32ri of ESP immediately after this
871      // instruction, merge the two instructions.
872      mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
873
874      if (NumBytes)
875        emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
876    }
877  }
878
879  if (needsFrameMoves)
880    emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
881}
882
883void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
884                                   MachineBasicBlock &MBB) const {
885  const MachineFrameInfo *MFI = MF.getFrameInfo();
886  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
887  MachineBasicBlock::iterator MBBI = prior(MBB.end());
888  unsigned RetOpcode = MBBI->getOpcode();
889  DebugLoc DL = DebugLoc::getUnknownLoc();
890
891  switch (RetOpcode) {
892  case X86::RET:
893  case X86::RETI:
894  case X86::TCRETURNdi:
895  case X86::TCRETURNri:
896  case X86::TCRETURNri64:
897  case X86::TCRETURNdi64:
898  case X86::EH_RETURN:
899  case X86::EH_RETURN64:
900  case X86::TAILJMPd:
901  case X86::TAILJMPr:
902  case X86::TAILJMPm: break;  // These are ok
903  default:
904    assert(0 && "Can only insert epilog into returning blocks");
905  }
906
907  // Get the number of bytes to allocate from the FrameInfo
908  uint64_t StackSize = MFI->getStackSize();
909  uint64_t MaxAlign  = MFI->getMaxAlignment();
910  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
911  uint64_t NumBytes = 0;
912
913  if (hasFP(MF)) {
914    // Calculate required stack adjustment
915    uint64_t FrameSize = StackSize - SlotSize;
916    if (needsStackRealignment(MF))
917      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
918
919    NumBytes = FrameSize - CSSize;
920
921    // pop EBP.
922    BuildMI(MBB, MBBI, DL,
923            TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
924  } else
925    NumBytes = StackSize - CSSize;
926
927  // Skip the callee-saved pop instructions.
928  MachineBasicBlock::iterator LastCSPop = MBBI;
929  while (MBBI != MBB.begin()) {
930    MachineBasicBlock::iterator PI = prior(MBBI);
931    unsigned Opc = PI->getOpcode();
932    if (Opc != X86::POP32r && Opc != X86::POP64r &&
933        !PI->getDesc().isTerminator())
934      break;
935    --MBBI;
936  }
937
938  // If there is an ADD32ri or SUB32ri of ESP immediately before this
939  // instruction, merge the two instructions.
940  if (NumBytes || MFI->hasVarSizedObjects())
941    mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
942
943  // If dynamic alloca is used, then reset esp to point to the last callee-saved
944  // slot before popping them off! Same applies for the case, when stack was
945  // realigned
946  if (needsStackRealignment(MF)) {
947    // We cannot use LEA here, because stack pointer was realigned. We need to
948    // deallocate local frame back
949    if (CSSize) {
950      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
951      MBBI = prior(LastCSPop);
952    }
953
954    BuildMI(MBB, MBBI, DL,
955            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
956            StackPtr).addReg(FramePtr);
957  } else if (MFI->hasVarSizedObjects()) {
958    if (CSSize) {
959      unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
960      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
961                                      FramePtr, false, -CSSize);
962      MBB.insert(MBBI, MI);
963    } else
964      BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
965              StackPtr).addReg(FramePtr);
966
967  } else {
968    // adjust stack pointer back: ESP += numbytes
969    if (NumBytes)
970      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
971  }
972
973  // We're returning from function via eh_return.
974  if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
975    MBBI = prior(MBB.end());
976    MachineOperand &DestAddr  = MBBI->getOperand(0);
977    assert(DestAddr.isReg() && "Offset should be in register!");
978    BuildMI(MBB, MBBI, DL,
979            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
980            StackPtr).addReg(DestAddr.getReg());
981  // Tail call return: adjust the stack pointer and jump to callee
982  } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
983             RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
984    MBBI = prior(MBB.end());
985    MachineOperand &JumpTarget = MBBI->getOperand(0);
986    MachineOperand &StackAdjust = MBBI->getOperand(1);
987    assert(StackAdjust.isImm() && "Expecting immediate value.");
988
989    // Adjust stack pointer.
990    int StackAdj = StackAdjust.getImm();
991    int MaxTCDelta = X86FI->getTCReturnAddrDelta();
992    int Offset = 0;
993    assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
994    // Incoporate the retaddr area.
995    Offset = StackAdj-MaxTCDelta;
996    assert(Offset >= 0 && "Offset should never be negative");
997    if (Offset) {
998      // Check for possible merge with preceeding ADD instruction.
999      Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1000      emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1001    }
1002    // Jump to label or value in register.
1003    if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1004      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1005        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1006    else if (RetOpcode== X86::TCRETURNri64) {
1007      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1008    } else
1009       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1010    // Delete the pseudo instruction TCRETURN.
1011    MBB.erase(MBBI);
1012  } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1013             (X86FI->getTCReturnAddrDelta() < 0)) {
1014    // Add the return addr area delta back since we are not tail calling.
1015    int delta = -1*X86FI->getTCReturnAddrDelta();
1016    MBBI = prior(MBB.end());
1017    // Check for possible merge with preceeding ADD instruction.
1018    delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1019    emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1020  }
1021}
1022
1023unsigned X86RegisterInfo::getRARegister() const {
1024  if (Is64Bit)
1025    return X86::RIP;  // Should have dwarf #16
1026  else
1027    return X86::EIP;  // Should have dwarf #8
1028}
1029
1030unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1031  return hasFP(MF) ? FramePtr : StackPtr;
1032}
1033
1034void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1035                                                                         const {
1036  // Calculate amount of bytes used for return address storing
1037  int stackGrowth = (Is64Bit ? -8 : -4);
1038
1039  // Initial state of the frame pointer is esp+4.
1040  MachineLocation Dst(MachineLocation::VirtualFP);
1041  MachineLocation Src(StackPtr, stackGrowth);
1042  Moves.push_back(MachineMove(0, Dst, Src));
1043
1044  // Add return address to move list
1045  MachineLocation CSDst(StackPtr, stackGrowth);
1046  MachineLocation CSSrc(getRARegister());
1047  Moves.push_back(MachineMove(0, CSDst, CSSrc));
1048}
1049
1050unsigned X86RegisterInfo::getEHExceptionRegister() const {
1051  assert(0 && "What is the exception register");
1052  return 0;
1053}
1054
1055unsigned X86RegisterInfo::getEHHandlerRegister() const {
1056  assert(0 && "What is the exception handler register");
1057  return 0;
1058}
1059
1060namespace llvm {
1061unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1062  switch (VT.getSimpleVT()) {
1063  default: return Reg;
1064  case MVT::i8:
1065    if (High) {
1066      switch (Reg) {
1067      default: return 0;
1068      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1069        return X86::AH;
1070      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1071        return X86::DH;
1072      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1073        return X86::CH;
1074      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1075        return X86::BH;
1076      }
1077    } else {
1078      switch (Reg) {
1079      default: return 0;
1080      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1081        return X86::AL;
1082      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1083        return X86::DL;
1084      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1085        return X86::CL;
1086      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1087        return X86::BL;
1088      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1089        return X86::SIL;
1090      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1091        return X86::DIL;
1092      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1093        return X86::BPL;
1094      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1095        return X86::SPL;
1096      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1097        return X86::R8B;
1098      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1099        return X86::R9B;
1100      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1101        return X86::R10B;
1102      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1103        return X86::R11B;
1104      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1105        return X86::R12B;
1106      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1107        return X86::R13B;
1108      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1109        return X86::R14B;
1110      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1111        return X86::R15B;
1112      }
1113    }
1114  case MVT::i16:
1115    switch (Reg) {
1116    default: return Reg;
1117    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1118      return X86::AX;
1119    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1120      return X86::DX;
1121    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1122      return X86::CX;
1123    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1124      return X86::BX;
1125    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1126      return X86::SI;
1127    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1128      return X86::DI;
1129    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1130      return X86::BP;
1131    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1132      return X86::SP;
1133    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1134      return X86::R8W;
1135    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1136      return X86::R9W;
1137    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1138      return X86::R10W;
1139    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1140      return X86::R11W;
1141    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1142      return X86::R12W;
1143    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1144      return X86::R13W;
1145    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1146      return X86::R14W;
1147    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1148      return X86::R15W;
1149    }
1150  case MVT::i32:
1151    switch (Reg) {
1152    default: return Reg;
1153    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1154      return X86::EAX;
1155    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1156      return X86::EDX;
1157    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1158      return X86::ECX;
1159    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1160      return X86::EBX;
1161    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1162      return X86::ESI;
1163    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1164      return X86::EDI;
1165    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1166      return X86::EBP;
1167    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1168      return X86::ESP;
1169    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1170      return X86::R8D;
1171    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1172      return X86::R9D;
1173    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1174      return X86::R10D;
1175    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1176      return X86::R11D;
1177    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1178      return X86::R12D;
1179    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1180      return X86::R13D;
1181    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1182      return X86::R14D;
1183    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1184      return X86::R15D;
1185    }
1186  case MVT::i64:
1187    switch (Reg) {
1188    default: return Reg;
1189    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1190      return X86::RAX;
1191    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1192      return X86::RDX;
1193    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1194      return X86::RCX;
1195    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1196      return X86::RBX;
1197    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1198      return X86::RSI;
1199    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1200      return X86::RDI;
1201    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1202      return X86::RBP;
1203    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1204      return X86::RSP;
1205    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1206      return X86::R8;
1207    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1208      return X86::R9;
1209    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1210      return X86::R10;
1211    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1212      return X86::R11;
1213    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1214      return X86::R12;
1215    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1216      return X86::R13;
1217    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1218      return X86::R14;
1219    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1220      return X86::R15;
1221    }
1222  }
1223
1224  return Reg;
1225}
1226}
1227
1228#include "X86GenRegisterInfo.inc"
1229
1230namespace {
1231  struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1232    static char ID;
1233    MSAC() : MachineFunctionPass(&ID) {}
1234
1235    virtual bool runOnMachineFunction(MachineFunction &MF) {
1236      MachineFrameInfo *FFI = MF.getFrameInfo();
1237      MachineRegisterInfo &RI = MF.getRegInfo();
1238
1239      // Calculate max stack alignment of all already allocated stack objects.
1240      unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1241
1242      // Be over-conservative: scan over all vreg defs and find, whether vector
1243      // registers are used. If yes - there is probability, that vector register
1244      // will be spilled and thus stack needs to be aligned properly.
1245      for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1246           RegNum < RI.getLastVirtReg(); ++RegNum)
1247        MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1248
1249      FFI->setMaxAlignment(MaxAlign);
1250
1251      return false;
1252    }
1253
1254    virtual const char *getPassName() const {
1255      return "X86 Maximal Stack Alignment Calculator";
1256    }
1257  };
1258
1259  char MSAC::ID = 0;
1260}
1261
1262FunctionPass*
1263llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }
1264