X86RegisterInfo.cpp revision 50b3b50cd03f09f7fa87f48edaa72d519948ab63 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineLocation.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/ADT/STLExtras.h"
34#include <iostream>
35
36using namespace llvm;
37
38namespace {
39  cl::opt<bool>
40  NoFusing("disable-spill-fusing",
41           cl::desc("Disable fusing of spill code into instructions"));
42  cl::opt<bool>
43  PrintFailedFusing("print-failed-fuse-candidates",
44                    cl::desc("Print instructions that the allocator wants to"
45                             " fuse, but the X86 backend currently can't"),
46                    cl::Hidden);
47}
48
49X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
50                                 const TargetInstrInfo &tii)
51  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
52    TM(tm), TII(tii) {
53  // Cache some information.
54  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55  Is64Bit = Subtarget->is64Bit();
56  if (Is64Bit) {
57    SlotSize = 8;
58    StackPtr = X86::RSP;
59    FramePtr = X86::RBP;
60  } else {
61    SlotSize = 4;
62    StackPtr = X86::ESP;
63    FramePtr = X86::EBP;
64  }
65}
66
67void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
68                                          MachineBasicBlock::iterator MI,
69                                          unsigned SrcReg, int FrameIdx,
70                                          const TargetRegisterClass *RC) const {
71  unsigned Opc;
72  if (RC == &X86::GR64RegClass) {
73    Opc = X86::MOV64mr;
74  } else if (RC == &X86::GR32RegClass) {
75    Opc = X86::MOV32mr;
76  } else if (RC == &X86::GR16RegClass) {
77    Opc = X86::MOV16mr;
78  } else if (RC == &X86::GR8RegClass) {
79    Opc = X86::MOV8mr;
80  } else if (RC == &X86::GR32_RegClass) {
81    Opc = X86::MOV32_mr;
82  } else if (RC == &X86::GR16_RegClass) {
83    Opc = X86::MOV16_mr;
84  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
85    Opc = X86::FpST64m;
86  } else if (RC == &X86::FR32RegClass) {
87    Opc = X86::MOVSSmr;
88  } else if (RC == &X86::FR64RegClass) {
89    Opc = X86::MOVSDmr;
90  } else if (RC == &X86::VR128RegClass) {
91    Opc = X86::MOVAPSmr;
92  } else {
93    assert(0 && "Unknown regclass");
94    abort();
95  }
96  addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
97}
98
99void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
100                                           MachineBasicBlock::iterator MI,
101                                           unsigned DestReg, int FrameIdx,
102                                           const TargetRegisterClass *RC) const{
103  unsigned Opc;
104  if (RC == &X86::GR64RegClass) {
105    Opc = X86::MOV64rm;
106  } else if (RC == &X86::GR32RegClass) {
107    Opc = X86::MOV32rm;
108  } else if (RC == &X86::GR16RegClass) {
109    Opc = X86::MOV16rm;
110  } else if (RC == &X86::GR8RegClass) {
111    Opc = X86::MOV8rm;
112  } else if (RC == &X86::GR32_RegClass) {
113    Opc = X86::MOV32_rm;
114  } else if (RC == &X86::GR16_RegClass) {
115    Opc = X86::MOV16_rm;
116  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
117    Opc = X86::FpLD64m;
118  } else if (RC == &X86::FR32RegClass) {
119    Opc = X86::MOVSSrm;
120  } else if (RC == &X86::FR64RegClass) {
121    Opc = X86::MOVSDrm;
122  } else if (RC == &X86::VR128RegClass) {
123    Opc = X86::MOVAPSrm;
124  } else {
125    assert(0 && "Unknown regclass");
126    abort();
127  }
128  addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
129}
130
131void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
132                                   MachineBasicBlock::iterator MI,
133                                   unsigned DestReg, unsigned SrcReg,
134                                   const TargetRegisterClass *RC) const {
135  unsigned Opc;
136  if (RC == &X86::GR64RegClass) {
137    Opc = X86::MOV64rr;
138  } else if (RC == &X86::GR32RegClass) {
139    Opc = X86::MOV32rr;
140  } else if (RC == &X86::GR16RegClass) {
141    Opc = X86::MOV16rr;
142  } else if (RC == &X86::GR8RegClass) {
143    Opc = X86::MOV8rr;
144  } else if (RC == &X86::GR32_RegClass) {
145    Opc = X86::MOV32_rr;
146  } else if (RC == &X86::GR16_RegClass) {
147    Opc = X86::MOV16_rr;
148  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
149    Opc = X86::FpMOV;
150  } else if (RC == &X86::FR32RegClass) {
151    Opc = X86::FsMOVAPSrr;
152  } else if (RC == &X86::FR64RegClass) {
153    Opc = X86::FsMOVAPDrr;
154  } else if (RC == &X86::VR128RegClass) {
155    Opc = X86::MOVAPSrr;
156  } else {
157    assert(0 && "Unknown regclass");
158    abort();
159  }
160  BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
161}
162
163static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
164                                     MachineInstr *MI,
165                                     const TargetInstrInfo &TII) {
166  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
167  // Create the base instruction with the memory operand as the first part.
168  MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
169                                              FrameIndex);
170
171  // Loop over the rest of the ri operands, converting them over.
172  for (unsigned i = 0; i != NumOps; ++i) {
173    MachineOperand &MO = MI->getOperand(i+2);
174    if (MO.isReg())
175      MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
176    else if (MO.isImm())
177      MIB = MIB.addImm(MO.getImm());
178    else if (MO.isGlobalAddress())
179      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
180    else if (MO.isJumpTableIndex())
181      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
182    else
183      assert(0 && "Unknown operand type!");
184  }
185  return MIB;
186}
187
188static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
189                              unsigned FrameIndex, MachineInstr *MI,
190                              const TargetInstrInfo &TII) {
191  MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
192
193  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
194    MachineOperand &MO = MI->getOperand(i);
195    if (i == OpNo) {
196      assert(MO.isReg() && "Expected to fold into reg operand!");
197      MIB = addFrameReference(MIB, FrameIndex);
198    } else if (MO.isReg())
199      MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
200    else if (MO.isImm())
201      MIB = MIB.addImm(MO.getImm());
202    else if (MO.isGlobalAddress())
203      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
204    else if (MO.isJumpTableIndex())
205      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
206    else
207      assert(0 && "Unknown operand for FuseInst!");
208  }
209  return MIB;
210}
211
212static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
213                                MachineInstr *MI) {
214  return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
215}
216
217
218//===----------------------------------------------------------------------===//
219// Efficient Lookup Table Support
220//===----------------------------------------------------------------------===//
221
222namespace {
223  /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
224  ///
225  struct TableEntry {
226    unsigned from;                      // Original opcode.
227    unsigned to;                        // New opcode.
228
229    // less operators used by STL search.
230    bool operator<(const TableEntry &TE) const { return from < TE.from; }
231    friend bool operator<(const TableEntry &TE, unsigned V) {
232      return TE.from < V;
233    }
234    friend bool operator<(unsigned V, const TableEntry &TE) {
235      return V < TE.from;
236    }
237  };
238}
239
240/// TableIsSorted - Return true if the table is in 'from' opcode order.
241///
242static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
243  for (unsigned i = 1; i != NumEntries; ++i)
244    if (!(Table[i-1] < Table[i])) {
245      std::cerr << "Entries out of order " << Table[i-1].from
246                << " " << Table[i].from << "\n";
247      return false;
248    }
249  return true;
250}
251
252/// TableLookup - Return the table entry matching the specified opcode.
253/// Otherwise return NULL.
254static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
255                                unsigned Opcode) {
256  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
257  if (I != Table+N && I->from == Opcode)
258    return I;
259  return NULL;
260}
261
262#define ARRAY_SIZE(TABLE)  \
263   (sizeof(TABLE)/sizeof(TABLE[0]))
264
265#ifdef NDEBUG
266#define ASSERT_SORTED(TABLE)
267#else
268#define ASSERT_SORTED(TABLE)                                              \
269  { static bool TABLE##Checked = false;                                   \
270    if (!TABLE##Checked) {                                                \
271       assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
272              "All lookup tables must be sorted for efficient access!");  \
273       TABLE##Checked = true;                                             \
274    }                                                                     \
275  }
276#endif
277
278
279MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
280                                                 unsigned i,
281                                                 int FrameIndex) const {
282  // Check switch flag
283  if (NoFusing) return NULL;
284
285  // Table (and size) to search
286  const TableEntry *OpcodeTablePtr = NULL;
287  unsigned OpcodeTableSize = 0;
288  bool isTwoAddrFold = false;
289  unsigned NumOps = TII.getNumOperands(MI->getOpcode());
290  bool isTwoAddr = NumOps > 1 &&
291    TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1;
292
293  // Folding a memory location into the two-address part of a two-address
294  // instruction is different than folding it other places.  It requires
295  // replacing the *two* registers with the memory location.
296  if (isTwoAddr && NumOps >= 2 && i < 2 &&
297      MI->getOperand(0).isReg() &&
298      MI->getOperand(1).isReg() &&
299      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
300    static const TableEntry OpcodeTable[] = {
301      { X86::ADC32ri,     X86::ADC32mi },
302      { X86::ADC32ri8,    X86::ADC32mi8 },
303      { X86::ADC32rr,     X86::ADC32mr },
304      { X86::ADC64ri32,   X86::ADC64mi32 },
305      { X86::ADC64ri8,    X86::ADC64mi8 },
306      { X86::ADC64rr,     X86::ADC64mr },
307      { X86::ADD16ri,     X86::ADD16mi },
308      { X86::ADD16ri8,    X86::ADD16mi8 },
309      { X86::ADD16rr,     X86::ADD16mr },
310      { X86::ADD32ri,     X86::ADD32mi },
311      { X86::ADD32ri8,    X86::ADD32mi8 },
312      { X86::ADD32rr,     X86::ADD32mr },
313      { X86::ADD64ri32,   X86::ADD64mi32 },
314      { X86::ADD64ri8,    X86::ADD64mi8 },
315      { X86::ADD64rr,     X86::ADD64mr },
316      { X86::ADD8ri,      X86::ADD8mi },
317      { X86::ADD8rr,      X86::ADD8mr },
318      { X86::AND16ri,     X86::AND16mi },
319      { X86::AND16ri8,    X86::AND16mi8 },
320      { X86::AND16rr,     X86::AND16mr },
321      { X86::AND32ri,     X86::AND32mi },
322      { X86::AND32ri8,    X86::AND32mi8 },
323      { X86::AND32rr,     X86::AND32mr },
324      { X86::AND64ri32,   X86::AND64mi32 },
325      { X86::AND64ri8,    X86::AND64mi8 },
326      { X86::AND64rr,     X86::AND64mr },
327      { X86::AND8ri,      X86::AND8mi },
328      { X86::AND8rr,      X86::AND8mr },
329      { X86::DEC16r,      X86::DEC16m },
330      { X86::DEC32r,      X86::DEC32m },
331      { X86::DEC64_16r,   X86::DEC16m },
332      { X86::DEC64_32r,   X86::DEC32m },
333      { X86::DEC64r,      X86::DEC64m },
334      { X86::DEC8r,       X86::DEC8m },
335      { X86::INC16r,      X86::INC16m },
336      { X86::INC32r,      X86::INC32m },
337      { X86::INC64_16r,   X86::INC16m },
338      { X86::INC64_32r,   X86::INC32m },
339      { X86::INC64r,      X86::INC64m },
340      { X86::INC8r,       X86::INC8m },
341      { X86::NEG16r,      X86::NEG16m },
342      { X86::NEG32r,      X86::NEG32m },
343      { X86::NEG64r,      X86::NEG64m },
344      { X86::NEG8r,       X86::NEG8m },
345      { X86::NOT16r,      X86::NOT16m },
346      { X86::NOT32r,      X86::NOT32m },
347      { X86::NOT64r,      X86::NOT64m },
348      { X86::NOT8r,       X86::NOT8m },
349      { X86::OR16ri,      X86::OR16mi },
350      { X86::OR16ri8,     X86::OR16mi8 },
351      { X86::OR16rr,      X86::OR16mr },
352      { X86::OR32ri,      X86::OR32mi },
353      { X86::OR32ri8,     X86::OR32mi8 },
354      { X86::OR32rr,      X86::OR32mr },
355      { X86::OR64ri32,    X86::OR64mi32 },
356      { X86::OR64ri8,     X86::OR64mi8 },
357      { X86::OR64rr,      X86::OR64mr },
358      { X86::OR8ri,       X86::OR8mi },
359      { X86::OR8rr,       X86::OR8mr },
360      { X86::ROL16r1,     X86::ROL16m1 },
361      { X86::ROL16rCL,    X86::ROL16mCL },
362      { X86::ROL16ri,     X86::ROL16mi },
363      { X86::ROL32r1,     X86::ROL32m1 },
364      { X86::ROL32rCL,    X86::ROL32mCL },
365      { X86::ROL32ri,     X86::ROL32mi },
366      { X86::ROL64r1,     X86::ROL64m1 },
367      { X86::ROL64rCL,    X86::ROL64mCL },
368      { X86::ROL64ri,     X86::ROL64mi },
369      { X86::ROL8r1,      X86::ROL8m1 },
370      { X86::ROL8rCL,     X86::ROL8mCL },
371      { X86::ROL8ri,      X86::ROL8mi },
372      { X86::ROR16r1,     X86::ROR16m1 },
373      { X86::ROR16rCL,    X86::ROR16mCL },
374      { X86::ROR16ri,     X86::ROR16mi },
375      { X86::ROR32r1,     X86::ROR32m1 },
376      { X86::ROR32rCL,    X86::ROR32mCL },
377      { X86::ROR32ri,     X86::ROR32mi },
378      { X86::ROR64r1,     X86::ROR64m1 },
379      { X86::ROR64rCL,    X86::ROR64mCL },
380      { X86::ROR64ri,     X86::ROR64mi },
381      { X86::ROR8r1,      X86::ROR8m1 },
382      { X86::ROR8rCL,     X86::ROR8mCL },
383      { X86::ROR8ri,      X86::ROR8mi },
384      { X86::SAR16r1,     X86::SAR16m1 },
385      { X86::SAR16rCL,    X86::SAR16mCL },
386      { X86::SAR16ri,     X86::SAR16mi },
387      { X86::SAR32r1,     X86::SAR32m1 },
388      { X86::SAR32rCL,    X86::SAR32mCL },
389      { X86::SAR32ri,     X86::SAR32mi },
390      { X86::SAR64r1,     X86::SAR64m1 },
391      { X86::SAR64rCL,    X86::SAR64mCL },
392      { X86::SAR64ri,     X86::SAR64mi },
393      { X86::SAR8r1,      X86::SAR8m1 },
394      { X86::SAR8rCL,     X86::SAR8mCL },
395      { X86::SAR8ri,      X86::SAR8mi },
396      { X86::SBB32ri,     X86::SBB32mi },
397      { X86::SBB32ri8,    X86::SBB32mi8 },
398      { X86::SBB32rr,     X86::SBB32mr },
399      { X86::SBB64ri32,   X86::SBB64mi32 },
400      { X86::SBB64ri8,    X86::SBB64mi8 },
401      { X86::SBB64rr,     X86::SBB64mr },
402      { X86::SHL16r1,     X86::SHL16m1 },
403      { X86::SHL16rCL,    X86::SHL16mCL },
404      { X86::SHL16ri,     X86::SHL16mi },
405      { X86::SHL32r1,     X86::SHL32m1 },
406      { X86::SHL32rCL,    X86::SHL32mCL },
407      { X86::SHL32ri,     X86::SHL32mi },
408      { X86::SHL64r1,     X86::SHL64m1 },
409      { X86::SHL64rCL,    X86::SHL64mCL },
410      { X86::SHL64ri,     X86::SHL64mi },
411      { X86::SHL8r1,      X86::SHL8m1 },
412      { X86::SHL8rCL,     X86::SHL8mCL },
413      { X86::SHL8ri,      X86::SHL8mi },
414      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
415      { X86::SHLD16rri8,  X86::SHLD16mri8 },
416      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
417      { X86::SHLD32rri8,  X86::SHLD32mri8 },
418      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
419      { X86::SHLD64rri8,  X86::SHLD64mri8 },
420      { X86::SHR16r1,     X86::SHR16m1 },
421      { X86::SHR16rCL,    X86::SHR16mCL },
422      { X86::SHR16ri,     X86::SHR16mi },
423      { X86::SHR32r1,     X86::SHR32m1 },
424      { X86::SHR32rCL,    X86::SHR32mCL },
425      { X86::SHR32ri,     X86::SHR32mi },
426      { X86::SHR64r1,     X86::SHR64m1 },
427      { X86::SHR64rCL,    X86::SHR64mCL },
428      { X86::SHR64ri,     X86::SHR64mi },
429      { X86::SHR8r1,      X86::SHR8m1 },
430      { X86::SHR8rCL,     X86::SHR8mCL },
431      { X86::SHR8ri,      X86::SHR8mi },
432      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
433      { X86::SHRD16rri8,  X86::SHRD16mri8 },
434      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
435      { X86::SHRD32rri8,  X86::SHRD32mri8 },
436      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
437      { X86::SHRD64rri8,  X86::SHRD64mri8 },
438      { X86::SUB16ri,     X86::SUB16mi },
439      { X86::SUB16ri8,    X86::SUB16mi8 },
440      { X86::SUB16rr,     X86::SUB16mr },
441      { X86::SUB32ri,     X86::SUB32mi },
442      { X86::SUB32ri8,    X86::SUB32mi8 },
443      { X86::SUB32rr,     X86::SUB32mr },
444      { X86::SUB64ri32,   X86::SUB64mi32 },
445      { X86::SUB64ri8,    X86::SUB64mi8 },
446      { X86::SUB64rr,     X86::SUB64mr },
447      { X86::SUB8ri,      X86::SUB8mi },
448      { X86::SUB8rr,      X86::SUB8mr },
449      { X86::XOR16ri,     X86::XOR16mi },
450      { X86::XOR16ri8,    X86::XOR16mi8 },
451      { X86::XOR16rr,     X86::XOR16mr },
452      { X86::XOR32ri,     X86::XOR32mi },
453      { X86::XOR32ri8,    X86::XOR32mi8 },
454      { X86::XOR32rr,     X86::XOR32mr },
455      { X86::XOR64ri32,   X86::XOR64mi32 },
456      { X86::XOR64ri8,    X86::XOR64mi8 },
457      { X86::XOR64rr,     X86::XOR64mr },
458      { X86::XOR8ri,      X86::XOR8mi },
459      { X86::XOR8rr,      X86::XOR8mr }
460    };
461    ASSERT_SORTED(OpcodeTable);
462    OpcodeTablePtr = OpcodeTable;
463    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
464    isTwoAddrFold = true;
465  } else if (i == 0) { // If operand 0
466    if (MI->getOpcode() == X86::MOV16r0)
467      return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
468    else if (MI->getOpcode() == X86::MOV32r0)
469      return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
470    else if (MI->getOpcode() == X86::MOV64r0)
471      return MakeM0Inst(X86::MOV64mi32, FrameIndex, MI);
472    else if (MI->getOpcode() == X86::MOV8r0)
473      return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
474
475    static const TableEntry OpcodeTable[] = {
476      { X86::CMP16ri,     X86::CMP16mi },
477      { X86::CMP16ri8,    X86::CMP16mi8 },
478      { X86::CMP32ri,     X86::CMP32mi },
479      { X86::CMP32ri8,    X86::CMP32mi8 },
480      { X86::CMP8ri,      X86::CMP8mi },
481      { X86::DIV16r,      X86::DIV16m },
482      { X86::DIV32r,      X86::DIV32m },
483      { X86::DIV64r,      X86::DIV64m },
484      { X86::DIV8r,       X86::DIV8m },
485      { X86::FsMOVAPDrr,  X86::MOVSDmr },
486      { X86::FsMOVAPSrr,  X86::MOVSSmr },
487      { X86::IDIV16r,     X86::IDIV16m },
488      { X86::IDIV32r,     X86::IDIV32m },
489      { X86::IDIV64r,     X86::IDIV64m },
490      { X86::IDIV8r,      X86::IDIV8m },
491      { X86::IMUL16r,     X86::IMUL16m },
492      { X86::IMUL32r,     X86::IMUL32m },
493      { X86::IMUL64r,     X86::IMUL64m },
494      { X86::IMUL8r,      X86::IMUL8m },
495      { X86::MOV16ri,     X86::MOV16mi },
496      { X86::MOV16rr,     X86::MOV16mr },
497      { X86::MOV32ri,     X86::MOV32mi },
498      { X86::MOV32rr,     X86::MOV32mr },
499      { X86::MOV64ri32,   X86::MOV64mi32 },
500      { X86::MOV64rr,     X86::MOV64mr },
501      { X86::MOV8ri,      X86::MOV8mi },
502      { X86::MOV8rr,      X86::MOV8mr },
503      { X86::MOVAPDrr,    X86::MOVAPDmr },
504      { X86::MOVAPSrr,    X86::MOVAPSmr },
505      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
506      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
507      { X86::MOVSDrr,     X86::MOVSDmr },
508      { X86::MOVSSrr,     X86::MOVSSmr },
509      { X86::MOVUPDrr,    X86::MOVUPDmr },
510      { X86::MOVUPSrr,    X86::MOVUPSmr },
511      { X86::MUL16r,      X86::MUL16m },
512      { X86::MUL32r,      X86::MUL32m },
513      { X86::MUL64r,      X86::MUL64m },
514      { X86::MUL8r,       X86::MUL8m },
515      { X86::SETAEr,      X86::SETAEm },
516      { X86::SETAr,       X86::SETAm },
517      { X86::SETBEr,      X86::SETBEm },
518      { X86::SETBr,       X86::SETBm },
519      { X86::SETEr,       X86::SETEm },
520      { X86::SETGEr,      X86::SETGEm },
521      { X86::SETGr,       X86::SETGm },
522      { X86::SETLEr,      X86::SETLEm },
523      { X86::SETLr,       X86::SETLm },
524      { X86::SETNEr,      X86::SETNEm },
525      { X86::SETNPr,      X86::SETNPm },
526      { X86::SETNSr,      X86::SETNSm },
527      { X86::SETPr,       X86::SETPm },
528      { X86::SETSr,       X86::SETSm },
529      { X86::TEST16ri,    X86::TEST16mi },
530      { X86::TEST32ri,    X86::TEST32mi },
531      { X86::TEST64ri32,  X86::TEST64mi32 },
532      { X86::TEST8ri,     X86::TEST8mi },
533      { X86::XCHG16rr,    X86::XCHG16mr },
534      { X86::XCHG32rr,    X86::XCHG32mr },
535      { X86::XCHG64rr,    X86::XCHG64mr },
536      { X86::XCHG8rr,     X86::XCHG8mr }
537    };
538    ASSERT_SORTED(OpcodeTable);
539    OpcodeTablePtr = OpcodeTable;
540    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
541  } else if (i == 1) {
542    static const TableEntry OpcodeTable[] = {
543      { X86::CMP16rr,         X86::CMP16rm },
544      { X86::CMP32rr,         X86::CMP32rm },
545      { X86::CMP64ri32,       X86::CMP64mi32 },
546      { X86::CMP64ri8,        X86::CMP64mi8 },
547      { X86::CMP64rr,         X86::CMP64rm },
548      { X86::CMP8rr,          X86::CMP8rm },
549      { X86::CMPPDrri,        X86::CMPPDrmi },
550      { X86::CMPPSrri,        X86::CMPPSrmi },
551      { X86::CMPSDrr,         X86::CMPSDrm },
552      { X86::CMPSSrr,         X86::CMPSSrm },
553      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
554      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
555      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
556      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
557      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
558      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
559      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
560      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
561      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
562      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
563      { X86::FsMOVAPDrr,      X86::MOVSDrm },
564      { X86::FsMOVAPSrr,      X86::MOVSSrm },
565      { X86::IMUL16rri,       X86::IMUL16rmi },
566      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
567      { X86::IMUL32rri,       X86::IMUL32rmi },
568      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
569      { X86::IMUL64rr,        X86::IMUL64rm },
570      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
571      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
572      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
573      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
574      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
575      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
576      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
577      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
578      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
579      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
580      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
581      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
582      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
583      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
584      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
585      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
586      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
587      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
588      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
589      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
590      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
591      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
592      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
593      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
594      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
595      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
596      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
597      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
598      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
599      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
600      { X86::MOV16rr,         X86::MOV16rm },
601      { X86::MOV32rr,         X86::MOV32rm },
602      { X86::MOV64rr,         X86::MOV64rm },
603      { X86::MOV8rr,          X86::MOV8rm },
604      { X86::MOVAPDrr,        X86::MOVAPDrm },
605      { X86::MOVAPSrr,        X86::MOVAPSrm },
606      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
607      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
608      { X86::MOVQI2PQIrr,     X86::MOVQI2PQIrm },
609      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
610      { X86::MOVSDrr,         X86::MOVSDrm },
611      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
612      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
613      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
614      { X86::MOVSSrr,         X86::MOVSSrm },
615      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
616      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
617      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
618      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
619      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
620      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
621      { X86::MOVUPDrr,        X86::MOVUPDrm },
622      { X86::MOVUPSrr,        X86::MOVUPSrm },
623      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
624      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
625      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
626      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
627      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
628      { X86::PSHUFDri,        X86::PSHUFDmi },
629      { X86::PSHUFHWri,       X86::PSHUFHWmi },
630      { X86::PSHUFLWri,       X86::PSHUFLWmi },
631      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
632      { X86::TEST16rr,        X86::TEST16rm },
633      { X86::TEST32rr,        X86::TEST32rm },
634      { X86::TEST64rr,        X86::TEST64rm },
635      { X86::TEST8rr,         X86::TEST8rm },
636      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
637      { X86::UCOMISDrr,       X86::UCOMISDrm },
638      { X86::UCOMISSrr,       X86::UCOMISSrm },
639      { X86::XCHG16rr,        X86::XCHG16rm },
640      { X86::XCHG32rr,        X86::XCHG32rm },
641      { X86::XCHG64rr,        X86::XCHG64rm },
642      { X86::XCHG8rr,         X86::XCHG8rm }
643    };
644    ASSERT_SORTED(OpcodeTable);
645    OpcodeTablePtr = OpcodeTable;
646    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
647  } else if (i == 2) {
648    static const TableEntry OpcodeTable[] = {
649      { X86::ADC32rr,         X86::ADC32rm },
650      { X86::ADC64rr,         X86::ADC64rm },
651      { X86::ADD16rr,         X86::ADD16rm },
652      { X86::ADD32rr,         X86::ADD32rm },
653      { X86::ADD64rr,         X86::ADD64rm },
654      { X86::ADD8rr,          X86::ADD8rm },
655      { X86::ADDPDrr,         X86::ADDPDrm },
656      { X86::ADDPSrr,         X86::ADDPSrm },
657      { X86::ADDSDrr,         X86::ADDSDrm },
658      { X86::ADDSSrr,         X86::ADDSSrm },
659      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
660      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
661      { X86::AND16rr,         X86::AND16rm },
662      { X86::AND32rr,         X86::AND32rm },
663      { X86::AND64rr,         X86::AND64rm },
664      { X86::AND8rr,          X86::AND8rm },
665      { X86::ANDNPDrr,        X86::ANDNPDrm },
666      { X86::ANDNPSrr,        X86::ANDNPSrm },
667      { X86::ANDPDrr,         X86::ANDPDrm },
668      { X86::ANDPSrr,         X86::ANDPSrm },
669      { X86::CMOVA16rr,       X86::CMOVA16rm },
670      { X86::CMOVA32rr,       X86::CMOVA32rm },
671      { X86::CMOVA64rr,       X86::CMOVA64rm },
672      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
673      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
674      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
675      { X86::CMOVB16rr,       X86::CMOVB16rm },
676      { X86::CMOVB32rr,       X86::CMOVB32rm },
677      { X86::CMOVB64rr,       X86::CMOVB64rm },
678      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
679      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
680      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
681      { X86::CMOVE16rr,       X86::CMOVE16rm },
682      { X86::CMOVE32rr,       X86::CMOVE32rm },
683      { X86::CMOVE64rr,       X86::CMOVE64rm },
684      { X86::CMOVG16rr,       X86::CMOVG16rm },
685      { X86::CMOVG32rr,       X86::CMOVG32rm },
686      { X86::CMOVG64rr,       X86::CMOVG64rm },
687      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
688      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
689      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
690      { X86::CMOVL16rr,       X86::CMOVL16rm },
691      { X86::CMOVL32rr,       X86::CMOVL32rm },
692      { X86::CMOVL64rr,       X86::CMOVL64rm },
693      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
694      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
695      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
696      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
697      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
698      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
699      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
700      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
701      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
702      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
703      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
704      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
705      { X86::CMOVP16rr,       X86::CMOVP16rm },
706      { X86::CMOVP32rr,       X86::CMOVP32rm },
707      { X86::CMOVP64rr,       X86::CMOVP64rm },
708      { X86::CMOVS16rr,       X86::CMOVS16rm },
709      { X86::CMOVS32rr,       X86::CMOVS32rm },
710      { X86::CMOVS64rr,       X86::CMOVS64rm },
711      { X86::DIVPDrr,         X86::DIVPDrm },
712      { X86::DIVPSrr,         X86::DIVPSrm },
713      { X86::DIVSDrr,         X86::DIVSDrm },
714      { X86::DIVSSrr,         X86::DIVSSrm },
715      { X86::HADDPDrr,        X86::HADDPDrm },
716      { X86::HADDPSrr,        X86::HADDPSrm },
717      { X86::HSUBPDrr,        X86::HSUBPDrm },
718      { X86::HSUBPSrr,        X86::HSUBPSrm },
719      { X86::IMUL16rr,        X86::IMUL16rm },
720      { X86::IMUL32rr,        X86::IMUL32rm },
721      { X86::MAXPDrr,         X86::MAXPDrm },
722      { X86::MAXPSrr,         X86::MAXPSrm },
723      { X86::MINPDrr,         X86::MINPDrm },
724      { X86::MINPSrr,         X86::MINPSrm },
725      { X86::MULPDrr,         X86::MULPDrm },
726      { X86::MULPSrr,         X86::MULPSrm },
727      { X86::MULSDrr,         X86::MULSDrm },
728      { X86::MULSSrr,         X86::MULSSrm },
729      { X86::OR16rr,          X86::OR16rm },
730      { X86::OR32rr,          X86::OR32rm },
731      { X86::OR64rr,          X86::OR64rm },
732      { X86::OR8rr,           X86::OR8rm },
733      { X86::ORPDrr,          X86::ORPDrm },
734      { X86::ORPSrr,          X86::ORPSrm },
735      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
736      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
737      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
738      { X86::PADDBrr,         X86::PADDBrm },
739      { X86::PADDDrr,         X86::PADDDrm },
740      { X86::PADDSBrr,        X86::PADDSBrm },
741      { X86::PADDSWrr,        X86::PADDSWrm },
742      { X86::PADDWrr,         X86::PADDWrm },
743      { X86::PANDNrr,         X86::PANDNrm },
744      { X86::PANDrr,          X86::PANDrm },
745      { X86::PAVGBrr,         X86::PAVGBrm },
746      { X86::PAVGWrr,         X86::PAVGWrm },
747      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
748      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
749      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
750      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
751      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
752      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
753      { X86::PINSRWrri,       X86::PINSRWrmi },
754      { X86::PMADDWDrr,       X86::PMADDWDrm },
755      { X86::PMAXSWrr,        X86::PMAXSWrm },
756      { X86::PMAXUBrr,        X86::PMAXUBrm },
757      { X86::PMINSWrr,        X86::PMINSWrm },
758      { X86::PMINUBrr,        X86::PMINUBrm },
759      { X86::PMULHUWrr,       X86::PMULHUWrm },
760      { X86::PMULHWrr,        X86::PMULHWrm },
761      { X86::PMULLWrr,        X86::PMULLWrm },
762      { X86::PMULUDQrr,       X86::PMULUDQrm },
763      { X86::PORrr,           X86::PORrm },
764      { X86::PSADBWrr,        X86::PSADBWrm },
765      { X86::PSLLDrr,         X86::PSLLDrm },
766      { X86::PSLLQrr,         X86::PSLLQrm },
767      { X86::PSLLWrr,         X86::PSLLWrm },
768      { X86::PSRADrr,         X86::PSRADrm },
769      { X86::PSRAWrr,         X86::PSRAWrm },
770      { X86::PSRLDrr,         X86::PSRLDrm },
771      { X86::PSRLQrr,         X86::PSRLQrm },
772      { X86::PSRLWrr,         X86::PSRLWrm },
773      { X86::PSUBBrr,         X86::PSUBBrm },
774      { X86::PSUBDrr,         X86::PSUBDrm },
775      { X86::PSUBSBrr,        X86::PSUBSBrm },
776      { X86::PSUBSWrr,        X86::PSUBSWrm },
777      { X86::PSUBWrr,         X86::PSUBWrm },
778      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
779      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
780      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
781      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
782      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
783      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
784      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
785      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
786      { X86::PXORrr,          X86::PXORrm },
787      { X86::RCPPSr,          X86::RCPPSm },
788      { X86::RSQRTPSr,        X86::RSQRTPSm },
789      { X86::SBB32rr,         X86::SBB32rm },
790      { X86::SBB64rr,         X86::SBB64rm },
791      { X86::SHUFPDrri,       X86::SHUFPDrmi },
792      { X86::SHUFPSrri,       X86::SHUFPSrmi },
793      { X86::SQRTPDr,         X86::SQRTPDm },
794      { X86::SQRTPSr,         X86::SQRTPSm },
795      { X86::SQRTSDr,         X86::SQRTSDm },
796      { X86::SQRTSSr,         X86::SQRTSSm },
797      { X86::SUB16rr,         X86::SUB16rm },
798      { X86::SUB32rr,         X86::SUB32rm },
799      { X86::SUB64rr,         X86::SUB64rm },
800      { X86::SUB8rr,          X86::SUB8rm },
801      { X86::SUBPDrr,         X86::SUBPDrm },
802      { X86::SUBPSrr,         X86::SUBPSrm },
803      { X86::SUBSDrr,         X86::SUBSDrm },
804      { X86::SUBSSrr,         X86::SUBSSrm },
805      // FIXME: TEST*rr -> swapped operand of TEST*mr.
806      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
807      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
808      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
809      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
810      { X86::XOR16rr,         X86::XOR16rm },
811      { X86::XOR32rr,         X86::XOR32rm },
812      { X86::XOR64rr,         X86::XOR64rm },
813      { X86::XOR8rr,          X86::XOR8rm },
814      { X86::XORPDrr,         X86::XORPDrm },
815      { X86::XORPSrr,         X86::XORPSrm }
816    };
817    ASSERT_SORTED(OpcodeTable);
818    OpcodeTablePtr = OpcodeTable;
819    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
820  }
821
822  // If table selected...
823  if (OpcodeTablePtr) {
824    // Find the Opcode to fuse
825    unsigned fromOpcode = MI->getOpcode();
826    // Lookup fromOpcode in table
827    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
828                                              fromOpcode)) {
829      if (isTwoAddrFold)
830        return FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
831
832      return FuseInst(Entry->to, i, FrameIndex, MI, TII);
833    }
834  }
835
836  // No fusion
837  if (PrintFailedFusing)
838    std::cerr << "We failed to fuse ("
839              << ((i == 1) ? "r" : "s") << "): " << *MI;
840  return NULL;
841}
842
843
844const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
845  static const unsigned CalleeSaveRegs32Bit[] = {
846    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
847  };
848  static const unsigned CalleeSaveRegs64Bit[] = {
849    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
850  };
851
852  return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
853}
854
855const TargetRegisterClass* const*
856X86RegisterInfo::getCalleeSaveRegClasses() const {
857  static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
858    &X86::GR32RegClass, &X86::GR32RegClass,
859    &X86::GR32RegClass, &X86::GR32RegClass,  0
860  };
861  static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
862    &X86::GR64RegClass, &X86::GR64RegClass,
863    &X86::GR64RegClass, &X86::GR64RegClass,
864    &X86::GR64RegClass, &X86::GR64RegClass, 0
865  };
866
867  return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
868}
869
870//===----------------------------------------------------------------------===//
871// Stack Frame Processing methods
872//===----------------------------------------------------------------------===//
873
874// hasFP - Return true if the specified function should have a dedicated frame
875// pointer register.  This is true if the function has variable sized allocas or
876// if frame pointer elimination is disabled.
877//
878static bool hasFP(const MachineFunction &MF) {
879  return (NoFramePointerElim ||
880          MF.getFrameInfo()->hasVarSizedObjects() ||
881          MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
882}
883
884void X86RegisterInfo::
885eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
886                              MachineBasicBlock::iterator I) const {
887  if (hasFP(MF)) {
888    // If we have a frame pointer, turn the adjcallstackup instruction into a
889    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
890    // <amt>'
891    MachineInstr *Old = I;
892    unsigned Amount = Old->getOperand(0).getImmedValue();
893    if (Amount != 0) {
894      // We need to keep the stack aligned properly.  To do this, we round the
895      // amount of space needed for the outgoing arguments up to the next
896      // alignment boundary.
897      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
898      Amount = (Amount+Align-1)/Align*Align;
899
900      MachineInstr *New = 0;
901      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
902        New=BuildMI(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
903          .addReg(StackPtr).addImm(Amount);
904      } else {
905        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
906        // factor out the amount the callee already popped.
907        unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
908        Amount -= CalleeAmt;
909        if (Amount) {
910          unsigned Opc = (Amount < 128) ?
911            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
912            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
913          New = BuildMI(Opc, 1,  StackPtr).addReg(StackPtr).addImm(Amount);
914        }
915      }
916
917      // Replace the pseudo instruction with a new instruction...
918      if (New) MBB.insert(I, New);
919    }
920  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
921    // If we are performing frame pointer elimination and if the callee pops
922    // something off the stack pointer, add it back.  We do this until we have
923    // more advanced stack pointer tracking ability.
924    if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
925      unsigned Opc = (CalleeAmt < 128) ?
926        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
927        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
928      MachineInstr *New =
929        BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
930      MBB.insert(I, New);
931    }
932  }
933
934  MBB.erase(I);
935}
936
937void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
938  unsigned i = 0;
939  MachineInstr &MI = *II;
940  MachineFunction &MF = *MI.getParent()->getParent();
941  while (!MI.getOperand(i).isFrameIndex()) {
942    ++i;
943    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
944  }
945
946  int FrameIndex = MI.getOperand(i).getFrameIndex();
947  // This must be part of a four operand memory reference.  Replace the
948  // FrameIndex with base register with EBP.  Add an offset to the offset.
949  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
950
951  // Now add the frame object offset to the offset from EBP.
952  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
953               MI.getOperand(i+3).getImmedValue()+SlotSize;
954
955  if (!hasFP(MF))
956    Offset += MF.getFrameInfo()->getStackSize();
957  else
958    Offset += SlotSize;  // Skip the saved EBP
959
960  MI.getOperand(i+3).ChangeToImmediate(Offset);
961}
962
963void
964X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
965  if (hasFP(MF)) {
966    // Create a frame entry for the EBP register that must be saved.
967    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
968    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
969           "Slot for EBP register must be last in order to be found!");
970  }
971}
972
973void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
974  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
975  MachineBasicBlock::iterator MBBI = MBB.begin();
976  MachineFrameInfo *MFI = MF.getFrameInfo();
977  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
978  const Function* Fn = MF.getFunction();
979  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
980  MachineInstr *MI;
981
982  // Get the number of bytes to allocate from the FrameInfo
983  unsigned NumBytes = MFI->getStackSize();
984  if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
985    // When we have no frame pointer, we reserve argument space for call sites
986    // in the function immediately on entry to the current function.  This
987    // eliminates the need for add/sub ESP brackets around call sites.
988    //
989    if (!hasFP(MF))
990      NumBytes += MFI->getMaxCallFrameSize();
991
992    // Round the size to a multiple of the alignment (don't forget the 4/8 byte
993    // offset though).
994    NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
995  }
996
997  // Update frame info to pretend that this is part of the stack...
998  MFI->setStackSize(NumBytes);
999
1000  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
1001    if (NumBytes >= 4096 && Subtarget->isTargetCygwin()) {
1002      // Function prologue calls _alloca to probe the stack when allocating
1003      // more than 4k bytes in one go. Touching the stack at 4K increments is
1004      // necessary to ensure that the guard pages used by the OS virtual memory
1005      // manager are allocated in correct sequence.
1006      MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
1007      MBB.insert(MBBI, MI);
1008      MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1009      MBB.insert(MBBI, MI);
1010    } else {
1011      unsigned Opc = (NumBytes < 128) ?
1012        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1013        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1014      MI= BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
1015      MBB.insert(MBBI, MI);
1016    }
1017  }
1018
1019  if (hasFP(MF)) {
1020    // Get the offset of the stack slot for the EBP register... which is
1021    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1022    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1023
1024    // Save EBP into the appropriate stack slot...
1025    // mov [ESP-<offset>], EBP
1026    MI = addRegOffset(BuildMI(Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
1027                      StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1028    MBB.insert(MBBI, MI);
1029
1030    // Update EBP with the new base value...
1031    if (NumBytes == SlotSize)    // mov EBP, ESP
1032      MI = BuildMI(Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
1033        addReg(StackPtr);
1034    else                  // lea EBP, [ESP+StackSize]
1035      MI = addRegOffset(BuildMI(Is64Bit ? X86::LEA64r : X86::LEA32r,
1036                               5, FramePtr), StackPtr, NumBytes-SlotSize);
1037
1038    MBB.insert(MBBI, MI);
1039  }
1040
1041  // If it's main() on Cygwin\Mingw32 we should align stack as well
1042  if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1043      Subtarget->isTargetCygwin()) {
1044    MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
1045    MBB.insert(MBBI, MI);
1046
1047    // Probe the stack
1048    MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
1049    MBB.insert(MBBI, MI);
1050    MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1051    MBB.insert(MBBI, MI);
1052  }
1053}
1054
1055void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1056                                   MachineBasicBlock &MBB) const {
1057  const MachineFrameInfo *MFI = MF.getFrameInfo();
1058  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1059
1060  switch (MBBI->getOpcode()) {
1061  case X86::RET:
1062  case X86::RETI:
1063  case X86::TAILJMPd:
1064  case X86::TAILJMPr:
1065  case X86::TAILJMPm: break;  // These are ok
1066  default:
1067    assert(0 && "Can only insert epilog into returning blocks");
1068  }
1069
1070  if (hasFP(MF)) {
1071    // mov ESP, EBP
1072    BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
1073      addReg(FramePtr);
1074
1075    // pop EBP
1076    BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr);
1077  } else {
1078    // Get the number of bytes allocated from the FrameInfo...
1079    unsigned NumBytes = MFI->getStackSize();
1080
1081    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
1082      // If there is an ADD32ri or SUB32ri of ESP immediately before this
1083      // instruction, merge the two instructions.
1084      if (MBBI != MBB.begin()) {
1085        MachineBasicBlock::iterator PI = prior(MBBI);
1086        unsigned Opc = PI->getOpcode();
1087        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1088             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1089            PI->getOperand(0).getReg() == StackPtr) {
1090          NumBytes += PI->getOperand(2).getImmedValue();
1091          MBB.erase(PI);
1092        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1093                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1094                   PI->getOperand(0).getReg() == StackPtr) {
1095          NumBytes -= PI->getOperand(2).getImmedValue();
1096          MBB.erase(PI);
1097        }
1098      }
1099
1100      if (NumBytes > 0) {
1101        unsigned Opc = (NumBytes < 128) ?
1102          (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1103          (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1104        BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes);
1105      } else if ((int)NumBytes < 0) {
1106        unsigned Opc = (-NumBytes < 128) ?
1107          (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1108          (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1109        BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes);
1110      }
1111    }
1112  }
1113}
1114
1115unsigned X86RegisterInfo::getRARegister() const {
1116  return X86::ST0;  // use a non-register register
1117}
1118
1119unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1120  return hasFP(MF) ? FramePtr : StackPtr;
1121}
1122
1123namespace llvm {
1124unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1125  switch (VT) {
1126  default: return Reg;
1127  case MVT::i8:
1128    if (High) {
1129      switch (Reg) {
1130      default: return 0;
1131      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1132        return X86::AH;
1133      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1134        return X86::DH;
1135      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1136        return X86::CH;
1137      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1138        return X86::BH;
1139      }
1140    } else {
1141      switch (Reg) {
1142      default: return 0;
1143      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1144        return X86::AL;
1145      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1146        return X86::DL;
1147      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1148        return X86::CL;
1149      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1150        return X86::BL;
1151      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1152        return X86::SIL;
1153      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1154        return X86::DIL;
1155      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1156        return X86::BPL;
1157      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1158        return X86::SPL;
1159      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1160        return X86::R8B;
1161      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1162        return X86::R9B;
1163      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1164        return X86::R10B;
1165      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1166        return X86::R11B;
1167      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1168        return X86::R12B;
1169      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1170        return X86::R13B;
1171      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1172        return X86::R14B;
1173      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1174        return X86::R15B;
1175      }
1176    }
1177  case MVT::i16:
1178    switch (Reg) {
1179    default: return Reg;
1180    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1181      return X86::AX;
1182    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1183      return X86::DX;
1184    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1185      return X86::CX;
1186    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1187      return X86::BX;
1188    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1189      return X86::SI;
1190    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1191      return X86::DI;
1192    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1193      return X86::BP;
1194    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1195      return X86::SP;
1196    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1197      return X86::R8W;
1198    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1199      return X86::R9W;
1200    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1201      return X86::R10W;
1202    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1203      return X86::R11W;
1204    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1205      return X86::R12W;
1206    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1207      return X86::R13W;
1208    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1209      return X86::R14W;
1210    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1211      return X86::R15W;
1212    }
1213  case MVT::i32:
1214    switch (Reg) {
1215    default: return Reg;
1216    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1217      return X86::EAX;
1218    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1219      return X86::EDX;
1220    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1221      return X86::ECX;
1222    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1223      return X86::EBX;
1224    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1225      return X86::ESI;
1226    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1227      return X86::EDI;
1228    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1229      return X86::EBP;
1230    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1231      return X86::ESP;
1232    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1233      return X86::R8D;
1234    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1235      return X86::R9D;
1236    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1237      return X86::R10D;
1238    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1239      return X86::R11D;
1240    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1241      return X86::R12D;
1242    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1243      return X86::R13D;
1244    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1245      return X86::R14D;
1246    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1247      return X86::R15D;
1248    }
1249  case MVT::i64:
1250    switch (Reg) {
1251    default: return Reg;
1252    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1253      return X86::RAX;
1254    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1255      return X86::RDX;
1256    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1257      return X86::RCX;
1258    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1259      return X86::RBX;
1260    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1261      return X86::RSI;
1262    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1263      return X86::RDI;
1264    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1265      return X86::RBP;
1266    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1267      return X86::RSP;
1268    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1269      return X86::R8;
1270    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1271      return X86::R9;
1272    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1273      return X86::R10;
1274    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1275      return X86::R11;
1276    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1277      return X86::R12;
1278    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1279      return X86::R13;
1280    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1281      return X86::R14;
1282    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1283      return X86::R15;
1284    }
1285  }
1286
1287  return Reg;
1288}
1289}
1290
1291#include "X86GenRegisterInfo.inc"
1292
1293