X86RegisterInfo.cpp revision 6972177bd497fd61d43ed90618fe11f827c441c5
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the MRegisterInfo class. This 11// file is responsible for the frame pointer elimination optimization on X86. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86RegisterInfo.h" 17#include "X86InstrBuilder.h" 18#include "llvm/Constants.h" 19#include "llvm/Type.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/Target/TargetFrameInfo.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/ADT/STLExtras.h" 29#include <iostream> 30 31using namespace llvm; 32 33namespace { 34 cl::opt<bool> 35 NoFusing("disable-spill-fusing", 36 cl::desc("Disable fusing of spill code into instructions")); 37 cl::opt<bool> 38 PrintFailedFusing("print-failed-fuse-candidates", 39 cl::desc("Print instructions that the allocator wants to" 40 " fuse, but the X86 backend currently can't"), 41 cl::Hidden); 42} 43 44X86RegisterInfo::X86RegisterInfo() 45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {} 46 47static unsigned getIdx(unsigned SpillSize) { 48 switch (SpillSize) { 49 default: assert(0 && "Invalid data size!"); 50 case 8: return 0; 51 case 16: return 1; 52 case 32: return 2; 53 case 64: return 3; // FP in 64-bit spill mode. 54 case 80: return 4; // FP in 80-bit spill mode. 55 } 56} 57 58void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 59 MachineBasicBlock::iterator MI, 60 unsigned SrcReg, int FrameIdx) const { 61 static const unsigned Opcode[] = 62 { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST64m, X86::FSTP80m }; 63 unsigned Idx = getIdx(getSpillSize(SrcReg)); 64 addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 5), FrameIdx).addReg(SrcReg); 65} 66 67void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator MI, 69 unsigned DestReg, int FrameIdx)const{ 70 static const unsigned Opcode[] = 71 { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD64m, X86::FLD80m }; 72 unsigned Idx = getIdx(getSpillSize(DestReg)); 73 addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 4, DestReg), FrameIdx); 74} 75 76void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MI, 78 unsigned DestReg, unsigned SrcReg, 79 const TargetRegisterClass *RC) const { 80 static const unsigned Opcode[] = 81 { X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::FpMOV }; 82 BuildMI(MBB, MI, Opcode[getIdx(RC->getSize()*8)], 1, DestReg).addReg(SrcReg); 83} 84 85static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex, 86 MachineInstr *MI) { 87 return addFrameReference(BuildMI(Opcode, 4), FrameIndex); 88} 89 90static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex, 91 MachineInstr *MI) { 92 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 93 .addReg(MI->getOperand(1).getReg()); 94} 95 96static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex, 97 MachineInstr *MI) { 98 return addFrameReference(BuildMI(Opcode, 6), FrameIndex) 99 .addReg(MI->getOperand(1).getReg()) 100 .addZImm(MI->getOperand(2).getImmedValue()); 101} 102 103static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex, 104 MachineInstr *MI) { 105 if (MI->getOperand(1).isImmediate()) 106 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 107 .addZImm(MI->getOperand(1).getImmedValue()); 108 else if (MI->getOperand(1).isGlobalAddress()) 109 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 110 .addGlobalAddress(MI->getOperand(1).getGlobal()); 111 assert(0 && "Unknown operand for MakeMI!"); 112 return 0; 113} 114 115static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex, 116 MachineInstr *MI) { 117 const MachineOperand& op = MI->getOperand(0); 118 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()), 119 FrameIndex); 120} 121 122static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex, 123 MachineInstr *MI) { 124 const MachineOperand& op = MI->getOperand(0); 125 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()), 126 FrameIndex).addZImm(MI->getOperand(2).getImmedValue()); 127} 128 129 130MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI, 131 unsigned i, 132 int FrameIndex) const { 133 if (NoFusing) return NULL; 134 135 /// FIXME: This should obviously be autogenerated by tablegen when patterns 136 /// are available! 137 MachineBasicBlock& MBB = *MI->getParent(); 138 if (i == 0) { 139 switch(MI->getOpcode()) { 140 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI); 141 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI); 142 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI); 143 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI); 144 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI); 145 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI); 146 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI); 147 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI); 148 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI); 149 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI); 150 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI); 151 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI); 152 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI); 153 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI); 154 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI); 155 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI); 156 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI); 157 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI); 158 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI); 159 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI); 160 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI); 161 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI); 162 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI); 163 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI); 164 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI); 165 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI); 166 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI); 167 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI); 168 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI); 169 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI); 170 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI); 171 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI); 172 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI); 173 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI); 174 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI); 175 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI); 176 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); 177 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); 178 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI); 179 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI); 180 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI); 181 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI); 182 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI); 183 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI); 184 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); 185 case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI); 186 case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI); 187 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); 188 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI); 189 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI); 190 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI); 191 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI); 192 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI); 193 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI); 194 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI); 195 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI); 196 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI); 197 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI); 198 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI); 199 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI); 200 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI); 201 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI); 202 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI); 203 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI); 204 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI); 205 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI); 206 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI); 207 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI); 208 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI); 209 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI); 210 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI); 211 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI); 212 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI); 213 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI); 214 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI); 215 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI); 216 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI); 217 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI); 218 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI); 219 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI); 220 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI); 221 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI); 222 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI); 223 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI); 224 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI); 225 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI); 226 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI); 227 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI); 228 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI); 229 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI); 230 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI); 231 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI); 232 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI); 233 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI); 234 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI); 235 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI); 236 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI); 237 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI); 238 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI); 239 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI); 240 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI); 241 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI); 242 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI); 243 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI); 244 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI); 245 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI); 246 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI); 247 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI); 248 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI); 249 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI); 250 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI); 251 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI); 252 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI); 253 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI); 254 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI); 255 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI); 256 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI); 257 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI); 258 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI); 259 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI); 260 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI); 261 case X86::TEST8rr: return MakeMRInst(X86::TEST8mr ,FrameIndex, MI); 262 case X86::TEST16rr: return MakeMRInst(X86::TEST16mr,FrameIndex, MI); 263 case X86::TEST32rr: return MakeMRInst(X86::TEST32mr,FrameIndex, MI); 264 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI); 265 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI); 266 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI); 267 case X86::CMP8rr: return MakeMRInst(X86::CMP8mr , FrameIndex, MI); 268 case X86::CMP16rr: return MakeMRInst(X86::CMP16mr, FrameIndex, MI); 269 case X86::CMP32rr: return MakeMRInst(X86::CMP32mr, FrameIndex, MI); 270 case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI); 271 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); 272 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); 273 } 274 } else if (i == 1) { 275 switch(MI->getOpcode()) { 276 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI); 277 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI); 278 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI); 279 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI); 280 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI); 281 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI); 282 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI); 283 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI); 284 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI); 285 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI); 286 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI); 287 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI); 288 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI); 289 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI); 290 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI); 291 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI); 292 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI); 293 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI); 294 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI); 295 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI); 296 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI); 297 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI); 298 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI); 299 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI); 300 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI); 301 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI); 302 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI); 303 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI); 304 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI); 305 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI); 306 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI); 307 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI); 308 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI); 309 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI); 310 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI); 311 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI); 312 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI); 313 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI); 314 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI); 315 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI); 316 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI); 317 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI); 318 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI); 319 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI); 320 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI); 321 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI); 322 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI); 323 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI); 324 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI); 325 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI); 326 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI); 327 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI); 328 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI); 329 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI); 330 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI); 331 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); 332 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); 333 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI); 334 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI); 335 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI); 336 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI); 337 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI); 338 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI); 339 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI); 340 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI); 341 case X86::MOVZX32rr8: return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI); 342 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI); 343 } 344 } 345 if (PrintFailedFusing) 346 std::cerr << "We failed to fuse: " << *MI; 347 return NULL; 348} 349 350//===----------------------------------------------------------------------===// 351// Stack Frame Processing methods 352//===----------------------------------------------------------------------===// 353 354// hasFP - Return true if the specified function should have a dedicated frame 355// pointer register. This is true if the function has variable sized allocas or 356// if frame pointer elimination is disabled. 357// 358static bool hasFP(MachineFunction &MF) { 359 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 360} 361 362void X86RegisterInfo:: 363eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator I) const { 365 if (hasFP(MF)) { 366 // If we have a frame pointer, turn the adjcallstackup instruction into a 367 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP, 368 // <amt>' 369 MachineInstr *Old = I; 370 unsigned Amount = Old->getOperand(0).getImmedValue(); 371 if (Amount != 0) { 372 // We need to keep the stack aligned properly. To do this, we round the 373 // amount of space needed for the outgoing arguments up to the next 374 // alignment boundary. 375 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 376 Amount = (Amount+Align-1)/Align*Align; 377 378 MachineInstr *New = 0; 379 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { 380 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) 381 .addZImm(Amount); 382 } else { 383 assert(Old->getOpcode() == X86::ADJCALLSTACKUP); 384 // factor out the amount the callee already popped. 385 unsigned CalleeAmt = Old->getOperand(1).getImmedValue(); 386 Amount -= CalleeAmt; 387 if (Amount) 388 New = BuildMI(X86::ADD32ri, 1, X86::ESP, 389 MachineOperand::UseAndDef).addZImm(Amount); 390 } 391 392 // Replace the pseudo instruction with a new instruction... 393 if (New) MBB.insert(I, New); 394 } 395 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { 396 // If we are performing frame pointer elimination and if the callee pops 397 // something off the stack pointer, add it back. We do this until we have 398 // more advanced stack pointer tracking ability. 399 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) { 400 MachineInstr *New = 401 BuildMI(X86::SUB32ri, 1, X86::ESP, 402 MachineOperand::UseAndDef).addZImm(CalleeAmt); 403 MBB.insert(I, New); 404 } 405 } 406 407 MBB.erase(I); 408} 409 410void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 411 unsigned i = 0; 412 MachineInstr &MI = *II; 413 MachineFunction &MF = *MI.getParent()->getParent(); 414 while (!MI.getOperand(i).isFrameIndex()) { 415 ++i; 416 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 417 } 418 419 int FrameIndex = MI.getOperand(i).getFrameIndex(); 420 421 // This must be part of a four operand memory reference. Replace the 422 // FrameIndex with base register with EBP. Add add an offset to the offset. 423 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP); 424 425 // Now add the frame object offset to the offset from EBP. 426 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 427 MI.getOperand(i+3).getImmedValue()+4; 428 429 if (!hasFP(MF)) 430 Offset += MF.getFrameInfo()->getStackSize(); 431 else 432 Offset += 4; // Skip the saved EBP 433 434 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset); 435} 436 437void 438X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ 439 if (hasFP(MF)) { 440 // Create a frame entry for the EBP register that must be saved. 441 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8); 442 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 443 "Slot for EBP register must be last in order to be found!"); 444 } 445} 446 447void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { 448 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 449 MachineBasicBlock::iterator MBBI = MBB.begin(); 450 MachineFrameInfo *MFI = MF.getFrameInfo(); 451 MachineInstr *MI; 452 453 // Get the number of bytes to allocate from the FrameInfo 454 unsigned NumBytes = MFI->getStackSize(); 455 if (hasFP(MF)) { 456 // Get the offset of the stack slot for the EBP register... which is 457 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 458 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4; 459 460 if (NumBytes) { // adjust stack pointer: ESP -= numbytes 461 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) 462 .addZImm(NumBytes); 463 MBB.insert(MBBI, MI); 464 } 465 466 // Save EBP into the appropriate stack slot... 467 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP 468 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); 469 MBB.insert(MBBI, MI); 470 471 // Update EBP with the new base value... 472 if (NumBytes == 4) // mov EBP, ESP 473 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP); 474 else // lea EBP, [ESP+StackSize] 475 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4); 476 477 MBB.insert(MBBI, MI); 478 479 } else { 480 if (MFI->hasCalls()) { 481 // When we have no frame pointer, we reserve argument space for call sites 482 // in the function immediately on entry to the current function. This 483 // eliminates the need for add/sub ESP brackets around call sites. 484 // 485 NumBytes += MFI->getMaxCallFrameSize(); 486 487 // Round the size to a multiple of the alignment (don't forget the 4 byte 488 // offset though). 489 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 490 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4; 491 } 492 493 // Update frame info to pretend that this is part of the stack... 494 MFI->setStackSize(NumBytes); 495 496 if (NumBytes) { 497 // adjust stack pointer: ESP -= numbytes 498 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) 499 .addZImm(NumBytes); 500 MBB.insert(MBBI, MI); 501 } 502 } 503} 504 505void X86RegisterInfo::emitEpilogue(MachineFunction &MF, 506 MachineBasicBlock &MBB) const { 507 const MachineFrameInfo *MFI = MF.getFrameInfo(); 508 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 509 510 switch (MBBI->getOpcode()) { 511 case X86::RET: 512 case X86::RETI: 513 case X86::TAILJMPd: 514 case X86::TAILJMPr: 515 case X86::TAILJMPm: break; // These are ok 516 default: 517 assert(0 && "Can only insert epilog into returning blocks"); 518 } 519 520 if (hasFP(MF)) { 521 // Get the offset of the stack slot for the EBP register... which is 522 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 523 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4; 524 525 // mov ESP, EBP 526 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP); 527 528 // pop EBP 529 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP); 530 } else { 531 // Get the number of bytes allocated from the FrameInfo... 532 unsigned NumBytes = MFI->getStackSize(); 533 534 if (NumBytes) { // adjust stack pointer back: ESP += numbytes 535 // If there is an ADD32ri or SUB32ri of ESP immediately before this 536 // instruction, merge the two instructions. 537 if (MBBI != MBB.begin()) { 538 MachineBasicBlock::iterator PI = prior(MBBI); 539 if (PI->getOpcode() == X86::ADD32ri && 540 PI->getOperand(0).getReg() == X86::ESP) { 541 NumBytes += PI->getOperand(1).getImmedValue(); 542 MBB.erase(PI); 543 } else if (PI->getOpcode() == X86::SUB32ri && 544 PI->getOperand(0).getReg() == X86::ESP) { 545 NumBytes -= PI->getOperand(1).getImmedValue(); 546 MBB.erase(PI); 547 } 548 } 549 550 if (NumBytes > 0) 551 BuildMI(MBB, MBBI, X86::ADD32ri, 2) 552 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes); 553 else if ((int)NumBytes < 0) 554 BuildMI(MBB, MBBI, X86::SUB32ri, 2) 555 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes); 556 } 557 } 558} 559 560#include "X86GenRegisterInfo.inc" 561 562const TargetRegisterClass* 563X86RegisterInfo::getRegClassForType(const Type* Ty) const { 564 switch (Ty->getTypeID()) { 565 case Type::LongTyID: 566 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); 567 default: assert(0 && "Invalid type to getClass!"); 568 case Type::BoolTyID: 569 case Type::SByteTyID: 570 case Type::UByteTyID: return &R8Instance; 571 case Type::ShortTyID: 572 case Type::UShortTyID: return &R16Instance; 573 case Type::IntTyID: 574 case Type::UIntTyID: 575 case Type::PointerTyID: return &R32Instance; 576 577 case Type::FloatTyID: 578 case Type::DoubleTyID: return &RFPInstance; 579 } 580} 581