X86RegisterInfo.cpp revision 6ffcccab5191ef1dcde876800c24a1f58b3b7ad8 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/CommandLine.h"
41#include "llvm/Support/ErrorHandling.h"
42using namespace llvm;
43
44X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45                                 const TargetInstrInfo &tii)
46  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47                         X86::ADJCALLSTACKDOWN64 :
48                         X86::ADJCALLSTACKDOWN32,
49                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
50                         X86::ADJCALLSTACKUP64 :
51                         X86::ADJCALLSTACKUP32),
52    TM(tm), TII(tii) {
53  // Cache some information.
54  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55  Is64Bit = Subtarget->is64Bit();
56  IsWin64 = Subtarget->isTargetWin64();
57  StackAlign = TM.getFrameInfo()->getStackAlignment();
58
59  if (Is64Bit) {
60    SlotSize = 8;
61    StackPtr = X86::RSP;
62    FramePtr = X86::RBP;
63  } else {
64    SlotSize = 4;
65    StackPtr = X86::ESP;
66    FramePtr = X86::EBP;
67  }
68}
69
70/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71/// specific numbering, used in debug info and exception tables.
72int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74  unsigned Flavour = DWARFFlavour::X86_64;
75
76  if (!Subtarget->is64Bit()) {
77    if (Subtarget->isTargetDarwin()) {
78      if (isEH)
79        Flavour = DWARFFlavour::X86_32_DarwinEH;
80      else
81        Flavour = DWARFFlavour::X86_32_Generic;
82    } else if (Subtarget->isTargetCygMing()) {
83      // Unsupported by now, just quick fallback
84      Flavour = DWARFFlavour::X86_32_Generic;
85    } else {
86      Flavour = DWARFFlavour::X86_32_Generic;
87    }
88  }
89
90  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91}
92
93/// getX86RegNum - This function maps LLVM register identifiers to their X86
94/// specific numbering, which is used in various places encoding instructions.
95unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96  switch(RegNo) {
97  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102    return N86::ESP;
103  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104    return N86::EBP;
105  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106    return N86::ESI;
107  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
108    return N86::EDI;
109
110  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
111    return N86::EAX;
112  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
113    return N86::ECX;
114  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115    return N86::EDX;
116  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117    return N86::EBX;
118  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119    return N86::ESP;
120  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121    return N86::EBP;
122  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123    return N86::ESI;
124  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
125    return N86::EDI;
126
127  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129    return RegNo-X86::ST0;
130
131  case X86::XMM0: case X86::XMM8: case X86::MM0:
132    return 0;
133  case X86::XMM1: case X86::XMM9: case X86::MM1:
134    return 1;
135  case X86::XMM2: case X86::XMM10: case X86::MM2:
136    return 2;
137  case X86::XMM3: case X86::XMM11: case X86::MM3:
138    return 3;
139  case X86::XMM4: case X86::XMM12: case X86::MM4:
140    return 4;
141  case X86::XMM5: case X86::XMM13: case X86::MM5:
142    return 5;
143  case X86::XMM6: case X86::XMM14: case X86::MM6:
144    return 6;
145  case X86::XMM7: case X86::XMM15: case X86::MM7:
146    return 7;
147
148  default:
149    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150    llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
151    return 0;
152  }
153}
154
155const TargetRegisterClass *
156X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157                                          const TargetRegisterClass *B,
158                                          unsigned SubIdx) const {
159  switch (SubIdx) {
160  default: return 0;
161  case 1:
162    // 8-bit
163    if (B == &X86::GR8RegClass) {
164      if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
165        return A;
166    } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168          A == &X86::GR64_NOREXRegClass ||
169          A == &X86::GR64_NOSPRegClass ||
170          A == &X86::GR64_NOREX_NOSPRegClass)
171        return &X86::GR64_ABCDRegClass;
172      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173               A == &X86::GR32_NOREXRegClass ||
174               A == &X86::GR32_NOSPRegClass)
175        return &X86::GR32_ABCDRegClass;
176      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177               A == &X86::GR16_NOREXRegClass)
178        return &X86::GR16_ABCDRegClass;
179    } else if (B == &X86::GR8_NOREXRegClass) {
180      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182        return &X86::GR64_NOREXRegClass;
183      else if (A == &X86::GR64_ABCDRegClass)
184        return &X86::GR64_ABCDRegClass;
185      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186               A == &X86::GR32_NOSPRegClass)
187        return &X86::GR32_NOREXRegClass;
188      else if (A == &X86::GR32_ABCDRegClass)
189        return &X86::GR32_ABCDRegClass;
190      else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191        return &X86::GR16_NOREXRegClass;
192      else if (A == &X86::GR16_ABCDRegClass)
193        return &X86::GR16_ABCDRegClass;
194    } else if (B == &X86::FR32RegClass) {
195      return A;
196    }
197    break;
198  case 2:
199    // 8-bit hi
200    if (B == &X86::GR8_ABCD_HRegClass) {
201      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
202          A == &X86::GR64_NOREXRegClass ||
203          A == &X86::GR64_NOSPRegClass ||
204          A == &X86::GR64_NOREX_NOSPRegClass)
205        return &X86::GR64_ABCDRegClass;
206      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
207               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
208        return &X86::GR32_ABCDRegClass;
209      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
210               A == &X86::GR16_NOREXRegClass)
211        return &X86::GR16_ABCDRegClass;
212    } else if (B == &X86::FR64RegClass) {
213      return A;
214    }
215    break;
216  case 3:
217    // 16-bit
218    if (B == &X86::GR16RegClass) {
219      if (A->getSize() == 4 || A->getSize() == 8)
220        return A;
221    } else if (B == &X86::GR16_ABCDRegClass) {
222      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
223          A == &X86::GR64_NOREXRegClass ||
224          A == &X86::GR64_NOSPRegClass ||
225          A == &X86::GR64_NOREX_NOSPRegClass)
226        return &X86::GR64_ABCDRegClass;
227      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
228               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
229        return &X86::GR32_ABCDRegClass;
230    } else if (B == &X86::GR16_NOREXRegClass) {
231      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
232          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
233        return &X86::GR64_NOREXRegClass;
234      else if (A == &X86::GR64_ABCDRegClass)
235        return &X86::GR64_ABCDRegClass;
236      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
237               A == &X86::GR32_NOSPRegClass)
238        return &X86::GR32_NOREXRegClass;
239      else if (A == &X86::GR32_ABCDRegClass)
240        return &X86::GR64_ABCDRegClass;
241    } else if (B == &X86::VR128RegClass) {
242      return A;
243    }
244    break;
245  case 4:
246    // 32-bit
247    if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
248      if (A->getSize() == 8)
249        return A;
250    } else if (B == &X86::GR32_ABCDRegClass) {
251      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252          A == &X86::GR64_NOREXRegClass ||
253          A == &X86::GR64_NOSPRegClass ||
254          A == &X86::GR64_NOREX_NOSPRegClass)
255        return &X86::GR64_ABCDRegClass;
256    } else if (B == &X86::GR32_NOREXRegClass) {
257      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
258          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
259        return &X86::GR64_NOREXRegClass;
260      else if (A == &X86::GR64_ABCDRegClass)
261        return &X86::GR64_ABCDRegClass;
262    }
263    break;
264  }
265  return 0;
266}
267
268const TargetRegisterClass *
269X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
270  switch (Kind) {
271  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
272  case 0: // Normal GPRs.
273    if (TM.getSubtarget<X86Subtarget>().is64Bit())
274      return &X86::GR64RegClass;
275    return &X86::GR32RegClass;
276  case 1: // Normal GRPs except the stack pointer (for encoding reasons).
277    if (TM.getSubtarget<X86Subtarget>().is64Bit())
278      return &X86::GR64_NOSPRegClass;
279    return &X86::GR32_NOSPRegClass;
280  }
281}
282
283const TargetRegisterClass *
284X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
285  if (RC == &X86::CCRRegClass) {
286    if (Is64Bit)
287      return &X86::GR64RegClass;
288    else
289      return &X86::GR32RegClass;
290  }
291  return NULL;
292}
293
294const unsigned *
295X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
296  bool callsEHReturn = false;
297  bool ghcCall = false;
298
299  if (MF) {
300    const MachineFrameInfo *MFI = MF->getFrameInfo();
301    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
302    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
303    const Function *F = MF->getFunction();
304    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
305  }
306
307  static const unsigned GhcCalleeSavedRegs[] = {
308    0
309  };
310
311  static const unsigned CalleeSavedRegs32Bit[] = {
312    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
313  };
314
315  static const unsigned CalleeSavedRegs32EHRet[] = {
316    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
317  };
318
319  static const unsigned CalleeSavedRegs64Bit[] = {
320    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
321  };
322
323  static const unsigned CalleeSavedRegs64EHRet[] = {
324    X86::RAX, X86::RDX, X86::RBX, X86::R12,
325    X86::R13, X86::R14, X86::R15, X86::RBP, 0
326  };
327
328  static const unsigned CalleeSavedRegsWin64[] = {
329    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
330    X86::R12,   X86::R13,   X86::R14,   X86::R15,
331    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
332    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
333    X86::XMM14, X86::XMM15, 0
334  };
335
336  if (ghcCall) {
337    return GhcCalleeSavedRegs;
338  } else if (Is64Bit) {
339    if (IsWin64)
340      return CalleeSavedRegsWin64;
341    else
342      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
343  } else {
344    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
345  }
346}
347
348const TargetRegisterClass* const*
349X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
350  bool callsEHReturn = false;
351
352  if (MF) {
353    const MachineFrameInfo *MFI = MF->getFrameInfo();
354    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
355    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
356  }
357
358  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
359    &X86::GR32RegClass, &X86::GR32RegClass,
360    &X86::GR32RegClass, &X86::GR32RegClass,  0
361  };
362  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
363    &X86::GR32RegClass, &X86::GR32RegClass,
364    &X86::GR32RegClass, &X86::GR32RegClass,
365    &X86::GR32RegClass, &X86::GR32RegClass,  0
366  };
367  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
368    &X86::GR64RegClass, &X86::GR64RegClass,
369    &X86::GR64RegClass, &X86::GR64RegClass,
370    &X86::GR64RegClass, &X86::GR64RegClass, 0
371  };
372  static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
373    &X86::GR64RegClass, &X86::GR64RegClass,
374    &X86::GR64RegClass, &X86::GR64RegClass,
375    &X86::GR64RegClass, &X86::GR64RegClass,
376    &X86::GR64RegClass, &X86::GR64RegClass, 0
377  };
378  static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
379    &X86::GR64RegClass,  &X86::GR64RegClass,
380    &X86::GR64RegClass,  &X86::GR64RegClass,
381    &X86::GR64RegClass,  &X86::GR64RegClass,
382    &X86::GR64RegClass,  &X86::GR64RegClass,
383    &X86::VR128RegClass, &X86::VR128RegClass,
384    &X86::VR128RegClass, &X86::VR128RegClass,
385    &X86::VR128RegClass, &X86::VR128RegClass,
386    &X86::VR128RegClass, &X86::VR128RegClass,
387    &X86::VR128RegClass, &X86::VR128RegClass, 0
388  };
389
390  if (Is64Bit) {
391    if (IsWin64)
392      return CalleeSavedRegClassesWin64;
393    else
394      return (callsEHReturn ?
395              CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
396  } else {
397    return (callsEHReturn ?
398            CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
399  }
400}
401
402BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
403  BitVector Reserved(getNumRegs());
404  // Set the stack-pointer register and its aliases as reserved.
405  Reserved.set(X86::RSP);
406  Reserved.set(X86::ESP);
407  Reserved.set(X86::SP);
408  Reserved.set(X86::SPL);
409
410  // Set the instruction pointer register and its aliases as reserved.
411  Reserved.set(X86::RIP);
412  Reserved.set(X86::EIP);
413  Reserved.set(X86::IP);
414
415  // Set the frame-pointer register and its aliases as reserved if needed.
416  if (hasFP(MF)) {
417    Reserved.set(X86::RBP);
418    Reserved.set(X86::EBP);
419    Reserved.set(X86::BP);
420    Reserved.set(X86::BPL);
421  }
422
423  // Mark the x87 stack registers as reserved, since they don't behave normally
424  // with respect to liveness. We don't fully model the effects of x87 stack
425  // pushes and pops after stackification.
426  Reserved.set(X86::ST0);
427  Reserved.set(X86::ST1);
428  Reserved.set(X86::ST2);
429  Reserved.set(X86::ST3);
430  Reserved.set(X86::ST4);
431  Reserved.set(X86::ST5);
432  Reserved.set(X86::ST6);
433  Reserved.set(X86::ST7);
434  return Reserved;
435}
436
437//===----------------------------------------------------------------------===//
438// Stack Frame Processing methods
439//===----------------------------------------------------------------------===//
440
441/// hasFP - Return true if the specified function should have a dedicated frame
442/// pointer register.  This is true if the function has variable sized allocas
443/// or if frame pointer elimination is disabled.
444bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
445  const MachineFrameInfo *MFI = MF.getFrameInfo();
446  const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
447
448  return (NoFramePointerElim ||
449          needsStackRealignment(MF) ||
450          MFI->hasVarSizedObjects() ||
451          MFI->isFrameAddressTaken() ||
452          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
453          (MMI && MMI->callsUnwindInit()));
454}
455
456bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
457  const MachineFrameInfo *MFI = MF.getFrameInfo();
458  return (RealignStack &&
459          !MFI->hasVarSizedObjects());
460}
461
462bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
463  const MachineFrameInfo *MFI = MF.getFrameInfo();
464  const Function *F = MF.getFunction();
465  bool requiresRealignment =
466    RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
467                     F->hasFnAttr(Attribute::StackAlignment));
468
469  // FIXME: Currently we don't support stack realignment for functions with
470  //        variable-sized allocas.
471  // FIXME: Temporary disable the error - it seems to be too conservative.
472  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
473    llvm_report_error(
474      "Stack realignment in presense of dynamic allocas is not supported");
475
476  return (requiresRealignment && !MFI->hasVarSizedObjects());
477}
478
479bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
480  return !MF.getFrameInfo()->hasVarSizedObjects();
481}
482
483bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
484                                           int &FrameIdx) const {
485  if (Reg == FramePtr && hasFP(MF)) {
486    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
487    return true;
488  }
489  return false;
490}
491
492int
493X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
494  const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
495  const MachineFrameInfo *MFI = MF.getFrameInfo();
496  int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
497  uint64_t StackSize = MFI->getStackSize();
498
499  if (needsStackRealignment(MF)) {
500    if (FI < 0) {
501      // Skip the saved EBP.
502      Offset += SlotSize;
503    } else {
504      unsigned Align = MFI->getObjectAlignment(FI);
505      assert((-(Offset + StackSize)) % Align == 0);
506      Align = 0;
507      return Offset + StackSize;
508    }
509    // FIXME: Support tail calls
510  } else {
511    if (!hasFP(MF))
512      return Offset + StackSize;
513
514    // Skip the saved EBP.
515    Offset += SlotSize;
516
517    // Skip the RETADDR move area
518    const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
519    int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
520    if (TailCallReturnAddrDelta < 0)
521      Offset -= TailCallReturnAddrDelta;
522  }
523
524  return Offset;
525}
526
527void X86RegisterInfo::
528eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
529                              MachineBasicBlock::iterator I) const {
530  if (!hasReservedCallFrame(MF)) {
531    // If the stack pointer can be changed after prologue, turn the
532    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
533    // adjcallstackdown instruction into 'add ESP, <amt>'
534    // TODO: consider using push / pop instead of sub + store / add
535    MachineInstr *Old = I;
536    uint64_t Amount = Old->getOperand(0).getImm();
537    if (Amount != 0) {
538      // We need to keep the stack aligned properly.  To do this, we round the
539      // amount of space needed for the outgoing arguments up to the next
540      // alignment boundary.
541      Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
542
543      MachineInstr *New = 0;
544      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
545        New = BuildMI(MF, Old->getDebugLoc(),
546                      TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
547                      StackPtr)
548          .addReg(StackPtr)
549          .addImm(Amount);
550      } else {
551        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
552
553        // Factor out the amount the callee already popped.
554        uint64_t CalleeAmt = Old->getOperand(1).getImm();
555        Amount -= CalleeAmt;
556
557      if (Amount) {
558          unsigned Opc = (Amount < 128) ?
559            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
560            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
561          New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
562            .addReg(StackPtr)
563            .addImm(Amount);
564        }
565      }
566
567      if (New) {
568        // The EFLAGS implicit def is dead.
569        New->getOperand(3).setIsDead();
570
571        // Replace the pseudo instruction with a new instruction.
572        MBB.insert(I, New);
573      }
574    }
575  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
576    // If we are performing frame pointer elimination and if the callee pops
577    // something off the stack pointer, add it back.  We do this until we have
578    // more advanced stack pointer tracking ability.
579    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
580      unsigned Opc = (CalleeAmt < 128) ?
581        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
582        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
583      MachineInstr *Old = I;
584      MachineInstr *New =
585        BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
586                StackPtr)
587          .addReg(StackPtr)
588          .addImm(CalleeAmt);
589
590      // The EFLAGS implicit def is dead.
591      New->getOperand(3).setIsDead();
592      MBB.insert(I, New);
593    }
594  }
595
596  MBB.erase(I);
597}
598
599unsigned
600X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
601                                     int SPAdj, FrameIndexValue *Value,
602                                     RegScavenger *RS) const{
603  assert(SPAdj == 0 && "Unexpected");
604
605  unsigned i = 0;
606  MachineInstr &MI = *II;
607  MachineFunction &MF = *MI.getParent()->getParent();
608
609  while (!MI.getOperand(i).isFI()) {
610    ++i;
611    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
612  }
613
614  int FrameIndex = MI.getOperand(i).getIndex();
615  unsigned BasePtr;
616
617  if (needsStackRealignment(MF))
618    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
619  else
620    BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
621
622  // This must be part of a four operand memory reference.  Replace the
623  // FrameIndex with base register with EBP.  Add an offset to the offset.
624  MI.getOperand(i).ChangeToRegister(BasePtr, false);
625
626  // Now add the frame object offset to the offset from EBP.
627  if (MI.getOperand(i+3).isImm()) {
628    // Offset is a 32-bit integer.
629    int Offset = getFrameIndexOffset(MF, FrameIndex) +
630      (int)(MI.getOperand(i + 3).getImm());
631
632    MI.getOperand(i + 3).ChangeToImmediate(Offset);
633  } else {
634    // Offset is symbolic. This is extremely rare.
635    uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
636                      (uint64_t)MI.getOperand(i+3).getOffset();
637    MI.getOperand(i+3).setOffset(Offset);
638  }
639  return 0;
640}
641
642void
643X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
644                                                      RegScavenger *RS) const {
645  MachineFrameInfo *MFI = MF.getFrameInfo();
646
647  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
648  int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
649
650  if (TailCallReturnAddrDelta < 0) {
651    // create RETURNADDR area
652    //   arg
653    //   arg
654    //   RETADDR
655    //   { ...
656    //     RETADDR area
657    //     ...
658    //   }
659    //   [EBP]
660    MFI->CreateFixedObject(-TailCallReturnAddrDelta,
661                           (-1U*SlotSize)+TailCallReturnAddrDelta,
662                           true, false);
663  }
664
665  if (hasFP(MF)) {
666    assert((TailCallReturnAddrDelta <= 0) &&
667           "The Delta should always be zero or negative");
668    const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
669
670    // Create a frame entry for the EBP register that must be saved.
671    int FrameIdx = MFI->CreateFixedObject(SlotSize,
672                                          -(int)SlotSize +
673                                          TFI.getOffsetOfLocalArea() +
674                                          TailCallReturnAddrDelta,
675                                          true, false);
676    assert(FrameIdx == MFI->getObjectIndexBegin() &&
677           "Slot for EBP register must be last in order to be found!");
678    FrameIdx = 0;
679  }
680}
681
682/// emitSPUpdate - Emit a series of instructions to increment / decrement the
683/// stack pointer by a constant value.
684static
685void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
686                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
687                  const TargetInstrInfo &TII) {
688  bool isSub = NumBytes < 0;
689  uint64_t Offset = isSub ? -NumBytes : NumBytes;
690  unsigned Opc = isSub
691    ? ((Offset < 128) ?
692       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
693       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
694    : ((Offset < 128) ?
695       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
696       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
697  uint64_t Chunk = (1LL << 31) - 1;
698  DebugLoc DL = MBB.findDebugLoc(MBBI);
699
700  while (Offset) {
701    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
702    MachineInstr *MI =
703      BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
704        .addReg(StackPtr)
705        .addImm(ThisVal);
706    MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
707    Offset -= ThisVal;
708  }
709}
710
711/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
712static
713void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
714                      unsigned StackPtr, uint64_t *NumBytes = NULL) {
715  if (MBBI == MBB.begin()) return;
716
717  MachineBasicBlock::iterator PI = prior(MBBI);
718  unsigned Opc = PI->getOpcode();
719  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
720       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
721      PI->getOperand(0).getReg() == StackPtr) {
722    if (NumBytes)
723      *NumBytes += PI->getOperand(2).getImm();
724    MBB.erase(PI);
725  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
726              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
727             PI->getOperand(0).getReg() == StackPtr) {
728    if (NumBytes)
729      *NumBytes -= PI->getOperand(2).getImm();
730    MBB.erase(PI);
731  }
732}
733
734/// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
735static
736void mergeSPUpdatesDown(MachineBasicBlock &MBB,
737                        MachineBasicBlock::iterator &MBBI,
738                        unsigned StackPtr, uint64_t *NumBytes = NULL) {
739  // FIXME: THIS ISN'T RUN!!!
740  return;
741
742  if (MBBI == MBB.end()) return;
743
744  MachineBasicBlock::iterator NI = llvm::next(MBBI);
745  if (NI == MBB.end()) return;
746
747  unsigned Opc = NI->getOpcode();
748  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
749       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
750      NI->getOperand(0).getReg() == StackPtr) {
751    if (NumBytes)
752      *NumBytes -= NI->getOperand(2).getImm();
753    MBB.erase(NI);
754    MBBI = NI;
755  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
756              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
757             NI->getOperand(0).getReg() == StackPtr) {
758    if (NumBytes)
759      *NumBytes += NI->getOperand(2).getImm();
760    MBB.erase(NI);
761    MBBI = NI;
762  }
763}
764
765/// mergeSPUpdates - Checks the instruction before/after the passed
766/// instruction. If it is an ADD/SUB instruction it is deleted argument and the
767/// stack adjustment is returned as a positive value for ADD and a negative for
768/// SUB.
769static int mergeSPUpdates(MachineBasicBlock &MBB,
770                           MachineBasicBlock::iterator &MBBI,
771                           unsigned StackPtr,
772                           bool doMergeWithPrevious) {
773  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
774      (!doMergeWithPrevious && MBBI == MBB.end()))
775    return 0;
776
777  MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
778  MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
779  unsigned Opc = PI->getOpcode();
780  int Offset = 0;
781
782  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
783       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
784      PI->getOperand(0).getReg() == StackPtr){
785    Offset += PI->getOperand(2).getImm();
786    MBB.erase(PI);
787    if (!doMergeWithPrevious) MBBI = NI;
788  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
789              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
790             PI->getOperand(0).getReg() == StackPtr) {
791    Offset -= PI->getOperand(2).getImm();
792    MBB.erase(PI);
793    if (!doMergeWithPrevious) MBBI = NI;
794  }
795
796  return Offset;
797}
798
799void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
800                                                unsigned LabelId,
801                                                unsigned FramePtr) const {
802  MachineFrameInfo *MFI = MF.getFrameInfo();
803  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
804  if (!MMI) return;
805
806  // Add callee saved registers to move list.
807  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
808  if (CSI.empty()) return;
809
810  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
811  const TargetData *TD = MF.getTarget().getTargetData();
812  bool HasFP = hasFP(MF);
813
814  // Calculate amount of bytes used for return address storing.
815  int stackGrowth =
816    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
817     TargetFrameInfo::StackGrowsUp ?
818     TD->getPointerSize() : -TD->getPointerSize());
819
820  // FIXME: This is dirty hack. The code itself is pretty mess right now.
821  // It should be rewritten from scratch and generalized sometimes.
822
823  // Determine maximum offset (minumum due to stack growth).
824  int64_t MaxOffset = 0;
825  for (std::vector<CalleeSavedInfo>::const_iterator
826         I = CSI.begin(), E = CSI.end(); I != E; ++I)
827    MaxOffset = std::min(MaxOffset,
828                         MFI->getObjectOffset(I->getFrameIdx()));
829
830  // Calculate offsets.
831  int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
832  for (std::vector<CalleeSavedInfo>::const_iterator
833         I = CSI.begin(), E = CSI.end(); I != E; ++I) {
834    int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
835    unsigned Reg = I->getReg();
836    Offset = MaxOffset - Offset + saveAreaOffset;
837
838    // Don't output a new machine move if we're re-saving the frame
839    // pointer. This happens when the PrologEpilogInserter has inserted an extra
840    // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
841    // generates one when frame pointers are used. If we generate a "machine
842    // move" for this extra "PUSH", the linker will lose track of the fact that
843    // the frame pointer should have the value of the first "PUSH" when it's
844    // trying to unwind.
845    //
846    // FIXME: This looks inelegant. It's possibly correct, but it's covering up
847    //        another bug. I.e., one where we generate a prolog like this:
848    //
849    //          pushl  %ebp
850    //          movl   %esp, %ebp
851    //          pushl  %ebp
852    //          pushl  %esi
853    //           ...
854    //
855    //        The immediate re-push of EBP is unnecessary. At the least, it's an
856    //        optimization bug. EBP can be used as a scratch register in certain
857    //        cases, but probably not when we have a frame pointer.
858    if (HasFP && FramePtr == Reg)
859      continue;
860
861    MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
862    MachineLocation CSSrc(Reg);
863    Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
864  }
865}
866
867/// emitPrologue - Push callee-saved registers onto the stack, which
868/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
869/// space for local variables. Also emit labels used by the exception handler to
870/// generate the exception handling frames.
871void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
872  MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
873  MachineBasicBlock::iterator MBBI = MBB.begin();
874  MachineFrameInfo *MFI = MF.getFrameInfo();
875  const Function *Fn = MF.getFunction();
876  const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
877  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
878  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
879  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
880                          !Fn->doesNotThrow() || UnwindTablesMandatory;
881  uint64_t MaxAlign  = MFI->getMaxAlignment(); // Desired stack alignment.
882  uint64_t StackSize = MFI->getStackSize();    // Number of bytes to allocate.
883  bool HasFP = hasFP(MF);
884  DebugLoc DL;
885
886  // Add RETADDR move area to callee saved frame size.
887  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
888  if (TailCallReturnAddrDelta < 0)
889    X86FI->setCalleeSavedFrameSize(
890      X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
891
892  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
893  // function, and use up to 128 bytes of stack space, don't have a frame
894  // pointer, calls, or dynamic alloca then we do not need to adjust the
895  // stack pointer (we fit in the Red Zone).
896  if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
897      !needsStackRealignment(MF) &&
898      !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
899      !MFI->hasCalls() &&                          // No calls.
900      !Subtarget->isTargetWin64()) {               // Win64 has no Red Zone
901    uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
902    if (HasFP) MinSize += SlotSize;
903    StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
904    MFI->setStackSize(StackSize);
905  } else if (Subtarget->isTargetWin64()) {
906    // We need to always allocate 32 bytes as register spill area.
907    // FIXME: We might reuse these 32 bytes for leaf functions.
908    StackSize += 32;
909    MFI->setStackSize(StackSize);
910  }
911
912  // Insert stack pointer adjustment for later moving of return addr.  Only
913  // applies to tail call optimized functions where the callee argument stack
914  // size is bigger than the callers.
915  if (TailCallReturnAddrDelta < 0) {
916    MachineInstr *MI =
917      BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
918              StackPtr)
919        .addReg(StackPtr)
920        .addImm(-TailCallReturnAddrDelta);
921    MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
922  }
923
924  // Mapping for machine moves:
925  //
926  //   DST: VirtualFP AND
927  //        SRC: VirtualFP              => DW_CFA_def_cfa_offset
928  //        ELSE                        => DW_CFA_def_cfa
929  //
930  //   SRC: VirtualFP AND
931  //        DST: Register               => DW_CFA_def_cfa_register
932  //
933  //   ELSE
934  //        OFFSET < 0                  => DW_CFA_offset_extended_sf
935  //        REG < 64                    => DW_CFA_offset + Reg
936  //        ELSE                        => DW_CFA_offset_extended
937
938  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
939  const TargetData *TD = MF.getTarget().getTargetData();
940  uint64_t NumBytes = 0;
941  int stackGrowth = -TD->getPointerSize();
942
943  if (HasFP) {
944    // Calculate required stack adjustment.
945    uint64_t FrameSize = StackSize - SlotSize;
946    if (needsStackRealignment(MF))
947      FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
948
949    NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
950
951    // Get the offset of the stack slot for the EBP register, which is
952    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
953    // Update the frame offset adjustment.
954    MFI->setOffsetAdjustment(-NumBytes);
955
956    // Save EBP/RBP into the appropriate stack slot.
957    BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
958      .addReg(FramePtr, RegState::Kill);
959
960    if (needsFrameMoves) {
961      // Mark the place where EBP/RBP was saved.
962      unsigned FrameLabelId = MMI->NextLabelID();
963      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL))
964        .addSym(MMI->getLabelSym(FrameLabelId));
965
966      // Define the current CFA rule to use the provided offset.
967      if (StackSize) {
968        MachineLocation SPDst(MachineLocation::VirtualFP);
969        MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
970        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
971      } else {
972        // FIXME: Verify & implement for FP
973        MachineLocation SPDst(StackPtr);
974        MachineLocation SPSrc(StackPtr, stackGrowth);
975        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
976      }
977
978      // Change the rule for the FramePtr to be an "offset" rule.
979      MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
980      MachineLocation FPSrc(FramePtr);
981      Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
982    }
983
984    // Update EBP with the new base value...
985    BuildMI(MBB, MBBI, DL,
986            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
987        .addReg(StackPtr);
988
989    if (needsFrameMoves) {
990      // Mark effective beginning of when frame pointer becomes valid.
991      unsigned FrameLabelId = MMI->NextLabelID();
992      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL))
993        .addSym(MMI->getLabelSym(FrameLabelId));
994
995      // Define the current CFA to use the EBP/RBP register.
996      MachineLocation FPDst(FramePtr);
997      MachineLocation FPSrc(MachineLocation::VirtualFP);
998      Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
999    }
1000
1001    // Mark the FramePtr as live-in in every block except the entry.
1002    for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1003         I != E; ++I)
1004      I->addLiveIn(FramePtr);
1005
1006    // Realign stack
1007    if (needsStackRealignment(MF)) {
1008      MachineInstr *MI =
1009        BuildMI(MBB, MBBI, DL,
1010                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1011                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1012
1013      // The EFLAGS implicit def is dead.
1014      MI->getOperand(3).setIsDead();
1015    }
1016  } else {
1017    NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1018  }
1019
1020  // Skip the callee-saved push instructions.
1021  bool PushedRegs = false;
1022  int StackOffset = 2 * stackGrowth;
1023
1024  while (MBBI != MBB.end() &&
1025         (MBBI->getOpcode() == X86::PUSH32r ||
1026          MBBI->getOpcode() == X86::PUSH64r)) {
1027    PushedRegs = true;
1028    ++MBBI;
1029
1030    if (!HasFP && needsFrameMoves) {
1031      // Mark callee-saved push instruction.
1032      unsigned LabelId = MMI->NextLabelID();
1033      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL))
1034        .addSym(MMI->getLabelSym(LabelId));
1035
1036      // Define the current CFA rule to use the provided offset.
1037      unsigned Ptr = StackSize ?
1038        MachineLocation::VirtualFP : StackPtr;
1039      MachineLocation SPDst(Ptr);
1040      MachineLocation SPSrc(Ptr, StackOffset);
1041      Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1042      StackOffset += stackGrowth;
1043    }
1044  }
1045
1046  DL = MBB.findDebugLoc(MBBI);
1047
1048  // Adjust stack pointer: ESP -= numbytes.
1049  if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1050    // Check, whether EAX is livein for this function.
1051    bool isEAXAlive = false;
1052    for (MachineRegisterInfo::livein_iterator
1053           II = MF.getRegInfo().livein_begin(),
1054           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1055      unsigned Reg = II->first;
1056      isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1057                    Reg == X86::AH || Reg == X86::AL);
1058    }
1059
1060    // Function prologue calls _alloca to probe the stack when allocating more
1061    // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1062    // to ensure that the guard pages used by the OS virtual memory manager are
1063    // allocated in correct sequence.
1064    if (!isEAXAlive) {
1065      BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1066        .addImm(NumBytes);
1067      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1068        .addExternalSymbol("_alloca")
1069        .addReg(StackPtr, RegState::Define | RegState::Implicit);
1070    } else {
1071      // Save EAX
1072      BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1073        .addReg(X86::EAX, RegState::Kill);
1074
1075      // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1076      // allocated bytes for EAX.
1077      BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1078        .addImm(NumBytes - 4);
1079      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1080        .addExternalSymbol("_alloca")
1081        .addReg(StackPtr, RegState::Define | RegState::Implicit);
1082
1083      // Restore EAX
1084      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1085                                              X86::EAX),
1086                                      StackPtr, false, NumBytes - 4);
1087      MBB.insert(MBBI, MI);
1088    }
1089  } else if (NumBytes) {
1090    // If there is an SUB32ri of ESP immediately before this instruction, merge
1091    // the two. This can be the case when tail call elimination is enabled and
1092    // the callee has more arguments then the caller.
1093    NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1094
1095    // If there is an ADD32ri or SUB32ri of ESP immediately after this
1096    // instruction, merge the two instructions.
1097    mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1098
1099    if (NumBytes)
1100      emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1101  }
1102
1103  if ((NumBytes || PushedRegs) && needsFrameMoves) {
1104    // Mark end of stack pointer adjustment.
1105    unsigned LabelId = MMI->NextLabelID();
1106    BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL))
1107      .addSym(MMI->getLabelSym(LabelId));
1108
1109    if (!HasFP && NumBytes) {
1110      // Define the current CFA rule to use the provided offset.
1111      if (StackSize) {
1112        MachineLocation SPDst(MachineLocation::VirtualFP);
1113        MachineLocation SPSrc(MachineLocation::VirtualFP,
1114                              -StackSize + stackGrowth);
1115        Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1116      } else {
1117        // FIXME: Verify & implement for FP
1118        MachineLocation SPDst(StackPtr);
1119        MachineLocation SPSrc(StackPtr, stackGrowth);
1120        Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1121      }
1122    }
1123
1124    // Emit DWARF info specifying the offsets of the callee-saved registers.
1125    if (PushedRegs)
1126      emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1127  }
1128}
1129
1130void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1131                                   MachineBasicBlock &MBB) const {
1132  const MachineFrameInfo *MFI = MF.getFrameInfo();
1133  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1134  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1135  unsigned RetOpcode = MBBI->getOpcode();
1136  DebugLoc DL = MBBI->getDebugLoc();
1137
1138  switch (RetOpcode) {
1139  default:
1140    llvm_unreachable("Can only insert epilog into returning blocks");
1141  case X86::RET:
1142  case X86::RETI:
1143  case X86::TCRETURNdi:
1144  case X86::TCRETURNri:
1145  case X86::TCRETURNmi:
1146  case X86::TCRETURNdi64:
1147  case X86::TCRETURNri64:
1148  case X86::TCRETURNmi64:
1149  case X86::EH_RETURN:
1150  case X86::EH_RETURN64:
1151    break;  // These are ok
1152  }
1153
1154  // Get the number of bytes to allocate from the FrameInfo.
1155  uint64_t StackSize = MFI->getStackSize();
1156  uint64_t MaxAlign  = MFI->getMaxAlignment();
1157  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1158  uint64_t NumBytes = 0;
1159
1160  if (hasFP(MF)) {
1161    // Calculate required stack adjustment.
1162    uint64_t FrameSize = StackSize - SlotSize;
1163    if (needsStackRealignment(MF))
1164      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1165
1166    NumBytes = FrameSize - CSSize;
1167
1168    // Pop EBP.
1169    BuildMI(MBB, MBBI, DL,
1170            TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1171  } else {
1172    NumBytes = StackSize - CSSize;
1173  }
1174
1175  // Skip the callee-saved pop instructions.
1176  MachineBasicBlock::iterator LastCSPop = MBBI;
1177  while (MBBI != MBB.begin()) {
1178    MachineBasicBlock::iterator PI = prior(MBBI);
1179    unsigned Opc = PI->getOpcode();
1180
1181    if (Opc != X86::POP32r && Opc != X86::POP64r &&
1182        !PI->getDesc().isTerminator())
1183      break;
1184
1185    --MBBI;
1186  }
1187
1188  DL = MBBI->getDebugLoc();
1189
1190  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1191  // instruction, merge the two instructions.
1192  if (NumBytes || MFI->hasVarSizedObjects())
1193    mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1194
1195  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1196  // slot before popping them off! Same applies for the case, when stack was
1197  // realigned.
1198  if (needsStackRealignment(MF)) {
1199    // We cannot use LEA here, because stack pointer was realigned. We need to
1200    // deallocate local frame back.
1201    if (CSSize) {
1202      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1203      MBBI = prior(LastCSPop);
1204    }
1205
1206    BuildMI(MBB, MBBI, DL,
1207            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1208            StackPtr).addReg(FramePtr);
1209  } else if (MFI->hasVarSizedObjects()) {
1210    if (CSSize) {
1211      unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1212      MachineInstr *MI =
1213        addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1214                        FramePtr, false, -CSSize);
1215      MBB.insert(MBBI, MI);
1216    } else {
1217      BuildMI(MBB, MBBI, DL,
1218              TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1219        .addReg(FramePtr);
1220    }
1221  } else if (NumBytes) {
1222    // Adjust stack pointer back: ESP += numbytes.
1223    emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1224  }
1225
1226  // We're returning from function via eh_return.
1227  if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1228    MBBI = prior(MBB.end());
1229    MachineOperand &DestAddr  = MBBI->getOperand(0);
1230    assert(DestAddr.isReg() && "Offset should be in register!");
1231    BuildMI(MBB, MBBI, DL,
1232            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1233            StackPtr).addReg(DestAddr.getReg());
1234  } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1235             RetOpcode == X86::TCRETURNmi ||
1236             RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1237             RetOpcode == X86::TCRETURNmi64) {
1238    bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1239    // Tail call return: adjust the stack pointer and jump to callee.
1240    MBBI = prior(MBB.end());
1241    MachineOperand &JumpTarget = MBBI->getOperand(0);
1242    MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1243    assert(StackAdjust.isImm() && "Expecting immediate value.");
1244
1245    // Adjust stack pointer.
1246    int StackAdj = StackAdjust.getImm();
1247    int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1248    int Offset = 0;
1249    assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1250
1251    // Incoporate the retaddr area.
1252    Offset = StackAdj-MaxTCDelta;
1253    assert(Offset >= 0 && "Offset should never be negative");
1254
1255    if (Offset) {
1256      // Check for possible merge with preceeding ADD instruction.
1257      Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1258      emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1259    }
1260
1261    // Jump to label or value in register.
1262    if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1263      BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1264                                     ? X86::TAILJMPd : X86::TAILJMPd64)).
1265        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1266                         JumpTarget.getTargetFlags());
1267    } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1268      MachineInstrBuilder MIB =
1269        BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1270                                       ? X86::TAILJMPm : X86::TAILJMPm64));
1271      for (unsigned i = 0; i != 5; ++i)
1272        MIB.addOperand(MBBI->getOperand(i));
1273    } else if (RetOpcode == X86::TCRETURNri64) {
1274      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1275    } else {
1276      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1277    }
1278
1279    MachineInstr *NewMI = prior(MBBI);
1280    for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1281      NewMI->addOperand(MBBI->getOperand(i));
1282
1283    // Delete the pseudo instruction TCRETURN.
1284    MBB.erase(MBBI);
1285  } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1286             (X86FI->getTCReturnAddrDelta() < 0)) {
1287    // Add the return addr area delta back since we are not tail calling.
1288    int delta = -1*X86FI->getTCReturnAddrDelta();
1289    MBBI = prior(MBB.end());
1290
1291    // Check for possible merge with preceeding ADD instruction.
1292    delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1293    emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1294  }
1295}
1296
1297unsigned X86RegisterInfo::getRARegister() const {
1298  return Is64Bit ? X86::RIP     // Should have dwarf #16.
1299                 : X86::EIP;    // Should have dwarf #8.
1300}
1301
1302unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1303  return hasFP(MF) ? FramePtr : StackPtr;
1304}
1305
1306void
1307X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1308  // Calculate amount of bytes used for return address storing
1309  int stackGrowth = (Is64Bit ? -8 : -4);
1310
1311  // Initial state of the frame pointer is esp+4.
1312  MachineLocation Dst(MachineLocation::VirtualFP);
1313  MachineLocation Src(StackPtr, stackGrowth);
1314  Moves.push_back(MachineMove(0, Dst, Src));
1315
1316  // Add return address to move list
1317  MachineLocation CSDst(StackPtr, stackGrowth);
1318  MachineLocation CSSrc(getRARegister());
1319  Moves.push_back(MachineMove(0, CSDst, CSSrc));
1320}
1321
1322unsigned X86RegisterInfo::getEHExceptionRegister() const {
1323  llvm_unreachable("What is the exception register");
1324  return 0;
1325}
1326
1327unsigned X86RegisterInfo::getEHHandlerRegister() const {
1328  llvm_unreachable("What is the exception handler register");
1329  return 0;
1330}
1331
1332namespace llvm {
1333unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1334  switch (VT.getSimpleVT().SimpleTy) {
1335  default: return Reg;
1336  case MVT::i8:
1337    if (High) {
1338      switch (Reg) {
1339      default: return 0;
1340      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1341        return X86::AH;
1342      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1343        return X86::DH;
1344      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1345        return X86::CH;
1346      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1347        return X86::BH;
1348      }
1349    } else {
1350      switch (Reg) {
1351      default: return 0;
1352      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1353        return X86::AL;
1354      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1355        return X86::DL;
1356      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1357        return X86::CL;
1358      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1359        return X86::BL;
1360      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1361        return X86::SIL;
1362      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1363        return X86::DIL;
1364      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1365        return X86::BPL;
1366      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1367        return X86::SPL;
1368      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1369        return X86::R8B;
1370      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1371        return X86::R9B;
1372      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1373        return X86::R10B;
1374      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1375        return X86::R11B;
1376      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1377        return X86::R12B;
1378      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1379        return X86::R13B;
1380      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1381        return X86::R14B;
1382      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1383        return X86::R15B;
1384      }
1385    }
1386  case MVT::i16:
1387    switch (Reg) {
1388    default: return Reg;
1389    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1390      return X86::AX;
1391    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1392      return X86::DX;
1393    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1394      return X86::CX;
1395    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1396      return X86::BX;
1397    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1398      return X86::SI;
1399    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1400      return X86::DI;
1401    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1402      return X86::BP;
1403    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1404      return X86::SP;
1405    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1406      return X86::R8W;
1407    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1408      return X86::R9W;
1409    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1410      return X86::R10W;
1411    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1412      return X86::R11W;
1413    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1414      return X86::R12W;
1415    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1416      return X86::R13W;
1417    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1418      return X86::R14W;
1419    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1420      return X86::R15W;
1421    }
1422  case MVT::i32:
1423    switch (Reg) {
1424    default: return Reg;
1425    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1426      return X86::EAX;
1427    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1428      return X86::EDX;
1429    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1430      return X86::ECX;
1431    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1432      return X86::EBX;
1433    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1434      return X86::ESI;
1435    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1436      return X86::EDI;
1437    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1438      return X86::EBP;
1439    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1440      return X86::ESP;
1441    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1442      return X86::R8D;
1443    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1444      return X86::R9D;
1445    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1446      return X86::R10D;
1447    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1448      return X86::R11D;
1449    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1450      return X86::R12D;
1451    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1452      return X86::R13D;
1453    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1454      return X86::R14D;
1455    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1456      return X86::R15D;
1457    }
1458  case MVT::i64:
1459    switch (Reg) {
1460    default: return Reg;
1461    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1462      return X86::RAX;
1463    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1464      return X86::RDX;
1465    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1466      return X86::RCX;
1467    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1468      return X86::RBX;
1469    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1470      return X86::RSI;
1471    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1472      return X86::RDI;
1473    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1474      return X86::RBP;
1475    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1476      return X86::RSP;
1477    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1478      return X86::R8;
1479    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1480      return X86::R9;
1481    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1482      return X86::R10;
1483    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1484      return X86::R11;
1485    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1486      return X86::R12;
1487    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1488      return X86::R13;
1489    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1490      return X86::R14;
1491    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1492      return X86::R15;
1493    }
1494  }
1495
1496  return Reg;
1497}
1498}
1499
1500#include "X86GenRegisterInfo.inc"
1501