X86RegisterInfo.cpp revision 718cb665ca6ce2bc4d8e8479f46a45db91b49f86 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineLocation.h"
29#include "llvm/Target/TargetAsmInfo.h"
30#include "llvm/Target/TargetFrameInfo.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetOptions.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/ADT/BitVector.h"
36#include "llvm/ADT/STLExtras.h"
37using namespace llvm;
38
39namespace {
40  cl::opt<bool>
41  NoFusing("disable-spill-fusing",
42           cl::desc("Disable fusing of spill code into instructions"));
43  cl::opt<bool>
44  PrintFailedFusing("print-failed-fuse-candidates",
45                    cl::desc("Print instructions that the allocator wants to"
46                             " fuse, but the X86 backend currently can't"),
47                    cl::Hidden);
48}
49
50X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51                                 const TargetInstrInfo &tii)
52  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
53    TM(tm), TII(tii) {
54  // Cache some information.
55  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
56  Is64Bit = Subtarget->is64Bit();
57  if (Is64Bit) {
58    SlotSize = 8;
59    StackPtr = X86::RSP;
60    FramePtr = X86::RBP;
61  } else {
62    SlotSize = 4;
63    StackPtr = X86::ESP;
64    FramePtr = X86::EBP;
65  }
66}
67
68// getX86RegNum - This function maps LLVM register identifiers to their X86
69// specific numbering, which is used in various places encoding instructions.
70//
71unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
72  switch(RegNo) {
73  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
74  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
75  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
76  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
77  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
78    return N86::ESP;
79  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
80    return N86::EBP;
81  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
82    return N86::ESI;
83  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
84    return N86::EDI;
85
86  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
87    return N86::EAX;
88  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
89    return N86::ECX;
90  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
91    return N86::EDX;
92  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
93    return N86::EBX;
94  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
95    return N86::ESP;
96  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
97    return N86::EBP;
98  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
99    return N86::ESI;
100  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
101    return N86::EDI;
102
103  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
104  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
105    return RegNo-X86::ST0;
106
107  case X86::XMM0:  case X86::XMM1:  case X86::XMM2:  case X86::XMM3:
108  case X86::XMM4:  case X86::XMM5:  case X86::XMM6:  case X86::XMM7:
109    return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0);
110  case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
111  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
112    return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8);
113
114  default:
115    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
116    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
117    return 0;
118  }
119}
120
121bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
122                                                MachineBasicBlock::iterator MI,
123                                const std::vector<CalleeSavedInfo> &CSI) const {
124  if (CSI.empty())
125    return false;
126
127  MachineFunction &MF = *MBB.getParent();
128  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
129  X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
130  unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
131  for (unsigned i = CSI.size(); i != 0; --i) {
132    unsigned Reg = CSI[i-1].getReg();
133    // Add the callee-saved register as live-in. It's killed at the spill.
134    MBB.addLiveIn(Reg);
135    BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg);
136  }
137  return true;
138}
139
140bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
141                                                 MachineBasicBlock::iterator MI,
142                                const std::vector<CalleeSavedInfo> &CSI) const {
143  if (CSI.empty())
144    return false;
145
146  unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r;
147  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
148    unsigned Reg = CSI[i].getReg();
149    BuildMI(MBB, MI, TII.get(Opc), Reg);
150  }
151  return true;
152}
153
154void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
155                                          MachineBasicBlock::iterator MI,
156                                          unsigned SrcReg, int FrameIdx,
157                                          const TargetRegisterClass *RC) const {
158  unsigned Opc;
159  if (RC == &X86::GR64RegClass) {
160    Opc = X86::MOV64mr;
161  } else if (RC == &X86::GR32RegClass) {
162    Opc = X86::MOV32mr;
163  } else if (RC == &X86::GR16RegClass) {
164    Opc = X86::MOV16mr;
165  } else if (RC == &X86::GR8RegClass) {
166    Opc = X86::MOV8mr;
167  } else if (RC == &X86::GR32_RegClass) {
168    Opc = X86::MOV32_mr;
169  } else if (RC == &X86::GR16_RegClass) {
170    Opc = X86::MOV16_mr;
171  } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) {
172    Opc = X86::ST_Fp64m;
173  } else if (RC == &X86::RFP32RegClass) {
174    Opc = X86::ST_Fp32m;
175  } else if (RC == &X86::FR32RegClass) {
176    Opc = X86::MOVSSmr;
177  } else if (RC == &X86::FR64RegClass) {
178    Opc = X86::MOVSDmr;
179  } else if (RC == &X86::VR128RegClass) {
180    Opc = X86::MOVAPSmr;
181  } else if (RC == &X86::VR64RegClass) {
182    Opc = X86::MMX_MOVQ64mr;
183  } else {
184    assert(0 && "Unknown regclass");
185    abort();
186  }
187  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
188    .addReg(SrcReg, false, false, true);
189}
190
191void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
192                                           MachineBasicBlock::iterator MI,
193                                           unsigned DestReg, int FrameIdx,
194                                           const TargetRegisterClass *RC) const{
195  unsigned Opc;
196  if (RC == &X86::GR64RegClass) {
197    Opc = X86::MOV64rm;
198  } else if (RC == &X86::GR32RegClass) {
199    Opc = X86::MOV32rm;
200  } else if (RC == &X86::GR16RegClass) {
201    Opc = X86::MOV16rm;
202  } else if (RC == &X86::GR8RegClass) {
203    Opc = X86::MOV8rm;
204  } else if (RC == &X86::GR32_RegClass) {
205    Opc = X86::MOV32_rm;
206  } else if (RC == &X86::GR16_RegClass) {
207    Opc = X86::MOV16_rm;
208  } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) {
209    Opc = X86::LD_Fp64m;
210  } else if (RC == &X86::RFP32RegClass) {
211    Opc = X86::LD_Fp32m;
212  } else if (RC == &X86::FR32RegClass) {
213    Opc = X86::MOVSSrm;
214  } else if (RC == &X86::FR64RegClass) {
215    Opc = X86::MOVSDrm;
216  } else if (RC == &X86::VR128RegClass) {
217    Opc = X86::MOVAPSrm;
218  } else if (RC == &X86::VR64RegClass) {
219    Opc = X86::MMX_MOVQ64rm;
220  } else {
221    assert(0 && "Unknown regclass");
222    abort();
223  }
224  addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
225}
226
227void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
228                                   MachineBasicBlock::iterator MI,
229                                   unsigned DestReg, unsigned SrcReg,
230                                   const TargetRegisterClass *RC) const {
231  unsigned Opc;
232  if (RC == &X86::GR64RegClass) {
233    Opc = X86::MOV64rr;
234  } else if (RC == &X86::GR32RegClass) {
235    Opc = X86::MOV32rr;
236  } else if (RC == &X86::GR16RegClass) {
237    Opc = X86::MOV16rr;
238  } else if (RC == &X86::GR8RegClass) {
239    Opc = X86::MOV8rr;
240  } else if (RC == &X86::GR32_RegClass) {
241    Opc = X86::MOV32_rr;
242  } else if (RC == &X86::GR16_RegClass) {
243    Opc = X86::MOV16_rr;
244  } else if (RC == &X86::RFP32RegClass) {
245    Opc = X86::MOV_Fp3232;
246  } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) {
247    Opc = X86::MOV_Fp6464;
248  } else if (RC == &X86::FR32RegClass) {
249    Opc = X86::FsMOVAPSrr;
250  } else if (RC == &X86::FR64RegClass) {
251    Opc = X86::FsMOVAPDrr;
252  } else if (RC == &X86::VR128RegClass) {
253    Opc = X86::MOVAPSrr;
254  } else if (RC == &X86::VR64RegClass) {
255    Opc = X86::MMX_MOVQ64rr;
256  } else {
257    assert(0 && "Unknown regclass");
258    abort();
259  }
260  BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
261}
262
263
264void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
265                                    MachineBasicBlock::iterator I,
266                                    unsigned DestReg,
267                                    const MachineInstr *Orig) const {
268  MachineInstr *MI = Orig->clone();
269  MI->getOperand(0).setReg(DestReg);
270  MBB.insert(I, MI);
271}
272
273static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB,
274                                                      MachineOperand &MO) {
275  if (MO.isReg())
276    MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
277  else if (MO.isImm())
278    MIB = MIB.addImm(MO.getImm());
279  else if (MO.isFrameIndex())
280    MIB = MIB.addFrameIndex(MO.getFrameIndex());
281  else if (MO.isGlobalAddress())
282    MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
283  else if (MO.isConstantPoolIndex())
284    MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset());
285  else if (MO.isJumpTableIndex())
286    MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
287  else if (MO.isExternalSymbol())
288    MIB = MIB.addExternalSymbol(MO.getSymbolName());
289  else
290    assert(0 && "Unknown operand for FuseInst!");
291
292  return MIB;
293}
294
295static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
296                                     SmallVector<MachineOperand,4> &MOs,
297                                 MachineInstr *MI, const TargetInstrInfo &TII) {
298  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
299
300  // Create the base instruction with the memory operand as the first part.
301  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
302  unsigned NumAddrOps = MOs.size();
303  for (unsigned i = 0; i != NumAddrOps; ++i)
304    MIB = FuseInstrAddOperand(MIB, MOs[i]);
305  if (NumAddrOps < 4)  // FrameIndex only
306    MIB.addImm(1).addReg(0).addImm(0);
307
308  // Loop over the rest of the ri operands, converting them over.
309  for (unsigned i = 0; i != NumOps; ++i) {
310    MachineOperand &MO = MI->getOperand(i+2);
311    MIB = FuseInstrAddOperand(MIB, MO);
312  }
313  return MIB;
314}
315
316static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
317                              SmallVector<MachineOperand,4> &MOs,
318                              MachineInstr *MI, const TargetInstrInfo &TII) {
319  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
320
321  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
322    MachineOperand &MO = MI->getOperand(i);
323    if (i == OpNo) {
324      assert(MO.isReg() && "Expected to fold into reg operand!");
325      unsigned NumAddrOps = MOs.size();
326      for (unsigned i = 0; i != NumAddrOps; ++i)
327        MIB = FuseInstrAddOperand(MIB, MOs[i]);
328      if (NumAddrOps < 4)  // FrameIndex only
329        MIB.addImm(1).addReg(0).addImm(0);
330    } else {
331      MIB = FuseInstrAddOperand(MIB, MO);
332    }
333  }
334  return MIB;
335}
336
337static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
338                                SmallVector<MachineOperand,4> &MOs,
339                                MachineInstr *MI) {
340  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
341
342  unsigned NumAddrOps = MOs.size();
343  for (unsigned i = 0; i != NumAddrOps; ++i)
344    MIB = FuseInstrAddOperand(MIB, MOs[i]);
345  if (NumAddrOps < 4)  // FrameIndex only
346    MIB.addImm(1).addReg(0).addImm(0);
347  return MIB.addImm(0);
348}
349
350
351//===----------------------------------------------------------------------===//
352// Efficient Lookup Table Support
353//===----------------------------------------------------------------------===//
354
355namespace {
356  /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
357  ///
358  struct TableEntry {
359    unsigned from;                      // Original opcode.
360    unsigned to;                        // New opcode.
361
362    // less operators used by STL search.
363    bool operator<(const TableEntry &TE) const { return from < TE.from; }
364    friend bool operator<(const TableEntry &TE, unsigned V) {
365      return TE.from < V;
366    }
367    friend bool operator<(unsigned V, const TableEntry &TE) {
368      return V < TE.from;
369    }
370  };
371}
372
373/// TableIsSorted - Return true if the table is in 'from' opcode order.
374///
375static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
376  for (unsigned i = 1; i != NumEntries; ++i)
377    if (!(Table[i-1] < Table[i])) {
378      cerr << "Entries out of order " << Table[i-1].from
379           << " " << Table[i].from << "\n";
380      return false;
381    }
382  return true;
383}
384
385/// TableLookup - Return the table entry matching the specified opcode.
386/// Otherwise return NULL.
387static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
388                                unsigned Opcode) {
389  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
390  if (I != Table+N && I->from == Opcode)
391    return I;
392  return NULL;
393}
394
395#ifdef NDEBUG
396#define ASSERT_SORTED(TABLE)
397#else
398#define ASSERT_SORTED(TABLE)                                              \
399  { static bool TABLE##Checked = false;                                   \
400    if (!TABLE##Checked) {                                                \
401       assert(TableIsSorted(TABLE, array_lengthof(TABLE)) &&              \
402              "All lookup tables must be sorted for efficient access!");  \
403       TABLE##Checked = true;                                             \
404    }                                                                     \
405  }
406#endif
407
408MachineInstr*
409X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
410                                   SmallVector<MachineOperand,4> &MOs) const {
411  // Table (and size) to search
412  const TableEntry *OpcodeTablePtr = NULL;
413  unsigned OpcodeTableSize = 0;
414  bool isTwoAddrFold = false;
415  unsigned NumOps = TII.getNumOperands(MI->getOpcode());
416  bool isTwoAddr = NumOps > 1 &&
417    MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
418
419  MachineInstr *NewMI = NULL;
420  // Folding a memory location into the two-address part of a two-address
421  // instruction is different than folding it other places.  It requires
422  // replacing the *two* registers with the memory location.
423  if (isTwoAddr && NumOps >= 2 && i < 2 &&
424      MI->getOperand(0).isReg() &&
425      MI->getOperand(1).isReg() &&
426      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
427    static const TableEntry OpcodeTable[] = {
428      { X86::ADC32ri,     X86::ADC32mi },
429      { X86::ADC32ri8,    X86::ADC32mi8 },
430      { X86::ADC32rr,     X86::ADC32mr },
431      { X86::ADC64ri32,   X86::ADC64mi32 },
432      { X86::ADC64ri8,    X86::ADC64mi8 },
433      { X86::ADC64rr,     X86::ADC64mr },
434      { X86::ADD16ri,     X86::ADD16mi },
435      { X86::ADD16ri8,    X86::ADD16mi8 },
436      { X86::ADD16rr,     X86::ADD16mr },
437      { X86::ADD32ri,     X86::ADD32mi },
438      { X86::ADD32ri8,    X86::ADD32mi8 },
439      { X86::ADD32rr,     X86::ADD32mr },
440      { X86::ADD64ri32,   X86::ADD64mi32 },
441      { X86::ADD64ri8,    X86::ADD64mi8 },
442      { X86::ADD64rr,     X86::ADD64mr },
443      { X86::ADD8ri,      X86::ADD8mi },
444      { X86::ADD8rr,      X86::ADD8mr },
445      { X86::AND16ri,     X86::AND16mi },
446      { X86::AND16ri8,    X86::AND16mi8 },
447      { X86::AND16rr,     X86::AND16mr },
448      { X86::AND32ri,     X86::AND32mi },
449      { X86::AND32ri8,    X86::AND32mi8 },
450      { X86::AND32rr,     X86::AND32mr },
451      { X86::AND64ri32,   X86::AND64mi32 },
452      { X86::AND64ri8,    X86::AND64mi8 },
453      { X86::AND64rr,     X86::AND64mr },
454      { X86::AND8ri,      X86::AND8mi },
455      { X86::AND8rr,      X86::AND8mr },
456      { X86::DEC16r,      X86::DEC16m },
457      { X86::DEC32r,      X86::DEC32m },
458      { X86::DEC64_16r,   X86::DEC16m },
459      { X86::DEC64_32r,   X86::DEC32m },
460      { X86::DEC64r,      X86::DEC64m },
461      { X86::DEC8r,       X86::DEC8m },
462      { X86::INC16r,      X86::INC16m },
463      { X86::INC32r,      X86::INC32m },
464      { X86::INC64_16r,   X86::INC16m },
465      { X86::INC64_32r,   X86::INC32m },
466      { X86::INC64r,      X86::INC64m },
467      { X86::INC8r,       X86::INC8m },
468      { X86::NEG16r,      X86::NEG16m },
469      { X86::NEG32r,      X86::NEG32m },
470      { X86::NEG64r,      X86::NEG64m },
471      { X86::NEG8r,       X86::NEG8m },
472      { X86::NOT16r,      X86::NOT16m },
473      { X86::NOT32r,      X86::NOT32m },
474      { X86::NOT64r,      X86::NOT64m },
475      { X86::NOT8r,       X86::NOT8m },
476      { X86::OR16ri,      X86::OR16mi },
477      { X86::OR16ri8,     X86::OR16mi8 },
478      { X86::OR16rr,      X86::OR16mr },
479      { X86::OR32ri,      X86::OR32mi },
480      { X86::OR32ri8,     X86::OR32mi8 },
481      { X86::OR32rr,      X86::OR32mr },
482      { X86::OR64ri32,    X86::OR64mi32 },
483      { X86::OR64ri8,     X86::OR64mi8 },
484      { X86::OR64rr,      X86::OR64mr },
485      { X86::OR8ri,       X86::OR8mi },
486      { X86::OR8rr,       X86::OR8mr },
487      { X86::ROL16r1,     X86::ROL16m1 },
488      { X86::ROL16rCL,    X86::ROL16mCL },
489      { X86::ROL16ri,     X86::ROL16mi },
490      { X86::ROL32r1,     X86::ROL32m1 },
491      { X86::ROL32rCL,    X86::ROL32mCL },
492      { X86::ROL32ri,     X86::ROL32mi },
493      { X86::ROL64r1,     X86::ROL64m1 },
494      { X86::ROL64rCL,    X86::ROL64mCL },
495      { X86::ROL64ri,     X86::ROL64mi },
496      { X86::ROL8r1,      X86::ROL8m1 },
497      { X86::ROL8rCL,     X86::ROL8mCL },
498      { X86::ROL8ri,      X86::ROL8mi },
499      { X86::ROR16r1,     X86::ROR16m1 },
500      { X86::ROR16rCL,    X86::ROR16mCL },
501      { X86::ROR16ri,     X86::ROR16mi },
502      { X86::ROR32r1,     X86::ROR32m1 },
503      { X86::ROR32rCL,    X86::ROR32mCL },
504      { X86::ROR32ri,     X86::ROR32mi },
505      { X86::ROR64r1,     X86::ROR64m1 },
506      { X86::ROR64rCL,    X86::ROR64mCL },
507      { X86::ROR64ri,     X86::ROR64mi },
508      { X86::ROR8r1,      X86::ROR8m1 },
509      { X86::ROR8rCL,     X86::ROR8mCL },
510      { X86::ROR8ri,      X86::ROR8mi },
511      { X86::SAR16r1,     X86::SAR16m1 },
512      { X86::SAR16rCL,    X86::SAR16mCL },
513      { X86::SAR16ri,     X86::SAR16mi },
514      { X86::SAR32r1,     X86::SAR32m1 },
515      { X86::SAR32rCL,    X86::SAR32mCL },
516      { X86::SAR32ri,     X86::SAR32mi },
517      { X86::SAR64r1,     X86::SAR64m1 },
518      { X86::SAR64rCL,    X86::SAR64mCL },
519      { X86::SAR64ri,     X86::SAR64mi },
520      { X86::SAR8r1,      X86::SAR8m1 },
521      { X86::SAR8rCL,     X86::SAR8mCL },
522      { X86::SAR8ri,      X86::SAR8mi },
523      { X86::SBB32ri,     X86::SBB32mi },
524      { X86::SBB32ri8,    X86::SBB32mi8 },
525      { X86::SBB32rr,     X86::SBB32mr },
526      { X86::SBB64ri32,   X86::SBB64mi32 },
527      { X86::SBB64ri8,    X86::SBB64mi8 },
528      { X86::SBB64rr,     X86::SBB64mr },
529      { X86::SHL16r1,     X86::SHL16m1 },
530      { X86::SHL16rCL,    X86::SHL16mCL },
531      { X86::SHL16ri,     X86::SHL16mi },
532      { X86::SHL32r1,     X86::SHL32m1 },
533      { X86::SHL32rCL,    X86::SHL32mCL },
534      { X86::SHL32ri,     X86::SHL32mi },
535      { X86::SHL64r1,     X86::SHL64m1 },
536      { X86::SHL64rCL,    X86::SHL64mCL },
537      { X86::SHL64ri,     X86::SHL64mi },
538      { X86::SHL8r1,      X86::SHL8m1 },
539      { X86::SHL8rCL,     X86::SHL8mCL },
540      { X86::SHL8ri,      X86::SHL8mi },
541      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
542      { X86::SHLD16rri8,  X86::SHLD16mri8 },
543      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
544      { X86::SHLD32rri8,  X86::SHLD32mri8 },
545      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
546      { X86::SHLD64rri8,  X86::SHLD64mri8 },
547      { X86::SHR16r1,     X86::SHR16m1 },
548      { X86::SHR16rCL,    X86::SHR16mCL },
549      { X86::SHR16ri,     X86::SHR16mi },
550      { X86::SHR32r1,     X86::SHR32m1 },
551      { X86::SHR32rCL,    X86::SHR32mCL },
552      { X86::SHR32ri,     X86::SHR32mi },
553      { X86::SHR64r1,     X86::SHR64m1 },
554      { X86::SHR64rCL,    X86::SHR64mCL },
555      { X86::SHR64ri,     X86::SHR64mi },
556      { X86::SHR8r1,      X86::SHR8m1 },
557      { X86::SHR8rCL,     X86::SHR8mCL },
558      { X86::SHR8ri,      X86::SHR8mi },
559      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
560      { X86::SHRD16rri8,  X86::SHRD16mri8 },
561      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
562      { X86::SHRD32rri8,  X86::SHRD32mri8 },
563      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
564      { X86::SHRD64rri8,  X86::SHRD64mri8 },
565      { X86::SUB16ri,     X86::SUB16mi },
566      { X86::SUB16ri8,    X86::SUB16mi8 },
567      { X86::SUB16rr,     X86::SUB16mr },
568      { X86::SUB32ri,     X86::SUB32mi },
569      { X86::SUB32ri8,    X86::SUB32mi8 },
570      { X86::SUB32rr,     X86::SUB32mr },
571      { X86::SUB64ri32,   X86::SUB64mi32 },
572      { X86::SUB64ri8,    X86::SUB64mi8 },
573      { X86::SUB64rr,     X86::SUB64mr },
574      { X86::SUB8ri,      X86::SUB8mi },
575      { X86::SUB8rr,      X86::SUB8mr },
576      { X86::XOR16ri,     X86::XOR16mi },
577      { X86::XOR16ri8,    X86::XOR16mi8 },
578      { X86::XOR16rr,     X86::XOR16mr },
579      { X86::XOR32ri,     X86::XOR32mi },
580      { X86::XOR32ri8,    X86::XOR32mi8 },
581      { X86::XOR32rr,     X86::XOR32mr },
582      { X86::XOR64ri32,   X86::XOR64mi32 },
583      { X86::XOR64ri8,    X86::XOR64mi8 },
584      { X86::XOR64rr,     X86::XOR64mr },
585      { X86::XOR8ri,      X86::XOR8mi },
586      { X86::XOR8rr,      X86::XOR8mr }
587    };
588    ASSERT_SORTED(OpcodeTable);
589    OpcodeTablePtr = OpcodeTable;
590    OpcodeTableSize = array_lengthof(OpcodeTable);
591    isTwoAddrFold = true;
592  } else if (i == 0) { // If operand 0
593    if (MI->getOpcode() == X86::MOV16r0)
594      NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI);
595    else if (MI->getOpcode() == X86::MOV32r0)
596      NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI);
597    else if (MI->getOpcode() == X86::MOV64r0)
598      NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI);
599    else if (MI->getOpcode() == X86::MOV8r0)
600      NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI);
601    if (NewMI) {
602      NewMI->copyKillDeadInfo(MI);
603      return NewMI;
604    }
605
606    static const TableEntry OpcodeTable[] = {
607      { X86::CMP16ri,     X86::CMP16mi },
608      { X86::CMP16ri8,    X86::CMP16mi8 },
609      { X86::CMP32ri,     X86::CMP32mi },
610      { X86::CMP32ri8,    X86::CMP32mi8 },
611      { X86::CMP8ri,      X86::CMP8mi },
612      { X86::DIV16r,      X86::DIV16m },
613      { X86::DIV32r,      X86::DIV32m },
614      { X86::DIV64r,      X86::DIV64m },
615      { X86::DIV8r,       X86::DIV8m },
616      { X86::FsMOVAPDrr,  X86::MOVSDmr },
617      { X86::FsMOVAPSrr,  X86::MOVSSmr },
618      { X86::IDIV16r,     X86::IDIV16m },
619      { X86::IDIV32r,     X86::IDIV32m },
620      { X86::IDIV64r,     X86::IDIV64m },
621      { X86::IDIV8r,      X86::IDIV8m },
622      { X86::IMUL16r,     X86::IMUL16m },
623      { X86::IMUL32r,     X86::IMUL32m },
624      { X86::IMUL64r,     X86::IMUL64m },
625      { X86::IMUL8r,      X86::IMUL8m },
626      { X86::MOV16ri,     X86::MOV16mi },
627      { X86::MOV16rr,     X86::MOV16mr },
628      { X86::MOV32ri,     X86::MOV32mi },
629      { X86::MOV32rr,     X86::MOV32mr },
630      { X86::MOV64ri32,   X86::MOV64mi32 },
631      { X86::MOV64rr,     X86::MOV64mr },
632      { X86::MOV8ri,      X86::MOV8mi },
633      { X86::MOV8rr,      X86::MOV8mr },
634      { X86::MOVAPDrr,    X86::MOVAPDmr },
635      { X86::MOVAPSrr,    X86::MOVAPSmr },
636      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
637      { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
638      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
639      { X86::MOVSDrr,     X86::MOVSDmr },
640      { X86::MOVSDto64rr, X86::MOVSDto64mr },
641      { X86::MOVSS2DIrr,  X86::MOVSS2DImr },
642      { X86::MOVSSrr,     X86::MOVSSmr },
643      { X86::MOVUPDrr,    X86::MOVUPDmr },
644      { X86::MOVUPSrr,    X86::MOVUPSmr },
645      { X86::MUL16r,      X86::MUL16m },
646      { X86::MUL32r,      X86::MUL32m },
647      { X86::MUL64r,      X86::MUL64m },
648      { X86::MUL8r,       X86::MUL8m },
649      { X86::SETAEr,      X86::SETAEm },
650      { X86::SETAr,       X86::SETAm },
651      { X86::SETBEr,      X86::SETBEm },
652      { X86::SETBr,       X86::SETBm },
653      { X86::SETEr,       X86::SETEm },
654      { X86::SETGEr,      X86::SETGEm },
655      { X86::SETGr,       X86::SETGm },
656      { X86::SETLEr,      X86::SETLEm },
657      { X86::SETLr,       X86::SETLm },
658      { X86::SETNEr,      X86::SETNEm },
659      { X86::SETNPr,      X86::SETNPm },
660      { X86::SETNSr,      X86::SETNSm },
661      { X86::SETPr,       X86::SETPm },
662      { X86::SETSr,       X86::SETSm },
663      { X86::TEST16ri,    X86::TEST16mi },
664      { X86::TEST32ri,    X86::TEST32mi },
665      { X86::TEST64ri32,  X86::TEST64mi32 },
666      { X86::TEST8ri,     X86::TEST8mi },
667      { X86::XCHG16rr,    X86::XCHG16mr },
668      { X86::XCHG32rr,    X86::XCHG32mr },
669      { X86::XCHG64rr,    X86::XCHG64mr },
670      { X86::XCHG8rr,     X86::XCHG8mr }
671    };
672
673    ASSERT_SORTED(OpcodeTable);
674    OpcodeTablePtr = OpcodeTable;
675    OpcodeTableSize = array_lengthof(OpcodeTable);
676  } else if (i == 1) {
677    static const TableEntry OpcodeTable[] = {
678      { X86::CMP16rr,         X86::CMP16rm },
679      { X86::CMP32rr,         X86::CMP32rm },
680      { X86::CMP64ri32,       X86::CMP64mi32 },
681      { X86::CMP64ri8,        X86::CMP64mi8 },
682      { X86::CMP64rr,         X86::CMP64rm },
683      { X86::CMP8rr,          X86::CMP8rm },
684      { X86::CMPPDrri,        X86::CMPPDrmi },
685      { X86::CMPPSrri,        X86::CMPPSrmi },
686      { X86::CMPSDrr,         X86::CMPSDrm },
687      { X86::CMPSSrr,         X86::CMPSSrm },
688      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
689      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
690      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
691      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
692      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
693      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
694      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
695      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
696      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
697      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
698      { X86::FsMOVAPDrr,      X86::MOVSDrm },
699      { X86::FsMOVAPSrr,      X86::MOVSSrm },
700      { X86::IMUL16rri,       X86::IMUL16rmi },
701      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
702      { X86::IMUL32rri,       X86::IMUL32rmi },
703      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
704      { X86::IMUL64rr,        X86::IMUL64rm },
705      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
706      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
707      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
708      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
709      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
710      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
711      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
712      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
713      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
714      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
715      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
716      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
717      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
718      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
719      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
720      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
721      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
722      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
723      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
724      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
725      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
726      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
727      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
728      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
729      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
730      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
731      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
732      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
733      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
734      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
735      { X86::MOV16rr,         X86::MOV16rm },
736      { X86::MOV32rr,         X86::MOV32rm },
737      { X86::MOV64rr,         X86::MOV64rm },
738      { X86::MOV64toPQIrr,    X86::MOV64toPQIrm },
739      { X86::MOV64toSDrr,     X86::MOV64toSDrm },
740      { X86::MOV8rr,          X86::MOV8rm },
741      { X86::MOVAPDrr,        X86::MOVAPDrm },
742      { X86::MOVAPSrr,        X86::MOVAPSrm },
743      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
744      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
745      { X86::MOVDI2SSrr,      X86::MOVDI2SSrm },
746      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
747      { X86::MOVSDrr,         X86::MOVSDrm },
748      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
749      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
750      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
751      { X86::MOVSSrr,         X86::MOVSSrm },
752      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
753      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
754      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
755      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
756      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
757      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
758      { X86::MOVUPDrr,        X86::MOVUPDrm },
759      { X86::MOVUPSrr,        X86::MOVUPSrm },
760      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
761      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
762      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
763      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
764      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
765      { X86::PSHUFDri,        X86::PSHUFDmi },
766      { X86::PSHUFHWri,       X86::PSHUFHWmi },
767      { X86::PSHUFLWri,       X86::PSHUFLWmi },
768      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
769      { X86::TEST16rr,        X86::TEST16rm },
770      { X86::TEST32rr,        X86::TEST32rm },
771      { X86::TEST64rr,        X86::TEST64rm },
772      { X86::TEST8rr,         X86::TEST8rm },
773      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
774      { X86::UCOMISDrr,       X86::UCOMISDrm },
775      { X86::UCOMISSrr,       X86::UCOMISSrm },
776      { X86::XCHG16rr,        X86::XCHG16rm },
777      { X86::XCHG32rr,        X86::XCHG32rm },
778      { X86::XCHG64rr,        X86::XCHG64rm },
779      { X86::XCHG8rr,         X86::XCHG8rm }
780    };
781
782    ASSERT_SORTED(OpcodeTable);
783    OpcodeTablePtr = OpcodeTable;
784    OpcodeTableSize = array_lengthof(OpcodeTable);
785  } else if (i == 2) {
786    static const TableEntry OpcodeTable[] = {
787      { X86::ADC32rr,         X86::ADC32rm },
788      { X86::ADC64rr,         X86::ADC64rm },
789      { X86::ADD16rr,         X86::ADD16rm },
790      { X86::ADD32rr,         X86::ADD32rm },
791      { X86::ADD64rr,         X86::ADD64rm },
792      { X86::ADD8rr,          X86::ADD8rm },
793      { X86::ADDPDrr,         X86::ADDPDrm },
794      { X86::ADDPSrr,         X86::ADDPSrm },
795      { X86::ADDSDrr,         X86::ADDSDrm },
796      { X86::ADDSSrr,         X86::ADDSSrm },
797      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
798      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
799      { X86::AND16rr,         X86::AND16rm },
800      { X86::AND32rr,         X86::AND32rm },
801      { X86::AND64rr,         X86::AND64rm },
802      { X86::AND8rr,          X86::AND8rm },
803      { X86::ANDNPDrr,        X86::ANDNPDrm },
804      { X86::ANDNPSrr,        X86::ANDNPSrm },
805      { X86::ANDPDrr,         X86::ANDPDrm },
806      { X86::ANDPSrr,         X86::ANDPSrm },
807      { X86::CMOVA16rr,       X86::CMOVA16rm },
808      { X86::CMOVA32rr,       X86::CMOVA32rm },
809      { X86::CMOVA64rr,       X86::CMOVA64rm },
810      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
811      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
812      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
813      { X86::CMOVB16rr,       X86::CMOVB16rm },
814      { X86::CMOVB32rr,       X86::CMOVB32rm },
815      { X86::CMOVB64rr,       X86::CMOVB64rm },
816      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
817      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
818      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
819      { X86::CMOVE16rr,       X86::CMOVE16rm },
820      { X86::CMOVE32rr,       X86::CMOVE32rm },
821      { X86::CMOVE64rr,       X86::CMOVE64rm },
822      { X86::CMOVG16rr,       X86::CMOVG16rm },
823      { X86::CMOVG32rr,       X86::CMOVG32rm },
824      { X86::CMOVG64rr,       X86::CMOVG64rm },
825      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
826      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
827      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
828      { X86::CMOVL16rr,       X86::CMOVL16rm },
829      { X86::CMOVL32rr,       X86::CMOVL32rm },
830      { X86::CMOVL64rr,       X86::CMOVL64rm },
831      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
832      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
833      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
834      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
835      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
836      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
837      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
838      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
839      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
840      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
841      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
842      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
843      { X86::CMOVP16rr,       X86::CMOVP16rm },
844      { X86::CMOVP32rr,       X86::CMOVP32rm },
845      { X86::CMOVP64rr,       X86::CMOVP64rm },
846      { X86::CMOVS16rr,       X86::CMOVS16rm },
847      { X86::CMOVS32rr,       X86::CMOVS32rm },
848      { X86::CMOVS64rr,       X86::CMOVS64rm },
849      { X86::DIVPDrr,         X86::DIVPDrm },
850      { X86::DIVPSrr,         X86::DIVPSrm },
851      { X86::DIVSDrr,         X86::DIVSDrm },
852      { X86::DIVSSrr,         X86::DIVSSrm },
853      { X86::HADDPDrr,        X86::HADDPDrm },
854      { X86::HADDPSrr,        X86::HADDPSrm },
855      { X86::HSUBPDrr,        X86::HSUBPDrm },
856      { X86::HSUBPSrr,        X86::HSUBPSrm },
857      { X86::IMUL16rr,        X86::IMUL16rm },
858      { X86::IMUL32rr,        X86::IMUL32rm },
859      { X86::MAXPDrr,         X86::MAXPDrm },
860      { X86::MAXPDrr_Int,     X86::MAXPDrm_Int },
861      { X86::MAXPSrr,         X86::MAXPSrm },
862      { X86::MAXPSrr_Int,     X86::MAXPSrm_Int },
863      { X86::MAXSDrr,         X86::MAXSDrm },
864      { X86::MAXSDrr_Int,     X86::MAXSDrm_Int },
865      { X86::MAXSSrr,         X86::MAXSSrm },
866      { X86::MAXSSrr_Int,     X86::MAXSSrm_Int },
867      { X86::MINPDrr,         X86::MINPDrm },
868      { X86::MINPDrr_Int,     X86::MINPDrm_Int },
869      { X86::MINPSrr,         X86::MINPSrm },
870      { X86::MINPSrr_Int,     X86::MINPSrm_Int },
871      { X86::MINSDrr,         X86::MINSDrm },
872      { X86::MINSDrr_Int,     X86::MINSDrm_Int },
873      { X86::MINSSrr,         X86::MINSSrm },
874      { X86::MINSSrr_Int,     X86::MINSSrm_Int },
875      { X86::MULPDrr,         X86::MULPDrm },
876      { X86::MULPSrr,         X86::MULPSrm },
877      { X86::MULSDrr,         X86::MULSDrm },
878      { X86::MULSSrr,         X86::MULSSrm },
879      { X86::OR16rr,          X86::OR16rm },
880      { X86::OR32rr,          X86::OR32rm },
881      { X86::OR64rr,          X86::OR64rm },
882      { X86::OR8rr,           X86::OR8rm },
883      { X86::ORPDrr,          X86::ORPDrm },
884      { X86::ORPSrr,          X86::ORPSrm },
885      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
886      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
887      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
888      { X86::PADDBrr,         X86::PADDBrm },
889      { X86::PADDDrr,         X86::PADDDrm },
890      { X86::PADDQrr,         X86::PADDQrm },
891      { X86::PADDSBrr,        X86::PADDSBrm },
892      { X86::PADDSWrr,        X86::PADDSWrm },
893      { X86::PADDWrr,         X86::PADDWrm },
894      { X86::PANDNrr,         X86::PANDNrm },
895      { X86::PANDrr,          X86::PANDrm },
896      { X86::PAVGBrr,         X86::PAVGBrm },
897      { X86::PAVGWrr,         X86::PAVGWrm },
898      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
899      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
900      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
901      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
902      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
903      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
904      { X86::PINSRWrri,       X86::PINSRWrmi },
905      { X86::PMADDWDrr,       X86::PMADDWDrm },
906      { X86::PMAXSWrr,        X86::PMAXSWrm },
907      { X86::PMAXUBrr,        X86::PMAXUBrm },
908      { X86::PMINSWrr,        X86::PMINSWrm },
909      { X86::PMINUBrr,        X86::PMINUBrm },
910      { X86::PMULHUWrr,       X86::PMULHUWrm },
911      { X86::PMULHWrr,        X86::PMULHWrm },
912      { X86::PMULLWrr,        X86::PMULLWrm },
913      { X86::PMULUDQrr,       X86::PMULUDQrm },
914      { X86::PORrr,           X86::PORrm },
915      { X86::PSADBWrr,        X86::PSADBWrm },
916      { X86::PSLLDrr,         X86::PSLLDrm },
917      { X86::PSLLQrr,         X86::PSLLQrm },
918      { X86::PSLLWrr,         X86::PSLLWrm },
919      { X86::PSRADrr,         X86::PSRADrm },
920      { X86::PSRAWrr,         X86::PSRAWrm },
921      { X86::PSRLDrr,         X86::PSRLDrm },
922      { X86::PSRLQrr,         X86::PSRLQrm },
923      { X86::PSRLWrr,         X86::PSRLWrm },
924      { X86::PSUBBrr,         X86::PSUBBrm },
925      { X86::PSUBDrr,         X86::PSUBDrm },
926      { X86::PSUBSBrr,        X86::PSUBSBrm },
927      { X86::PSUBSWrr,        X86::PSUBSWrm },
928      { X86::PSUBWrr,         X86::PSUBWrm },
929      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
930      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
931      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
932      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
933      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
934      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
935      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
936      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
937      { X86::PXORrr,          X86::PXORrm },
938      { X86::RCPPSr,          X86::RCPPSm },
939      { X86::RCPPSr_Int,      X86::RCPPSm_Int },
940      { X86::RSQRTPSr,        X86::RSQRTPSm },
941      { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int },
942      { X86::RSQRTSSr,        X86::RSQRTSSm },
943      { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int },
944      { X86::SBB32rr,         X86::SBB32rm },
945      { X86::SBB64rr,         X86::SBB64rm },
946      { X86::SHUFPDrri,       X86::SHUFPDrmi },
947      { X86::SHUFPSrri,       X86::SHUFPSrmi },
948      { X86::SQRTPDr,         X86::SQRTPDm },
949      { X86::SQRTPDr_Int,     X86::SQRTPDm_Int },
950      { X86::SQRTPSr,         X86::SQRTPSm },
951      { X86::SQRTPSr_Int,     X86::SQRTPSm_Int },
952      { X86::SQRTSDr,         X86::SQRTSDm },
953      { X86::SQRTSDr_Int,     X86::SQRTSDm_Int },
954      { X86::SQRTSSr,         X86::SQRTSSm },
955      { X86::SQRTSSr_Int,     X86::SQRTSSm_Int },
956      { X86::SUB16rr,         X86::SUB16rm },
957      { X86::SUB32rr,         X86::SUB32rm },
958      { X86::SUB64rr,         X86::SUB64rm },
959      { X86::SUB8rr,          X86::SUB8rm },
960      { X86::SUBPDrr,         X86::SUBPDrm },
961      { X86::SUBPSrr,         X86::SUBPSrm },
962      { X86::SUBSDrr,         X86::SUBSDrm },
963      { X86::SUBSSrr,         X86::SUBSSrm },
964      // FIXME: TEST*rr -> swapped operand of TEST*mr.
965      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
966      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
967      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
968      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
969      { X86::XOR16rr,         X86::XOR16rm },
970      { X86::XOR32rr,         X86::XOR32rm },
971      { X86::XOR64rr,         X86::XOR64rm },
972      { X86::XOR8rr,          X86::XOR8rm },
973      { X86::XORPDrr,         X86::XORPDrm },
974      { X86::XORPSrr,         X86::XORPSrm }
975    };
976
977    ASSERT_SORTED(OpcodeTable);
978    OpcodeTablePtr = OpcodeTable;
979    OpcodeTableSize = array_lengthof(OpcodeTable);
980  }
981
982  // If table selected...
983  if (OpcodeTablePtr) {
984    // Find the Opcode to fuse
985    unsigned fromOpcode = MI->getOpcode();
986    // Lookup fromOpcode in table
987    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
988                                              fromOpcode)) {
989      if (isTwoAddrFold)
990        NewMI = FuseTwoAddrInst(Entry->to, MOs, MI, TII);
991      else
992        NewMI = FuseInst(Entry->to, i, MOs, MI, TII);
993      NewMI->copyKillDeadInfo(MI);
994      return NewMI;
995    }
996  }
997
998  // No fusion
999  if (PrintFailedFusing)
1000    cerr << "We failed to fuse ("
1001         << ((i == 1) ? "r" : "s") << "): " << *MI;
1002  return NULL;
1003}
1004
1005
1006MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1007                                                 int FrameIndex) const {
1008  // Check switch flag
1009  if (NoFusing) return NULL;
1010  SmallVector<MachineOperand,4> MOs;
1011  MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex));
1012  return foldMemoryOperand(MI, OpNum, MOs);
1013}
1014
1015MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1016                                                 MachineInstr *LoadMI) const {
1017  // Check switch flag
1018  if (NoFusing) return NULL;
1019  SmallVector<MachineOperand,4> MOs;
1020  unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode());
1021  for (unsigned i = NumOps - 4; i != NumOps; ++i)
1022    MOs.push_back(LoadMI->getOperand(i));
1023  return foldMemoryOperand(MI, OpNum, MOs);
1024}
1025
1026const unsigned *
1027X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
1028  static const unsigned CalleeSavedRegs32Bit[] = {
1029    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
1030  };
1031
1032  static const unsigned CalleeSavedRegs32EHRet[] = {
1033    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
1034  };
1035
1036  static const unsigned CalleeSavedRegs64Bit[] = {
1037    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1038  };
1039
1040  if (Is64Bit)
1041    return CalleeSavedRegs64Bit;
1042  else {
1043    if (MF) {
1044        MachineFrameInfo *MFI = MF->getFrameInfo();
1045        MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1046        if (MMI && MMI->callsEHReturn())
1047          return CalleeSavedRegs32EHRet;
1048    }
1049    return CalleeSavedRegs32Bit;
1050  }
1051}
1052
1053const TargetRegisterClass* const*
1054X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
1055  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
1056    &X86::GR32RegClass, &X86::GR32RegClass,
1057    &X86::GR32RegClass, &X86::GR32RegClass,  0
1058  };
1059  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
1060    &X86::GR32RegClass, &X86::GR32RegClass,
1061    &X86::GR32RegClass, &X86::GR32RegClass,
1062    &X86::GR32RegClass, &X86::GR32RegClass,  0
1063  };
1064  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
1065    &X86::GR64RegClass, &X86::GR64RegClass,
1066    &X86::GR64RegClass, &X86::GR64RegClass,
1067    &X86::GR64RegClass, &X86::GR64RegClass, 0
1068  };
1069
1070  if (Is64Bit)
1071    return CalleeSavedRegClasses64Bit;
1072  else {
1073    if (MF) {
1074        MachineFrameInfo *MFI = MF->getFrameInfo();
1075        MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1076        if (MMI && MMI->callsEHReturn())
1077          return CalleeSavedRegClasses32EHRet;
1078    }
1079    return CalleeSavedRegClasses32Bit;
1080  }
1081
1082}
1083
1084BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
1085  BitVector Reserved(getNumRegs());
1086  Reserved.set(X86::RSP);
1087  Reserved.set(X86::ESP);
1088  Reserved.set(X86::SP);
1089  Reserved.set(X86::SPL);
1090  if (hasFP(MF)) {
1091    Reserved.set(X86::RBP);
1092    Reserved.set(X86::EBP);
1093    Reserved.set(X86::BP);
1094    Reserved.set(X86::BPL);
1095  }
1096  return Reserved;
1097}
1098
1099//===----------------------------------------------------------------------===//
1100// Stack Frame Processing methods
1101//===----------------------------------------------------------------------===//
1102
1103// hasFP - Return true if the specified function should have a dedicated frame
1104// pointer register.  This is true if the function has variable sized allocas or
1105// if frame pointer elimination is disabled.
1106//
1107bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
1108  MachineFrameInfo *MFI = MF.getFrameInfo();
1109  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1110
1111  return (NoFramePointerElim ||
1112          MFI->hasVarSizedObjects() ||
1113          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
1114          (MMI && MMI->callsUnwindInit()));
1115}
1116
1117bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
1118  return !MF.getFrameInfo()->hasVarSizedObjects();
1119}
1120
1121void X86RegisterInfo::
1122eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1123                              MachineBasicBlock::iterator I) const {
1124  if (!hasReservedCallFrame(MF)) {
1125    // If the stack pointer can be changed after prologue, turn the
1126    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1127    // adjcallstackdown instruction into 'add ESP, <amt>'
1128    // TODO: consider using push / pop instead of sub + store / add
1129    MachineInstr *Old = I;
1130    uint64_t Amount = Old->getOperand(0).getImm();
1131    if (Amount != 0) {
1132      // We need to keep the stack aligned properly.  To do this, we round the
1133      // amount of space needed for the outgoing arguments up to the next
1134      // alignment boundary.
1135      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1136      Amount = (Amount+Align-1)/Align*Align;
1137
1138      MachineInstr *New = 0;
1139      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
1140        New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
1141          .addReg(StackPtr).addImm(Amount);
1142      } else {
1143        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
1144        // factor out the amount the callee already popped.
1145        uint64_t CalleeAmt = Old->getOperand(1).getImm();
1146        Amount -= CalleeAmt;
1147        if (Amount) {
1148          unsigned Opc = (Amount < 128) ?
1149            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1150            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1151          New = BuildMI(TII.get(Opc),  StackPtr)
1152                        .addReg(StackPtr).addImm(Amount);
1153        }
1154      }
1155
1156      // Replace the pseudo instruction with a new instruction...
1157      if (New) MBB.insert(I, New);
1158    }
1159  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
1160    // If we are performing frame pointer elimination and if the callee pops
1161    // something off the stack pointer, add it back.  We do this until we have
1162    // more advanced stack pointer tracking ability.
1163    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
1164      unsigned Opc = (CalleeAmt < 128) ?
1165        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1166        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1167      MachineInstr *New =
1168        BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
1169      MBB.insert(I, New);
1170    }
1171  }
1172
1173  MBB.erase(I);
1174}
1175
1176void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1177                                          int SPAdj, RegScavenger *RS) const{
1178  assert(SPAdj == 0 && "Unexpected");
1179
1180  unsigned i = 0;
1181  MachineInstr &MI = *II;
1182  MachineFunction &MF = *MI.getParent()->getParent();
1183  while (!MI.getOperand(i).isFrameIndex()) {
1184    ++i;
1185    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1186  }
1187
1188  int FrameIndex = MI.getOperand(i).getFrameIndex();
1189  // This must be part of a four operand memory reference.  Replace the
1190  // FrameIndex with base register with EBP.  Add an offset to the offset.
1191  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
1192
1193  // Now add the frame object offset to the offset from EBP.
1194  int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1195                   MI.getOperand(i+3).getImm()+SlotSize;
1196
1197  if (!hasFP(MF))
1198    Offset += MF.getFrameInfo()->getStackSize();
1199  else
1200    Offset += SlotSize;  // Skip the saved EBP
1201
1202  MI.getOperand(i+3).ChangeToImmediate(Offset);
1203}
1204
1205void
1206X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1207  if (hasFP(MF)) {
1208    // Create a frame entry for the EBP register that must be saved.
1209    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1210                                                        (int)SlotSize * -2);
1211    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1212           "Slot for EBP register must be last in order to be found!");
1213  }
1214}
1215
1216/// emitSPUpdate - Emit a series of instructions to increment / decrement the
1217/// stack pointer by a constant value.
1218static
1219void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1220                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
1221                  const TargetInstrInfo &TII) {
1222  bool isSub = NumBytes < 0;
1223  uint64_t Offset = isSub ? -NumBytes : NumBytes;
1224  unsigned Opc = isSub
1225    ? ((Offset < 128) ?
1226       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1227       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
1228    : ((Offset < 128) ?
1229       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1230       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
1231  uint64_t Chunk = (1LL << 31) - 1;
1232
1233  while (Offset) {
1234    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
1235    BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
1236    Offset -= ThisVal;
1237  }
1238}
1239
1240void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1241  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
1242  MachineFrameInfo *MFI = MF.getFrameInfo();
1243  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1244  const Function* Fn = MF.getFunction();
1245  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1246  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1247  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1248  MachineBasicBlock::iterator MBBI = MBB.begin();
1249
1250  // Prepare for frame info.
1251  unsigned FrameLabelId = 0, StartLabelId = 0;
1252
1253  // Get the number of bytes to allocate from the FrameInfo
1254  uint64_t StackSize = MFI->getStackSize();
1255  uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1256
1257  if (MMI && MMI->needsFrameInfo()) {
1258    // Mark function start
1259    StartLabelId = MMI->NextLabelID();
1260    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(StartLabelId);
1261  }
1262
1263  if (hasFP(MF)) {
1264    // Get the offset of the stack slot for the EBP register... which is
1265    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1266    // Update the frame offset adjustment.
1267    MFI->setOffsetAdjustment(SlotSize-NumBytes);
1268
1269    // Save EBP into the appropriate stack slot...
1270    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1271      .addReg(FramePtr);
1272    NumBytes -= SlotSize;
1273
1274    if (MMI && MMI->needsFrameInfo()) {
1275      // Mark effective beginning of when frame pointer becomes valid.
1276      FrameLabelId = MMI->NextLabelID();
1277      BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1278    }
1279
1280    // Update EBP with the new base value...
1281    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1282      .addReg(StackPtr);
1283  }
1284
1285  unsigned ReadyLabelId = 0;
1286  if (MMI && MMI->needsFrameInfo()) {
1287    // Mark effective beginning of when frame pointer is ready.
1288    ReadyLabelId = MMI->NextLabelID();
1289    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1290  }
1291
1292  // Skip the callee-saved push instructions.
1293  while (MBBI != MBB.end() &&
1294         (MBBI->getOpcode() == X86::PUSH32r ||
1295          MBBI->getOpcode() == X86::PUSH64r))
1296    ++MBBI;
1297
1298  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
1299    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1300      // Check, whether EAX is livein for this function
1301      bool isEAXAlive = false;
1302      for (MachineFunction::livein_iterator II = MF.livein_begin(),
1303             EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1304        unsigned Reg = II->first;
1305        isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1306                      Reg == X86::AH || Reg == X86::AL);
1307      }
1308
1309      // Function prologue calls _alloca to probe the stack when allocating
1310      // more than 4k bytes in one go. Touching the stack at 4K increments is
1311      // necessary to ensure that the guard pages used by the OS virtual memory
1312      // manager are allocated in correct sequence.
1313      if (!isEAXAlive) {
1314        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1315        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1316          .addExternalSymbol("_alloca");
1317      } else {
1318        // Save EAX
1319        BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
1320        // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1321        // allocated bytes for EAX.
1322        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
1323        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1324          .addExternalSymbol("_alloca");
1325        // Restore EAX
1326        MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
1327                                        StackPtr, NumBytes-4);
1328        MBB.insert(MBBI, MI);
1329      }
1330    } else {
1331      // If there is an ADD32ri or SUB32ri of ESP immediately after this
1332      // instruction, merge the two instructions.
1333      if (MBBI != MBB.end()) {
1334        MachineBasicBlock::iterator NI = next(MBBI);
1335        unsigned Opc = MBBI->getOpcode();
1336        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1337             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1338            MBBI->getOperand(0).getReg() == StackPtr) {
1339          NumBytes -= MBBI->getOperand(2).getImm();
1340          MBB.erase(MBBI);
1341          MBBI = NI;
1342        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1343                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1344                   MBBI->getOperand(0).getReg() == StackPtr) {
1345          NumBytes += MBBI->getOperand(2).getImm();
1346          MBB.erase(MBBI);
1347          MBBI = NI;
1348        }
1349      }
1350
1351      if (NumBytes)
1352        emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1353    }
1354  }
1355
1356  if (MMI && MMI->needsFrameInfo()) {
1357    std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1358    const TargetAsmInfo *TAI = MF.getTarget().getTargetAsmInfo();
1359
1360    // Calculate amount of bytes used for return address storing
1361    int stackGrowth =
1362      (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
1363       TargetFrameInfo::StackGrowsUp ?
1364       TAI->getAddressSize() : -TAI->getAddressSize());
1365
1366    if (StackSize) {
1367      // Show update of SP.
1368      if (hasFP(MF)) {
1369        // Adjust SP
1370        MachineLocation SPDst(MachineLocation::VirtualFP);
1371        MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
1372        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1373      } else {
1374        MachineLocation SPDst(MachineLocation::VirtualFP);
1375        MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
1376        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1377      }
1378    } else {
1379      //FIXME: Verify & implement for FP
1380      MachineLocation SPDst(StackPtr);
1381      MachineLocation SPSrc(StackPtr, stackGrowth);
1382      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1383    }
1384
1385    // Add callee saved registers to move list.
1386    const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1387
1388    // FIXME: This is dirty hack. The code itself is pretty mess right now.
1389    // It should be rewritten from scratch and generalized sometimes.
1390
1391    // Determine maximum offset (minumum due to stack growth)
1392    int64_t MaxOffset = 0;
1393    for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
1394      MaxOffset = std::min(MaxOffset,
1395                           MFI->getObjectOffset(CSI[I].getFrameIdx()));
1396
1397    // Calculate offsets
1398    for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
1399      int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1400      unsigned Reg = CSI[I].getReg();
1401      Offset = (MaxOffset-Offset+3*stackGrowth);
1402      MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1403      MachineLocation CSSrc(Reg);
1404      Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1405    }
1406
1407    if (hasFP(MF)) {
1408      // Save FP
1409      MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
1410      MachineLocation FPSrc(FramePtr);
1411      Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1412    }
1413
1414    MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1415    MachineLocation FPSrc(MachineLocation::VirtualFP);
1416    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1417  }
1418
1419  // If it's main() on Cygwin\Mingw32 we should align stack as well
1420  if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1421      Subtarget->isTargetCygMing()) {
1422    BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
1423                .addReg(X86::ESP).addImm(-Align);
1424
1425    // Probe the stack
1426    BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1427    BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1428  }
1429}
1430
1431void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1432                                   MachineBasicBlock &MBB) const {
1433  const MachineFrameInfo *MFI = MF.getFrameInfo();
1434  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1435  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1436  unsigned RetOpcode = MBBI->getOpcode();
1437
1438  switch (RetOpcode) {
1439  case X86::RET:
1440  case X86::RETI:
1441  case X86::EH_RETURN:
1442  case X86::TAILJMPd:
1443  case X86::TAILJMPr:
1444  case X86::TAILJMPm: break;  // These are ok
1445  default:
1446    assert(0 && "Can only insert epilog into returning blocks");
1447  }
1448
1449  // Get the number of bytes to allocate from the FrameInfo
1450  uint64_t StackSize = MFI->getStackSize();
1451  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1452  uint64_t NumBytes = StackSize - CSSize;
1453
1454  if (hasFP(MF)) {
1455    // pop EBP.
1456    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1457    NumBytes -= SlotSize;
1458  }
1459
1460  // Skip the callee-saved pop instructions.
1461  while (MBBI != MBB.begin()) {
1462    MachineBasicBlock::iterator PI = prior(MBBI);
1463    unsigned Opc = PI->getOpcode();
1464    if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
1465      break;
1466    --MBBI;
1467  }
1468
1469  if (NumBytes || MFI->hasVarSizedObjects()) {
1470    // If there is an ADD32ri or SUB32ri of ESP immediately before this
1471    // instruction, merge the two instructions.
1472    if (MBBI != MBB.begin()) {
1473      MachineBasicBlock::iterator PI = prior(MBBI);
1474      unsigned Opc = PI->getOpcode();
1475      if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1476           Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1477          PI->getOperand(0).getReg() == StackPtr) {
1478        NumBytes += PI->getOperand(2).getImm();
1479        MBB.erase(PI);
1480      } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1481                  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1482                 PI->getOperand(0).getReg() == StackPtr) {
1483        NumBytes -= PI->getOperand(2).getImm();
1484        MBB.erase(PI);
1485      }
1486    }
1487  }
1488
1489  // If dynamic alloca is used, then reset esp to point to the last
1490  // callee-saved slot before popping them off!
1491  if (MFI->hasVarSizedObjects()) {
1492    unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1493    if (CSSize) {
1494      MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
1495                                      FramePtr, -CSSize);
1496      MBB.insert(MBBI, MI);
1497    } else
1498      BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1499        addReg(FramePtr);
1500
1501    NumBytes = 0;
1502  }
1503
1504  // adjust stack pointer back: ESP += numbytes
1505  if (NumBytes)
1506    emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1507
1508  // We're returning from function via eh_return.
1509  if (RetOpcode == X86::EH_RETURN) {
1510    MBBI = prior(MBB.end());
1511    MachineOperand &DestAddr  = MBBI->getOperand(0);
1512    assert(DestAddr.isReg() && "Offset should be in register!");
1513    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1514      addReg(DestAddr.getReg());
1515  }
1516}
1517
1518unsigned X86RegisterInfo::getRARegister() const {
1519  if (Is64Bit)
1520    return X86::RIP;  // Should have dwarf #16
1521  else
1522    return X86::EIP;  // Should have dwarf #8
1523}
1524
1525unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1526  return hasFP(MF) ? FramePtr : StackPtr;
1527}
1528
1529void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1530                                                                         const {
1531  // Calculate amount of bytes used for return address storing
1532  int stackGrowth = (Is64Bit ? -8 : -4);
1533
1534  // Initial state of the frame pointer is esp+4.
1535  MachineLocation Dst(MachineLocation::VirtualFP);
1536  MachineLocation Src(StackPtr, stackGrowth);
1537  Moves.push_back(MachineMove(0, Dst, Src));
1538
1539  // Add return address to move list
1540  MachineLocation CSDst(StackPtr, stackGrowth);
1541  MachineLocation CSSrc(getRARegister());
1542  Moves.push_back(MachineMove(0, CSDst, CSSrc));
1543}
1544
1545unsigned X86RegisterInfo::getEHExceptionRegister() const {
1546  assert(0 && "What is the exception register");
1547  return 0;
1548}
1549
1550unsigned X86RegisterInfo::getEHHandlerRegister() const {
1551  assert(0 && "What is the exception handler register");
1552  return 0;
1553}
1554
1555namespace llvm {
1556unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1557  switch (VT) {
1558  default: return Reg;
1559  case MVT::i8:
1560    if (High) {
1561      switch (Reg) {
1562      default: return 0;
1563      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1564        return X86::AH;
1565      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1566        return X86::DH;
1567      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1568        return X86::CH;
1569      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1570        return X86::BH;
1571      }
1572    } else {
1573      switch (Reg) {
1574      default: return 0;
1575      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1576        return X86::AL;
1577      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1578        return X86::DL;
1579      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1580        return X86::CL;
1581      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1582        return X86::BL;
1583      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1584        return X86::SIL;
1585      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1586        return X86::DIL;
1587      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1588        return X86::BPL;
1589      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1590        return X86::SPL;
1591      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1592        return X86::R8B;
1593      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1594        return X86::R9B;
1595      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1596        return X86::R10B;
1597      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1598        return X86::R11B;
1599      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1600        return X86::R12B;
1601      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1602        return X86::R13B;
1603      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1604        return X86::R14B;
1605      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1606        return X86::R15B;
1607      }
1608    }
1609  case MVT::i16:
1610    switch (Reg) {
1611    default: return Reg;
1612    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1613      return X86::AX;
1614    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1615      return X86::DX;
1616    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1617      return X86::CX;
1618    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1619      return X86::BX;
1620    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1621      return X86::SI;
1622    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1623      return X86::DI;
1624    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1625      return X86::BP;
1626    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1627      return X86::SP;
1628    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1629      return X86::R8W;
1630    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1631      return X86::R9W;
1632    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1633      return X86::R10W;
1634    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1635      return X86::R11W;
1636    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1637      return X86::R12W;
1638    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1639      return X86::R13W;
1640    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1641      return X86::R14W;
1642    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1643      return X86::R15W;
1644    }
1645  case MVT::i32:
1646    switch (Reg) {
1647    default: return Reg;
1648    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1649      return X86::EAX;
1650    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1651      return X86::EDX;
1652    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1653      return X86::ECX;
1654    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1655      return X86::EBX;
1656    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1657      return X86::ESI;
1658    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1659      return X86::EDI;
1660    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1661      return X86::EBP;
1662    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1663      return X86::ESP;
1664    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1665      return X86::R8D;
1666    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1667      return X86::R9D;
1668    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1669      return X86::R10D;
1670    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1671      return X86::R11D;
1672    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1673      return X86::R12D;
1674    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1675      return X86::R13D;
1676    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1677      return X86::R14D;
1678    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1679      return X86::R15D;
1680    }
1681  case MVT::i64:
1682    switch (Reg) {
1683    default: return Reg;
1684    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1685      return X86::RAX;
1686    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1687      return X86::RDX;
1688    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1689      return X86::RCX;
1690    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1691      return X86::RBX;
1692    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1693      return X86::RSI;
1694    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1695      return X86::RDI;
1696    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1697      return X86::RBP;
1698    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1699      return X86::RSP;
1700    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1701      return X86::R8;
1702    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1703      return X86::R9;
1704    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1705      return X86::R10;
1706    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1707      return X86::R11;
1708    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1709      return X86::R12;
1710    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1711      return X86::R13;
1712    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1713      return X86::R14;
1714    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1715      return X86::R15;
1716    }
1717  }
1718
1719  return Reg;
1720}
1721}
1722
1723#include "X86GenRegisterInfo.inc"
1724
1725