X86RegisterInfo.cpp revision 73e884bb3e971b1e794ba2501df15138f73b8b1a 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/CommandLine.h"
41#include "llvm/Support/ErrorHandling.h"
42using namespace llvm;
43
44X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45                                 const TargetInstrInfo &tii)
46  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47                         X86::ADJCALLSTACKDOWN64 :
48                         X86::ADJCALLSTACKDOWN32,
49                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
50                         X86::ADJCALLSTACKUP64 :
51                         X86::ADJCALLSTACKUP32),
52    TM(tm), TII(tii) {
53  // Cache some information.
54  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55  Is64Bit = Subtarget->is64Bit();
56  IsWin64 = Subtarget->isTargetWin64();
57  StackAlign = TM.getFrameInfo()->getStackAlignment();
58
59  if (Is64Bit) {
60    SlotSize = 8;
61    StackPtr = X86::RSP;
62    FramePtr = X86::RBP;
63  } else {
64    SlotSize = 4;
65    StackPtr = X86::ESP;
66    FramePtr = X86::EBP;
67  }
68}
69
70/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71/// specific numbering, used in debug info and exception tables.
72int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74  unsigned Flavour = DWARFFlavour::X86_64;
75
76  if (!Subtarget->is64Bit()) {
77    if (Subtarget->isTargetDarwin()) {
78      if (isEH)
79        Flavour = DWARFFlavour::X86_32_DarwinEH;
80      else
81        Flavour = DWARFFlavour::X86_32_Generic;
82    } else if (Subtarget->isTargetCygMing()) {
83      // Unsupported by now, just quick fallback
84      Flavour = DWARFFlavour::X86_32_Generic;
85    } else {
86      Flavour = DWARFFlavour::X86_32_Generic;
87    }
88  }
89
90  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91}
92
93/// getX86RegNum - This function maps LLVM register identifiers to their X86
94/// specific numbering, which is used in various places encoding instructions.
95unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96  switch(RegNo) {
97  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102    return N86::ESP;
103  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104    return N86::EBP;
105  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106    return N86::ESI;
107  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
108    return N86::EDI;
109
110  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
111    return N86::EAX;
112  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
113    return N86::ECX;
114  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115    return N86::EDX;
116  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117    return N86::EBX;
118  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119    return N86::ESP;
120  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121    return N86::EBP;
122  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123    return N86::ESI;
124  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
125    return N86::EDI;
126
127  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129    return RegNo-X86::ST0;
130
131  case X86::XMM0: case X86::XMM8: case X86::MM0:
132    return 0;
133  case X86::XMM1: case X86::XMM9: case X86::MM1:
134    return 1;
135  case X86::XMM2: case X86::XMM10: case X86::MM2:
136    return 2;
137  case X86::XMM3: case X86::XMM11: case X86::MM3:
138    return 3;
139  case X86::XMM4: case X86::XMM12: case X86::MM4:
140    return 4;
141  case X86::XMM5: case X86::XMM13: case X86::MM5:
142    return 5;
143  case X86::XMM6: case X86::XMM14: case X86::MM6:
144    return 6;
145  case X86::XMM7: case X86::XMM15: case X86::MM7:
146    return 7;
147
148  default:
149    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150    llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
151    return 0;
152  }
153}
154
155const TargetRegisterClass *
156X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157                                          const TargetRegisterClass *B,
158                                          unsigned SubIdx) const {
159  switch (SubIdx) {
160  default: return 0;
161  case 1:
162    // 8-bit
163    if (B == &X86::GR8RegClass) {
164      if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
165        return A;
166    } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168          A == &X86::GR64_NOREXRegClass ||
169          A == &X86::GR64_NOSPRegClass ||
170          A == &X86::GR64_NOREX_NOSPRegClass)
171        return &X86::GR64_ABCDRegClass;
172      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173               A == &X86::GR32_NOREXRegClass ||
174               A == &X86::GR32_NOSPRegClass)
175        return &X86::GR32_ABCDRegClass;
176      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177               A == &X86::GR16_NOREXRegClass)
178        return &X86::GR16_ABCDRegClass;
179    } else if (B == &X86::GR8_NOREXRegClass) {
180      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182        return &X86::GR64_NOREXRegClass;
183      else if (A == &X86::GR64_ABCDRegClass)
184        return &X86::GR64_ABCDRegClass;
185      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186               A == &X86::GR32_NOSPRegClass)
187        return &X86::GR32_NOREXRegClass;
188      else if (A == &X86::GR32_ABCDRegClass)
189        return &X86::GR32_ABCDRegClass;
190      else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191        return &X86::GR16_NOREXRegClass;
192      else if (A == &X86::GR16_ABCDRegClass)
193        return &X86::GR16_ABCDRegClass;
194    }
195    break;
196  case 2:
197    // 8-bit hi
198    if (B == &X86::GR8_ABCD_HRegClass) {
199      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200          A == &X86::GR64_NOREXRegClass ||
201          A == &X86::GR64_NOSPRegClass ||
202          A == &X86::GR64_NOREX_NOSPRegClass)
203        return &X86::GR64_ABCDRegClass;
204      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206        return &X86::GR32_ABCDRegClass;
207      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208               A == &X86::GR16_NOREXRegClass)
209        return &X86::GR16_ABCDRegClass;
210    }
211    break;
212  case 3:
213    // 16-bit
214    if (B == &X86::GR16RegClass) {
215      if (A->getSize() == 4 || A->getSize() == 8)
216        return A;
217    } else if (B == &X86::GR16_ABCDRegClass) {
218      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219          A == &X86::GR64_NOREXRegClass ||
220          A == &X86::GR64_NOSPRegClass ||
221          A == &X86::GR64_NOREX_NOSPRegClass)
222        return &X86::GR64_ABCDRegClass;
223      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225        return &X86::GR32_ABCDRegClass;
226    } else if (B == &X86::GR16_NOREXRegClass) {
227      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229        return &X86::GR64_NOREXRegClass;
230      else if (A == &X86::GR64_ABCDRegClass)
231        return &X86::GR64_ABCDRegClass;
232      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233               A == &X86::GR32_NOSPRegClass)
234        return &X86::GR32_NOREXRegClass;
235      else if (A == &X86::GR32_ABCDRegClass)
236        return &X86::GR64_ABCDRegClass;
237    }
238    break;
239  case 4:
240    // 32-bit
241    if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242      if (A->getSize() == 8)
243        return A;
244    } else if (B == &X86::GR32_ABCDRegClass) {
245      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246          A == &X86::GR64_NOREXRegClass ||
247          A == &X86::GR64_NOSPRegClass ||
248          A == &X86::GR64_NOREX_NOSPRegClass)
249        return &X86::GR64_ABCDRegClass;
250    } else if (B == &X86::GR32_NOREXRegClass) {
251      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253        return &X86::GR64_NOREXRegClass;
254      else if (A == &X86::GR64_ABCDRegClass)
255        return &X86::GR64_ABCDRegClass;
256    }
257    break;
258  }
259  return 0;
260}
261
262const TargetRegisterClass *
263X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
264  switch (Kind) {
265  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266  case 0: // Normal GPRs.
267    if (TM.getSubtarget<X86Subtarget>().is64Bit())
268      return &X86::GR64RegClass;
269    return &X86::GR32RegClass;
270  case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271    if (TM.getSubtarget<X86Subtarget>().is64Bit())
272      return &X86::GR64_NOSPRegClass;
273    return &X86::GR32_NOSPRegClass;
274  }
275}
276
277const TargetRegisterClass *
278X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279  if (RC == &X86::CCRRegClass) {
280    if (Is64Bit)
281      return &X86::GR64RegClass;
282    else
283      return &X86::GR32RegClass;
284  }
285  return NULL;
286}
287
288const unsigned *
289X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290  bool callsEHReturn = false;
291
292  if (MF) {
293    const MachineFrameInfo *MFI = MF->getFrameInfo();
294    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
296  }
297
298  static const unsigned CalleeSavedRegs32Bit[] = {
299    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
300  };
301
302  static const unsigned CalleeSavedRegs32EHRet[] = {
303    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
304  };
305
306  static const unsigned CalleeSavedRegs64Bit[] = {
307    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
308  };
309
310  static const unsigned CalleeSavedRegs64EHRet[] = {
311    X86::RAX, X86::RDX, X86::RBX, X86::R12,
312    X86::R13, X86::R14, X86::R15, X86::RBP, 0
313  };
314
315  static const unsigned CalleeSavedRegsWin64[] = {
316    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
317    X86::R12,   X86::R13,   X86::R14,   X86::R15,
318    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
319    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320    X86::XMM14, X86::XMM15, 0
321  };
322
323  if (Is64Bit) {
324    if (IsWin64)
325      return CalleeSavedRegsWin64;
326    else
327      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
328  } else {
329    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
330  }
331}
332
333const TargetRegisterClass* const*
334X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335  bool callsEHReturn = false;
336
337  if (MF) {
338    const MachineFrameInfo *MFI = MF->getFrameInfo();
339    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
341  }
342
343  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344    &X86::GR32RegClass, &X86::GR32RegClass,
345    &X86::GR32RegClass, &X86::GR32RegClass,  0
346  };
347  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348    &X86::GR32RegClass, &X86::GR32RegClass,
349    &X86::GR32RegClass, &X86::GR32RegClass,
350    &X86::GR32RegClass, &X86::GR32RegClass,  0
351  };
352  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353    &X86::GR64RegClass, &X86::GR64RegClass,
354    &X86::GR64RegClass, &X86::GR64RegClass,
355    &X86::GR64RegClass, &X86::GR64RegClass, 0
356  };
357  static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358    &X86::GR64RegClass, &X86::GR64RegClass,
359    &X86::GR64RegClass, &X86::GR64RegClass,
360    &X86::GR64RegClass, &X86::GR64RegClass,
361    &X86::GR64RegClass, &X86::GR64RegClass, 0
362  };
363  static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364    &X86::GR64RegClass,  &X86::GR64RegClass,
365    &X86::GR64RegClass,  &X86::GR64RegClass,
366    &X86::GR64RegClass,  &X86::GR64RegClass,
367    &X86::GR64RegClass,  &X86::GR64RegClass,
368    &X86::VR128RegClass, &X86::VR128RegClass,
369    &X86::VR128RegClass, &X86::VR128RegClass,
370    &X86::VR128RegClass, &X86::VR128RegClass,
371    &X86::VR128RegClass, &X86::VR128RegClass,
372    &X86::VR128RegClass, &X86::VR128RegClass, 0
373  };
374
375  if (Is64Bit) {
376    if (IsWin64)
377      return CalleeSavedRegClassesWin64;
378    else
379      return (callsEHReturn ?
380              CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
381  } else {
382    return (callsEHReturn ?
383            CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
384  }
385}
386
387BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388  BitVector Reserved(getNumRegs());
389  // Set the stack-pointer register and its aliases as reserved.
390  Reserved.set(X86::RSP);
391  Reserved.set(X86::ESP);
392  Reserved.set(X86::SP);
393  Reserved.set(X86::SPL);
394
395  // Set the instruction pointer register and its aliases as reserved.
396  Reserved.set(X86::RIP);
397  Reserved.set(X86::EIP);
398  Reserved.set(X86::IP);
399
400  // Set the frame-pointer register and its aliases as reserved if needed.
401  if (hasFP(MF)) {
402    Reserved.set(X86::RBP);
403    Reserved.set(X86::EBP);
404    Reserved.set(X86::BP);
405    Reserved.set(X86::BPL);
406  }
407
408  // Mark the x87 stack registers as reserved, since they don't behave normally
409  // with respect to liveness. We don't fully model the effects of x87 stack
410  // pushes and pops after stackification.
411  Reserved.set(X86::ST0);
412  Reserved.set(X86::ST1);
413  Reserved.set(X86::ST2);
414  Reserved.set(X86::ST3);
415  Reserved.set(X86::ST4);
416  Reserved.set(X86::ST5);
417  Reserved.set(X86::ST6);
418  Reserved.set(X86::ST7);
419  return Reserved;
420}
421
422//===----------------------------------------------------------------------===//
423// Stack Frame Processing methods
424//===----------------------------------------------------------------------===//
425
426/// hasFP - Return true if the specified function should have a dedicated frame
427/// pointer register.  This is true if the function has variable sized allocas
428/// or if frame pointer elimination is disabled.
429bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
430  const MachineFrameInfo *MFI = MF.getFrameInfo();
431  const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
432
433  return (NoFramePointerElim ||
434          needsStackRealignment(MF) ||
435          MFI->hasVarSizedObjects() ||
436          MFI->isFrameAddressTaken() ||
437          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
438          (MMI && MMI->callsUnwindInit()));
439}
440
441bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
442  const MachineFrameInfo *MFI = MF.getFrameInfo();
443  return (RealignStack &&
444          !MFI->hasVarSizedObjects());
445}
446
447bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
448  const MachineFrameInfo *MFI = MF.getFrameInfo();
449  bool requiresRealignment =
450    RealignStack && (MFI->getMaxAlignment() > StackAlign);
451
452  // FIXME: Currently we don't support stack realignment for functions with
453  //        variable-sized allocas.
454  // FIXME: Temporary disable the error - it seems to be too conservative.
455  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
456    llvm_report_error(
457      "Stack realignment in presense of dynamic allocas is not supported");
458
459  return (requiresRealignment && !MFI->hasVarSizedObjects());
460}
461
462bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
463  return !MF.getFrameInfo()->hasVarSizedObjects();
464}
465
466bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
467                                           int &FrameIdx) const {
468  if (Reg == FramePtr && hasFP(MF)) {
469    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
470    return true;
471  }
472  return false;
473}
474
475int
476X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
477  const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
478  MachineFrameInfo *MFI = MF.getFrameInfo();
479  int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
480  uint64_t StackSize = MFI->getStackSize();
481
482  if (needsStackRealignment(MF)) {
483    if (FI < 0) {
484      // Skip the saved EBP.
485      Offset += SlotSize;
486    } else {
487      unsigned Align = MFI->getObjectAlignment(FI);
488      assert( (-(Offset + StackSize)) % Align == 0);
489      Align = 0;
490      return Offset + StackSize;
491    }
492    // FIXME: Support tail calls
493  } else {
494    if (!hasFP(MF))
495      return Offset + StackSize;
496
497    // Skip the saved EBP.
498    Offset += SlotSize;
499
500    // Skip the RETADDR move area
501    X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
502    int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
503    if (TailCallReturnAddrDelta < 0)
504      Offset -= TailCallReturnAddrDelta;
505  }
506
507  return Offset;
508}
509
510void X86RegisterInfo::
511eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
512                              MachineBasicBlock::iterator I) const {
513  if (!hasReservedCallFrame(MF)) {
514    // If the stack pointer can be changed after prologue, turn the
515    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
516    // adjcallstackdown instruction into 'add ESP, <amt>'
517    // TODO: consider using push / pop instead of sub + store / add
518    MachineInstr *Old = I;
519    uint64_t Amount = Old->getOperand(0).getImm();
520    if (Amount != 0) {
521      // We need to keep the stack aligned properly.  To do this, we round the
522      // amount of space needed for the outgoing arguments up to the next
523      // alignment boundary.
524      Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
525
526      MachineInstr *New = 0;
527      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
528        New = BuildMI(MF, Old->getDebugLoc(),
529                      TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
530                      StackPtr)
531          .addReg(StackPtr)
532          .addImm(Amount);
533      } else {
534        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
535
536        // Factor out the amount the callee already popped.
537        uint64_t CalleeAmt = Old->getOperand(1).getImm();
538        Amount -= CalleeAmt;
539
540      if (Amount) {
541          unsigned Opc = (Amount < 128) ?
542            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
543            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
544          New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
545            .addReg(StackPtr)
546            .addImm(Amount);
547        }
548      }
549
550      if (New) {
551        // The EFLAGS implicit def is dead.
552        New->getOperand(3).setIsDead();
553
554        // Replace the pseudo instruction with a new instruction.
555        MBB.insert(I, New);
556      }
557    }
558  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
559    // If we are performing frame pointer elimination and if the callee pops
560    // something off the stack pointer, add it back.  We do this until we have
561    // more advanced stack pointer tracking ability.
562    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
563      unsigned Opc = (CalleeAmt < 128) ?
564        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
565        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
566      MachineInstr *Old = I;
567      MachineInstr *New =
568        BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
569                StackPtr)
570          .addReg(StackPtr)
571          .addImm(CalleeAmt);
572
573      // The EFLAGS implicit def is dead.
574      New->getOperand(3).setIsDead();
575      MBB.insert(I, New);
576    }
577  }
578
579  MBB.erase(I);
580}
581
582unsigned
583X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
584                                     int SPAdj, int *Value,
585                                     RegScavenger *RS) const{
586  assert(SPAdj == 0 && "Unexpected");
587
588  unsigned i = 0;
589  MachineInstr &MI = *II;
590  MachineFunction &MF = *MI.getParent()->getParent();
591
592  while (!MI.getOperand(i).isFI()) {
593    ++i;
594    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
595  }
596
597  int FrameIndex = MI.getOperand(i).getIndex();
598  unsigned BasePtr;
599
600  if (needsStackRealignment(MF))
601    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
602  else
603    BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
604
605  // This must be part of a four operand memory reference.  Replace the
606  // FrameIndex with base register with EBP.  Add an offset to the offset.
607  MI.getOperand(i).ChangeToRegister(BasePtr, false);
608
609  // Now add the frame object offset to the offset from EBP.
610  if (MI.getOperand(i+3).isImm()) {
611    // Offset is a 32-bit integer.
612    int Offset = getFrameIndexOffset(MF, FrameIndex) +
613      (int)(MI.getOperand(i + 3).getImm());
614
615    MI.getOperand(i + 3).ChangeToImmediate(Offset);
616  } else {
617    // Offset is symbolic. This is extremely rare.
618    uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
619                      (uint64_t)MI.getOperand(i+3).getOffset();
620    MI.getOperand(i+3).setOffset(Offset);
621  }
622  return 0;
623}
624
625void
626X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
627                                                      RegScavenger *RS) const {
628  MachineFrameInfo *MFI = MF.getFrameInfo();
629
630  // Calculate and set max stack object alignment early, so we can decide
631  // whether we will need stack realignment (and thus FP).
632  MFI->calculateMaxStackAlignment();
633
634  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
635  int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
636
637  if (TailCallReturnAddrDelta < 0) {
638    // create RETURNADDR area
639    //   arg
640    //   arg
641    //   RETADDR
642    //   { ...
643    //     RETADDR area
644    //     ...
645    //   }
646    //   [EBP]
647    MFI->CreateFixedObject(-TailCallReturnAddrDelta,
648                           (-1U*SlotSize)+TailCallReturnAddrDelta,
649                           true, false);
650  }
651
652  if (hasFP(MF)) {
653    assert((TailCallReturnAddrDelta <= 0) &&
654           "The Delta should always be zero or negative");
655    const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
656
657    // Create a frame entry for the EBP register that must be saved.
658    int FrameIdx = MFI->CreateFixedObject(SlotSize,
659                                          -(int)SlotSize +
660                                          TFI.getOffsetOfLocalArea() +
661                                          TailCallReturnAddrDelta,
662                                          true, false);
663    assert(FrameIdx == MFI->getObjectIndexBegin() &&
664           "Slot for EBP register must be last in order to be found!");
665    FrameIdx = 0;
666  }
667}
668
669/// emitSPUpdate - Emit a series of instructions to increment / decrement the
670/// stack pointer by a constant value.
671static
672void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
673                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
674                  const TargetInstrInfo &TII) {
675  bool isSub = NumBytes < 0;
676  uint64_t Offset = isSub ? -NumBytes : NumBytes;
677  unsigned Opc = isSub
678    ? ((Offset < 128) ?
679       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
680       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
681    : ((Offset < 128) ?
682       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
683       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
684  uint64_t Chunk = (1LL << 31) - 1;
685  DebugLoc DL = MBB.findDebugLoc(MBBI);
686
687  while (Offset) {
688    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
689    MachineInstr *MI =
690      BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
691        .addReg(StackPtr)
692        .addImm(ThisVal);
693    MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
694    Offset -= ThisVal;
695  }
696}
697
698/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
699static
700void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
701                      unsigned StackPtr, uint64_t *NumBytes = NULL) {
702  if (MBBI == MBB.begin()) return;
703
704  MachineBasicBlock::iterator PI = prior(MBBI);
705  unsigned Opc = PI->getOpcode();
706  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
707       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
708      PI->getOperand(0).getReg() == StackPtr) {
709    if (NumBytes)
710      *NumBytes += PI->getOperand(2).getImm();
711    MBB.erase(PI);
712  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
713              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
714             PI->getOperand(0).getReg() == StackPtr) {
715    if (NumBytes)
716      *NumBytes -= PI->getOperand(2).getImm();
717    MBB.erase(PI);
718  }
719}
720
721/// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
722static
723void mergeSPUpdatesDown(MachineBasicBlock &MBB,
724                        MachineBasicBlock::iterator &MBBI,
725                        unsigned StackPtr, uint64_t *NumBytes = NULL) {
726  // FIXME: THIS ISN'T RUN!!!
727  return;
728
729  if (MBBI == MBB.end()) return;
730
731  MachineBasicBlock::iterator NI = llvm::next(MBBI);
732  if (NI == MBB.end()) return;
733
734  unsigned Opc = NI->getOpcode();
735  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
736       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
737      NI->getOperand(0).getReg() == StackPtr) {
738    if (NumBytes)
739      *NumBytes -= NI->getOperand(2).getImm();
740    MBB.erase(NI);
741    MBBI = NI;
742  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
743              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
744             NI->getOperand(0).getReg() == StackPtr) {
745    if (NumBytes)
746      *NumBytes += NI->getOperand(2).getImm();
747    MBB.erase(NI);
748    MBBI = NI;
749  }
750}
751
752/// mergeSPUpdates - Checks the instruction before/after the passed
753/// instruction. If it is an ADD/SUB instruction it is deleted argument and the
754/// stack adjustment is returned as a positive value for ADD and a negative for
755/// SUB.
756static int mergeSPUpdates(MachineBasicBlock &MBB,
757                           MachineBasicBlock::iterator &MBBI,
758                           unsigned StackPtr,
759                           bool doMergeWithPrevious) {
760  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
761      (!doMergeWithPrevious && MBBI == MBB.end()))
762    return 0;
763
764  MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
765  MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
766  unsigned Opc = PI->getOpcode();
767  int Offset = 0;
768
769  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
770       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
771      PI->getOperand(0).getReg() == StackPtr){
772    Offset += PI->getOperand(2).getImm();
773    MBB.erase(PI);
774    if (!doMergeWithPrevious) MBBI = NI;
775  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
776              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
777             PI->getOperand(0).getReg() == StackPtr) {
778    Offset -= PI->getOperand(2).getImm();
779    MBB.erase(PI);
780    if (!doMergeWithPrevious) MBBI = NI;
781  }
782
783  return Offset;
784}
785
786void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
787                                                unsigned LabelId,
788                                                unsigned FramePtr) const {
789  MachineFrameInfo *MFI = MF.getFrameInfo();
790  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
791  if (!MMI) return;
792
793  // Add callee saved registers to move list.
794  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
795  if (CSI.empty()) return;
796
797  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
798  const TargetData *TD = MF.getTarget().getTargetData();
799  bool HasFP = hasFP(MF);
800
801  // Calculate amount of bytes used for return address storing.
802  int stackGrowth =
803    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
804     TargetFrameInfo::StackGrowsUp ?
805     TD->getPointerSize() : -TD->getPointerSize());
806
807  // FIXME: This is dirty hack. The code itself is pretty mess right now.
808  // It should be rewritten from scratch and generalized sometimes.
809
810  // Determine maximum offset (minumum due to stack growth).
811  int64_t MaxOffset = 0;
812  for (std::vector<CalleeSavedInfo>::const_iterator
813         I = CSI.begin(), E = CSI.end(); I != E; ++I)
814    MaxOffset = std::min(MaxOffset,
815                         MFI->getObjectOffset(I->getFrameIdx()));
816
817  // Calculate offsets.
818  int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
819  for (std::vector<CalleeSavedInfo>::const_iterator
820         I = CSI.begin(), E = CSI.end(); I != E; ++I) {
821    int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
822    unsigned Reg = I->getReg();
823    Offset = MaxOffset - Offset + saveAreaOffset;
824
825    // Don't output a new machine move if we're re-saving the frame
826    // pointer. This happens when the PrologEpilogInserter has inserted an extra
827    // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
828    // generates one when frame pointers are used. If we generate a "machine
829    // move" for this extra "PUSH", the linker will lose track of the fact that
830    // the frame pointer should have the value of the first "PUSH" when it's
831    // trying to unwind.
832    //
833    // FIXME: This looks inelegant. It's possibly correct, but it's covering up
834    //        another bug. I.e., one where we generate a prolog like this:
835    //
836    //          pushl  %ebp
837    //          movl   %esp, %ebp
838    //          pushl  %ebp
839    //          pushl  %esi
840    //           ...
841    //
842    //        The immediate re-push of EBP is unnecessary. At the least, it's an
843    //        optimization bug. EBP can be used as a scratch register in certain
844    //        cases, but probably not when we have a frame pointer.
845    if (HasFP && FramePtr == Reg)
846      continue;
847
848    MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
849    MachineLocation CSSrc(Reg);
850    Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
851  }
852}
853
854/// emitPrologue - Push callee-saved registers onto the stack, which
855/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
856/// space for local variables. Also emit labels used by the exception handler to
857/// generate the exception handling frames.
858void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
859  MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
860  MachineBasicBlock::iterator MBBI = MBB.begin();
861  MachineFrameInfo *MFI = MF.getFrameInfo();
862  const Function *Fn = MF.getFunction();
863  const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
864  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
865  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
866  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
867                          !Fn->doesNotThrow() || UnwindTablesMandatory;
868  uint64_t MaxAlign  = MFI->getMaxAlignment(); // Desired stack alignment.
869  uint64_t StackSize = MFI->getStackSize();    // Number of bytes to allocate.
870  bool HasFP = hasFP(MF);
871  DebugLoc DL;
872
873  // Add RETADDR move area to callee saved frame size.
874  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
875  if (TailCallReturnAddrDelta < 0)
876    X86FI->setCalleeSavedFrameSize(
877      X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
878
879  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
880  // function, and use up to 128 bytes of stack space, don't have a frame
881  // pointer, calls, or dynamic alloca then we do not need to adjust the
882  // stack pointer (we fit in the Red Zone).
883  if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
884      !needsStackRealignment(MF) &&
885      !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
886      !MFI->hasCalls() &&                          // No calls.
887      !Subtarget->isTargetWin64()) {               // Win64 has no Red Zone
888    uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
889    if (HasFP) MinSize += SlotSize;
890    StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
891    MFI->setStackSize(StackSize);
892  } else if (Subtarget->isTargetWin64()) {
893    // We need to always allocate 32 bytes as register spill area.
894    // FIXME: We might reuse these 32 bytes for leaf functions.
895    StackSize += 32;
896    MFI->setStackSize(StackSize);
897  }
898
899  // Insert stack pointer adjustment for later moving of return addr.  Only
900  // applies to tail call optimized functions where the callee argument stack
901  // size is bigger than the callers.
902  if (TailCallReturnAddrDelta < 0) {
903    MachineInstr *MI =
904      BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
905              StackPtr)
906        .addReg(StackPtr)
907        .addImm(-TailCallReturnAddrDelta);
908    MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
909  }
910
911  // Mapping for machine moves:
912  //
913  //   DST: VirtualFP AND
914  //        SRC: VirtualFP              => DW_CFA_def_cfa_offset
915  //        ELSE                        => DW_CFA_def_cfa
916  //
917  //   SRC: VirtualFP AND
918  //        DST: Register               => DW_CFA_def_cfa_register
919  //
920  //   ELSE
921  //        OFFSET < 0                  => DW_CFA_offset_extended_sf
922  //        REG < 64                    => DW_CFA_offset + Reg
923  //        ELSE                        => DW_CFA_offset_extended
924
925  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
926  const TargetData *TD = MF.getTarget().getTargetData();
927  uint64_t NumBytes = 0;
928  int stackGrowth =
929    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
930     TargetFrameInfo::StackGrowsUp ?
931       TD->getPointerSize() : -TD->getPointerSize());
932
933  if (HasFP) {
934    // Calculate required stack adjustment.
935    uint64_t FrameSize = StackSize - SlotSize;
936    if (needsStackRealignment(MF))
937      FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
938
939    NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
940
941    // Get the offset of the stack slot for the EBP register, which is
942    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
943    // Update the frame offset adjustment.
944    MFI->setOffsetAdjustment(-NumBytes);
945
946    // Save EBP/RBP into the appropriate stack slot.
947    BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
948      .addReg(FramePtr, RegState::Kill);
949
950    if (needsFrameMoves) {
951      // Mark the place where EBP/RBP was saved.
952      unsigned FrameLabelId = MMI->NextLabelID();
953      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
954
955      // Define the current CFA rule to use the provided offset.
956      if (StackSize) {
957        MachineLocation SPDst(MachineLocation::VirtualFP);
958        MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
959        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
960      } else {
961        // FIXME: Verify & implement for FP
962        MachineLocation SPDst(StackPtr);
963        MachineLocation SPSrc(StackPtr, stackGrowth);
964        Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
965      }
966
967      // Change the rule for the FramePtr to be an "offset" rule.
968      MachineLocation FPDst(MachineLocation::VirtualFP,
969                            2 * stackGrowth);
970      MachineLocation FPSrc(FramePtr);
971      Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
972    }
973
974    // Update EBP with the new base value...
975    BuildMI(MBB, MBBI, DL,
976            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
977        .addReg(StackPtr);
978
979    if (needsFrameMoves) {
980      // Mark effective beginning of when frame pointer becomes valid.
981      unsigned FrameLabelId = MMI->NextLabelID();
982      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
983
984      // Define the current CFA to use the EBP/RBP register.
985      MachineLocation FPDst(FramePtr);
986      MachineLocation FPSrc(MachineLocation::VirtualFP);
987      Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
988    }
989
990    // Mark the FramePtr as live-in in every block except the entry.
991    for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
992         I != E; ++I)
993      I->addLiveIn(FramePtr);
994
995    // Realign stack
996    if (needsStackRealignment(MF)) {
997      MachineInstr *MI =
998        BuildMI(MBB, MBBI, DL,
999                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1000                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1001
1002      // The EFLAGS implicit def is dead.
1003      MI->getOperand(3).setIsDead();
1004    }
1005  } else {
1006    NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1007  }
1008
1009  // Skip the callee-saved push instructions.
1010  bool PushedRegs = false;
1011  int StackOffset = 2 * stackGrowth;
1012
1013  while (MBBI != MBB.end() &&
1014         (MBBI->getOpcode() == X86::PUSH32r ||
1015          MBBI->getOpcode() == X86::PUSH64r)) {
1016    PushedRegs = true;
1017    ++MBBI;
1018
1019    if (!HasFP && needsFrameMoves) {
1020      // Mark callee-saved push instruction.
1021      unsigned LabelId = MMI->NextLabelID();
1022      BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1023
1024      // Define the current CFA rule to use the provided offset.
1025      unsigned Ptr = StackSize ?
1026        MachineLocation::VirtualFP : StackPtr;
1027      MachineLocation SPDst(Ptr);
1028      MachineLocation SPSrc(Ptr, StackOffset);
1029      Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1030      StackOffset += stackGrowth;
1031    }
1032  }
1033
1034  DL = MBB.findDebugLoc(MBBI);
1035
1036  // Adjust stack pointer: ESP -= numbytes.
1037  if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1038    // Check, whether EAX is livein for this function.
1039    bool isEAXAlive = false;
1040    for (MachineRegisterInfo::livein_iterator
1041           II = MF.getRegInfo().livein_begin(),
1042           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1043      unsigned Reg = II->first;
1044      isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1045                    Reg == X86::AH || Reg == X86::AL);
1046    }
1047
1048    // Function prologue calls _alloca to probe the stack when allocating more
1049    // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1050    // to ensure that the guard pages used by the OS virtual memory manager are
1051    // allocated in correct sequence.
1052    if (!isEAXAlive) {
1053      BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1054        .addImm(NumBytes);
1055      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1056        .addExternalSymbol("_alloca");
1057    } else {
1058      // Save EAX
1059      BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1060        .addReg(X86::EAX, RegState::Kill);
1061
1062      // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1063      // allocated bytes for EAX.
1064      BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1065        .addImm(NumBytes - 4);
1066      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1067        .addExternalSymbol("_alloca");
1068
1069      // Restore EAX
1070      MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1071                                              X86::EAX),
1072                                      StackPtr, false, NumBytes - 4);
1073      MBB.insert(MBBI, MI);
1074    }
1075  } else if (NumBytes) {
1076    // If there is an SUB32ri of ESP immediately before this instruction, merge
1077    // the two. This can be the case when tail call elimination is enabled and
1078    // the callee has more arguments then the caller.
1079    NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1080
1081    // If there is an ADD32ri or SUB32ri of ESP immediately after this
1082    // instruction, merge the two instructions.
1083    mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1084
1085    if (NumBytes)
1086      emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1087  }
1088
1089  if ((NumBytes || PushedRegs) && needsFrameMoves) {
1090    // Mark end of stack pointer adjustment.
1091    unsigned LabelId = MMI->NextLabelID();
1092    BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1093
1094    if (!HasFP && NumBytes) {
1095      // Define the current CFA rule to use the provided offset.
1096      if (StackSize) {
1097        MachineLocation SPDst(MachineLocation::VirtualFP);
1098        MachineLocation SPSrc(MachineLocation::VirtualFP,
1099                              -StackSize + stackGrowth);
1100        Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1101      } else {
1102        // FIXME: Verify & implement for FP
1103        MachineLocation SPDst(StackPtr);
1104        MachineLocation SPSrc(StackPtr, stackGrowth);
1105        Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1106      }
1107    }
1108
1109    // Emit DWARF info specifying the offsets of the callee-saved registers.
1110    if (PushedRegs)
1111      emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1112  }
1113}
1114
1115void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1116                                   MachineBasicBlock &MBB) const {
1117  const MachineFrameInfo *MFI = MF.getFrameInfo();
1118  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1119  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1120  unsigned RetOpcode = MBBI->getOpcode();
1121  DebugLoc DL = MBBI->getDebugLoc();
1122
1123  switch (RetOpcode) {
1124  default:
1125    llvm_unreachable("Can only insert epilog into returning blocks");
1126  case X86::RET:
1127  case X86::RETI:
1128  case X86::TCRETURNdi:
1129  case X86::TCRETURNri:
1130  case X86::TCRETURNri64:
1131  case X86::TCRETURNdi64:
1132  case X86::EH_RETURN:
1133  case X86::EH_RETURN64:
1134  case X86::TAILJMPd:
1135  case X86::TAILJMPr:
1136  case X86::TAILJMPm:
1137    break;  // These are ok
1138  }
1139
1140  // Get the number of bytes to allocate from the FrameInfo.
1141  uint64_t StackSize = MFI->getStackSize();
1142  uint64_t MaxAlign  = MFI->getMaxAlignment();
1143  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1144  uint64_t NumBytes = 0;
1145
1146  if (hasFP(MF)) {
1147    // Calculate required stack adjustment.
1148    uint64_t FrameSize = StackSize - SlotSize;
1149    if (needsStackRealignment(MF))
1150      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1151
1152    NumBytes = FrameSize - CSSize;
1153
1154    // Pop EBP.
1155    BuildMI(MBB, MBBI, DL,
1156            TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1157  } else {
1158    NumBytes = StackSize - CSSize;
1159  }
1160
1161  // Skip the callee-saved pop instructions.
1162  MachineBasicBlock::iterator LastCSPop = MBBI;
1163  while (MBBI != MBB.begin()) {
1164    MachineBasicBlock::iterator PI = prior(MBBI);
1165    unsigned Opc = PI->getOpcode();
1166
1167    if (Opc != X86::POP32r && Opc != X86::POP64r &&
1168        !PI->getDesc().isTerminator())
1169      break;
1170
1171    --MBBI;
1172  }
1173
1174  DL = MBBI->getDebugLoc();
1175
1176  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1177  // instruction, merge the two instructions.
1178  if (NumBytes || MFI->hasVarSizedObjects())
1179    mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1180
1181  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1182  // slot before popping them off! Same applies for the case, when stack was
1183  // realigned.
1184  if (needsStackRealignment(MF)) {
1185    // We cannot use LEA here, because stack pointer was realigned. We need to
1186    // deallocate local frame back.
1187    if (CSSize) {
1188      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1189      MBBI = prior(LastCSPop);
1190    }
1191
1192    BuildMI(MBB, MBBI, DL,
1193            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1194            StackPtr).addReg(FramePtr);
1195  } else if (MFI->hasVarSizedObjects()) {
1196    if (CSSize) {
1197      unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1198      MachineInstr *MI =
1199        addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1200                        FramePtr, false, -CSSize);
1201      MBB.insert(MBBI, MI);
1202    } else {
1203      BuildMI(MBB, MBBI, DL,
1204              TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1205        .addReg(FramePtr);
1206    }
1207  } else if (NumBytes) {
1208    // Adjust stack pointer back: ESP += numbytes.
1209    emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1210  }
1211
1212  // We're returning from function via eh_return.
1213  if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1214    MBBI = prior(MBB.end());
1215    MachineOperand &DestAddr  = MBBI->getOperand(0);
1216    assert(DestAddr.isReg() && "Offset should be in register!");
1217    BuildMI(MBB, MBBI, DL,
1218            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1219            StackPtr).addReg(DestAddr.getReg());
1220  } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1221             RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1222    // Tail call return: adjust the stack pointer and jump to callee.
1223    MBBI = prior(MBB.end());
1224    MachineOperand &JumpTarget = MBBI->getOperand(0);
1225    MachineOperand &StackAdjust = MBBI->getOperand(1);
1226    assert(StackAdjust.isImm() && "Expecting immediate value.");
1227
1228    // Adjust stack pointer.
1229    int StackAdj = StackAdjust.getImm();
1230    int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1231    int Offset = 0;
1232    assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1233
1234    // Incoporate the retaddr area.
1235    Offset = StackAdj-MaxTCDelta;
1236    assert(Offset >= 0 && "Offset should never be negative");
1237
1238    if (Offset) {
1239      // Check for possible merge with preceeding ADD instruction.
1240      Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1241      emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1242    }
1243
1244    // Jump to label or value in register.
1245    if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1246      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1247        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1248    else if (RetOpcode== X86::TCRETURNri64)
1249      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1250    else
1251      BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1252
1253    // Delete the pseudo instruction TCRETURN.
1254    MBB.erase(MBBI);
1255  } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1256             (X86FI->getTCReturnAddrDelta() < 0)) {
1257    // Add the return addr area delta back since we are not tail calling.
1258    int delta = -1*X86FI->getTCReturnAddrDelta();
1259    MBBI = prior(MBB.end());
1260
1261    // Check for possible merge with preceeding ADD instruction.
1262    delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1263    emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1264  }
1265}
1266
1267unsigned X86RegisterInfo::getRARegister() const {
1268  return Is64Bit ? X86::RIP     // Should have dwarf #16.
1269                 : X86::EIP;    // Should have dwarf #8.
1270}
1271
1272unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1273  return hasFP(MF) ? FramePtr : StackPtr;
1274}
1275
1276void
1277X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1278  // Calculate amount of bytes used for return address storing
1279  int stackGrowth = (Is64Bit ? -8 : -4);
1280
1281  // Initial state of the frame pointer is esp+4.
1282  MachineLocation Dst(MachineLocation::VirtualFP);
1283  MachineLocation Src(StackPtr, stackGrowth);
1284  Moves.push_back(MachineMove(0, Dst, Src));
1285
1286  // Add return address to move list
1287  MachineLocation CSDst(StackPtr, stackGrowth);
1288  MachineLocation CSSrc(getRARegister());
1289  Moves.push_back(MachineMove(0, CSDst, CSSrc));
1290}
1291
1292unsigned X86RegisterInfo::getEHExceptionRegister() const {
1293  llvm_unreachable("What is the exception register");
1294  return 0;
1295}
1296
1297unsigned X86RegisterInfo::getEHHandlerRegister() const {
1298  llvm_unreachable("What is the exception handler register");
1299  return 0;
1300}
1301
1302namespace llvm {
1303unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1304  switch (VT.getSimpleVT().SimpleTy) {
1305  default: return Reg;
1306  case MVT::i8:
1307    if (High) {
1308      switch (Reg) {
1309      default: return 0;
1310      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1311        return X86::AH;
1312      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1313        return X86::DH;
1314      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1315        return X86::CH;
1316      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1317        return X86::BH;
1318      }
1319    } else {
1320      switch (Reg) {
1321      default: return 0;
1322      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1323        return X86::AL;
1324      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1325        return X86::DL;
1326      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1327        return X86::CL;
1328      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1329        return X86::BL;
1330      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1331        return X86::SIL;
1332      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1333        return X86::DIL;
1334      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1335        return X86::BPL;
1336      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1337        return X86::SPL;
1338      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1339        return X86::R8B;
1340      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1341        return X86::R9B;
1342      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1343        return X86::R10B;
1344      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1345        return X86::R11B;
1346      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1347        return X86::R12B;
1348      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1349        return X86::R13B;
1350      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1351        return X86::R14B;
1352      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1353        return X86::R15B;
1354      }
1355    }
1356  case MVT::i16:
1357    switch (Reg) {
1358    default: return Reg;
1359    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1360      return X86::AX;
1361    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1362      return X86::DX;
1363    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1364      return X86::CX;
1365    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1366      return X86::BX;
1367    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1368      return X86::SI;
1369    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1370      return X86::DI;
1371    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1372      return X86::BP;
1373    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1374      return X86::SP;
1375    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1376      return X86::R8W;
1377    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1378      return X86::R9W;
1379    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1380      return X86::R10W;
1381    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1382      return X86::R11W;
1383    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1384      return X86::R12W;
1385    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1386      return X86::R13W;
1387    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1388      return X86::R14W;
1389    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1390      return X86::R15W;
1391    }
1392  case MVT::i32:
1393    switch (Reg) {
1394    default: return Reg;
1395    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1396      return X86::EAX;
1397    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1398      return X86::EDX;
1399    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1400      return X86::ECX;
1401    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1402      return X86::EBX;
1403    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1404      return X86::ESI;
1405    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1406      return X86::EDI;
1407    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1408      return X86::EBP;
1409    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1410      return X86::ESP;
1411    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1412      return X86::R8D;
1413    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1414      return X86::R9D;
1415    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1416      return X86::R10D;
1417    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1418      return X86::R11D;
1419    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1420      return X86::R12D;
1421    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1422      return X86::R13D;
1423    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1424      return X86::R14D;
1425    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1426      return X86::R15D;
1427    }
1428  case MVT::i64:
1429    switch (Reg) {
1430    default: return Reg;
1431    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1432      return X86::RAX;
1433    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1434      return X86::RDX;
1435    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1436      return X86::RCX;
1437    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1438      return X86::RBX;
1439    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1440      return X86::RSI;
1441    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1442      return X86::RDI;
1443    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1444      return X86::RBP;
1445    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1446      return X86::RSP;
1447    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1448      return X86::R8;
1449    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1450      return X86::R9;
1451    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1452      return X86::R10;
1453    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1454      return X86::R11;
1455    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1456      return X86::R12;
1457    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1458      return X86::R13;
1459    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1460      return X86::R14;
1461    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1462      return X86::R15;
1463    }
1464  }
1465
1466  return Reg;
1467}
1468}
1469
1470#include "X86GenRegisterInfo.inc"
1471