X86RegisterInfo.cpp revision 7e9450107148895cd882dbaa21f17727b876998a 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Target/TargetFrameLowering.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/CommandLine.h"
42
43#define GET_REGINFO_MC_DESC
44#define GET_REGINFO_TARGET_DESC
45#include "X86GenRegisterInfo.inc"
46
47using namespace llvm;
48
49cl::opt<bool>
50ForceStackAlign("force-align-stack",
51                 cl::desc("Force align the stack to the minimum alignment"
52                           " needed for the function."),
53                 cl::init(false), cl::Hidden);
54
55X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
56                                 const TargetInstrInfo &tii)
57  : X86GenRegisterInfo(), TM(tm), TII(tii) {
58  // Cache some information.
59  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
60  Is64Bit = Subtarget->is64Bit();
61  IsWin64 = Subtarget->isTargetWin64();
62
63  if (Is64Bit) {
64    SlotSize = 8;
65    StackPtr = X86::RSP;
66    FramePtr = X86::RBP;
67  } else {
68    SlotSize = 4;
69    StackPtr = X86::ESP;
70    FramePtr = X86::EBP;
71  }
72}
73
74static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
75  if (!Subtarget->is64Bit()) {
76    if (Subtarget->isTargetDarwin()) {
77      if (isEH)
78        return DWARFFlavour::X86_32_DarwinEH;
79      else
80        return DWARFFlavour::X86_32_Generic;
81    } else if (Subtarget->isTargetCygMing()) {
82      // Unsupported by now, just quick fallback
83      return DWARFFlavour::X86_32_Generic;
84    } else {
85      return DWARFFlavour::X86_32_Generic;
86    }
87  }
88  return DWARFFlavour::X86_64;
89}
90
91/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
92/// specific numbering, used in debug info and exception tables.
93int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
94  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
95  unsigned Flavour = getFlavour(Subtarget, isEH);
96
97  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
98}
99
100/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
101int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
102  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
103  unsigned Flavour = getFlavour(Subtarget, isEH);
104
105  return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
106}
107
108/// getCompactUnwindRegNum - This function maps the register to the number for
109/// compact unwind encoding. Return -1 if the register isn't valid.
110int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
111  switch (getLLVMRegNum(RegNum, isEH)) {
112  case X86::EBX: case X86::RBX: return 1;
113  case X86::ECX: case X86::R12: return 2;
114  case X86::EDX: case X86::R13: return 3;
115  case X86::EDI: case X86::R14: return 4;
116  case X86::ESI: case X86::R15: return 5;
117  case X86::EBP: case X86::RBP: return 6;
118  }
119
120  return -1;
121}
122
123int
124X86RegisterInfo::getSEHRegNum(unsigned i) const {
125  int reg = getX86RegNum(i);
126  switch (i) {
127  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
128  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
129  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
130  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
131  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
132  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
133  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
134  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
135  case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
136  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
137  case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
138  case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
139    reg += 8;
140  }
141  return reg;
142}
143
144/// getX86RegNum - This function maps LLVM register identifiers to their X86
145/// specific numbering, which is used in various places encoding instructions.
146unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
147  switch(RegNo) {
148  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
149  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
150  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
151  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
152  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
153    return N86::ESP;
154  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
155    return N86::EBP;
156  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
157    return N86::ESI;
158  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
159    return N86::EDI;
160
161  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
162    return N86::EAX;
163  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
164    return N86::ECX;
165  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
166    return N86::EDX;
167  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
168    return N86::EBX;
169  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
170    return N86::ESP;
171  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
172    return N86::EBP;
173  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
174    return N86::ESI;
175  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
176    return N86::EDI;
177
178  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
179  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
180    return RegNo-X86::ST0;
181
182  case X86::XMM0: case X86::XMM8:
183  case X86::YMM0: case X86::YMM8: case X86::MM0:
184    return 0;
185  case X86::XMM1: case X86::XMM9:
186  case X86::YMM1: case X86::YMM9: case X86::MM1:
187    return 1;
188  case X86::XMM2: case X86::XMM10:
189  case X86::YMM2: case X86::YMM10: case X86::MM2:
190    return 2;
191  case X86::XMM3: case X86::XMM11:
192  case X86::YMM3: case X86::YMM11: case X86::MM3:
193    return 3;
194  case X86::XMM4: case X86::XMM12:
195  case X86::YMM4: case X86::YMM12: case X86::MM4:
196    return 4;
197  case X86::XMM5: case X86::XMM13:
198  case X86::YMM5: case X86::YMM13: case X86::MM5:
199    return 5;
200  case X86::XMM6: case X86::XMM14:
201  case X86::YMM6: case X86::YMM14: case X86::MM6:
202    return 6;
203  case X86::XMM7: case X86::XMM15:
204  case X86::YMM7: case X86::YMM15: case X86::MM7:
205    return 7;
206
207  case X86::ES: return 0;
208  case X86::CS: return 1;
209  case X86::SS: return 2;
210  case X86::DS: return 3;
211  case X86::FS: return 4;
212  case X86::GS: return 5;
213
214  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
215  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
216  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
217  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
218  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
219  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
220  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
221  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
222
223  // Pseudo index registers are equivalent to a "none"
224  // scaled index (See Intel Manual 2A, table 2-3)
225  case X86::EIZ:
226  case X86::RIZ:
227    return 4;
228
229  default:
230    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
231    llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
232    return 0;
233  }
234}
235
236const TargetRegisterClass *
237X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
238                                          const TargetRegisterClass *B,
239                                          unsigned SubIdx) const {
240  switch (SubIdx) {
241  default: return 0;
242  case X86::sub_8bit:
243    if (B == &X86::GR8RegClass) {
244      if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
245        return A;
246    } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
247      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
248          A == &X86::GR64_NOREXRegClass ||
249          A == &X86::GR64_NOSPRegClass ||
250          A == &X86::GR64_NOREX_NOSPRegClass)
251        return &X86::GR64_ABCDRegClass;
252      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
253               A == &X86::GR32_NOREXRegClass ||
254               A == &X86::GR32_NOSPRegClass)
255        return &X86::GR32_ABCDRegClass;
256      else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
257               A == &X86::GR16_NOREXRegClass)
258        return &X86::GR16_ABCDRegClass;
259    } else if (B == &X86::GR8_NOREXRegClass) {
260      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
261          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
262        return &X86::GR64_NOREXRegClass;
263      else if (A == &X86::GR64_ABCDRegClass)
264        return &X86::GR64_ABCDRegClass;
265      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
266               A == &X86::GR32_NOSPRegClass)
267        return &X86::GR32_NOREXRegClass;
268      else if (A == &X86::GR32_ABCDRegClass)
269        return &X86::GR32_ABCDRegClass;
270      else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
271        return &X86::GR16_NOREXRegClass;
272      else if (A == &X86::GR16_ABCDRegClass)
273        return &X86::GR16_ABCDRegClass;
274    }
275    break;
276  case X86::sub_8bit_hi:
277    if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
278      switch (A->getSize()) {
279        case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
280        case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
281        case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
282        default: return 0;
283      }
284    break;
285  case X86::sub_16bit:
286    if (B == &X86::GR16RegClass) {
287      if (A->getSize() == 4 || A->getSize() == 8)
288        return A;
289    } else if (B == &X86::GR16_ABCDRegClass) {
290      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
291          A == &X86::GR64_NOREXRegClass ||
292          A == &X86::GR64_NOSPRegClass ||
293          A == &X86::GR64_NOREX_NOSPRegClass)
294        return &X86::GR64_ABCDRegClass;
295      else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
296               A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
297        return &X86::GR32_ABCDRegClass;
298    } else if (B == &X86::GR16_NOREXRegClass) {
299      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
300          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
301        return &X86::GR64_NOREXRegClass;
302      else if (A == &X86::GR64_ABCDRegClass)
303        return &X86::GR64_ABCDRegClass;
304      else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
305               A == &X86::GR32_NOSPRegClass)
306        return &X86::GR32_NOREXRegClass;
307      else if (A == &X86::GR32_ABCDRegClass)
308        return &X86::GR64_ABCDRegClass;
309    }
310    break;
311  case X86::sub_32bit:
312    if (B == &X86::GR32RegClass) {
313      if (A->getSize() == 8)
314        return A;
315    } else if (B == &X86::GR32_NOSPRegClass) {
316      if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
317        return &X86::GR64_NOSPRegClass;
318      if (A->getSize() == 8)
319        return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
320    } else if (B == &X86::GR32_ABCDRegClass) {
321      if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
322          A == &X86::GR64_NOREXRegClass ||
323          A == &X86::GR64_NOSPRegClass ||
324          A == &X86::GR64_NOREX_NOSPRegClass)
325        return &X86::GR64_ABCDRegClass;
326    } else if (B == &X86::GR32_NOREXRegClass) {
327      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
328        return &X86::GR64_NOREXRegClass;
329      else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
330        return &X86::GR64_NOREX_NOSPRegClass;
331      else if (A == &X86::GR64_ABCDRegClass)
332        return &X86::GR64_ABCDRegClass;
333    } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
334      if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
335          A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
336        return &X86::GR64_NOREX_NOSPRegClass;
337      else if (A == &X86::GR64_ABCDRegClass)
338        return &X86::GR64_ABCDRegClass;
339    }
340    break;
341  case X86::sub_ss:
342    if (B == &X86::FR32RegClass)
343      return A;
344    break;
345  case X86::sub_sd:
346    if (B == &X86::FR64RegClass)
347      return A;
348    break;
349  case X86::sub_xmm:
350    if (B == &X86::VR128RegClass)
351      return A;
352    break;
353  }
354  return 0;
355}
356
357const TargetRegisterClass*
358X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
359  const TargetRegisterClass *Super = RC;
360  TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
361  do {
362    switch (Super->getID()) {
363    case X86::GR8RegClassID:
364    case X86::GR16RegClassID:
365    case X86::GR32RegClassID:
366    case X86::GR64RegClassID:
367    case X86::FR32RegClassID:
368    case X86::FR64RegClassID:
369    case X86::RFP32RegClassID:
370    case X86::RFP64RegClassID:
371    case X86::RFP80RegClassID:
372    case X86::VR128RegClassID:
373    case X86::VR256RegClassID:
374      // Don't return a super-class that would shrink the spill size.
375      // That can happen with the vector and float classes.
376      if (Super->getSize() == RC->getSize())
377        return Super;
378    }
379    Super = *I++;
380  } while (Super);
381  return RC;
382}
383
384const TargetRegisterClass *
385X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
386  switch (Kind) {
387  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
388  case 0: // Normal GPRs.
389    if (TM.getSubtarget<X86Subtarget>().is64Bit())
390      return &X86::GR64RegClass;
391    return &X86::GR32RegClass;
392  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
393    if (TM.getSubtarget<X86Subtarget>().is64Bit())
394      return &X86::GR64_NOSPRegClass;
395    return &X86::GR32_NOSPRegClass;
396  case 2: // Available for tailcall (not callee-saved GPRs).
397    if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
398      return &X86::GR64_TCW64RegClass;
399    if (TM.getSubtarget<X86Subtarget>().is64Bit())
400      return &X86::GR64_TCRegClass;
401    return &X86::GR32_TCRegClass;
402  }
403}
404
405const TargetRegisterClass *
406X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
407  if (RC == &X86::CCRRegClass) {
408    if (Is64Bit)
409      return &X86::GR64RegClass;
410    else
411      return &X86::GR32RegClass;
412  }
413  return RC;
414}
415
416unsigned
417X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
418                                     MachineFunction &MF) const {
419  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
420
421  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
422  switch (RC->getID()) {
423  default:
424    return 0;
425  case X86::GR32RegClassID:
426    return 4 - FPDiff;
427  case X86::GR64RegClassID:
428    return 12 - FPDiff;
429  case X86::VR128RegClassID:
430    return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
431  case X86::VR64RegClassID:
432    return 4;
433  }
434}
435
436const unsigned *
437X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
438  bool callsEHReturn = false;
439  bool ghcCall = false;
440
441  if (MF) {
442    callsEHReturn = MF->getMMI().callsEHReturn();
443    const Function *F = MF->getFunction();
444    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
445  }
446
447  static const unsigned GhcCalleeSavedRegs[] = {
448    0
449  };
450
451  static const unsigned CalleeSavedRegs32Bit[] = {
452    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
453  };
454
455  static const unsigned CalleeSavedRegs32EHRet[] = {
456    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
457  };
458
459  static const unsigned CalleeSavedRegs64Bit[] = {
460    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
461  };
462
463  static const unsigned CalleeSavedRegs64EHRet[] = {
464    X86::RAX, X86::RDX, X86::RBX, X86::R12,
465    X86::R13, X86::R14, X86::R15, X86::RBP, 0
466  };
467
468  static const unsigned CalleeSavedRegsWin64[] = {
469    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
470    X86::R12,   X86::R13,   X86::R14,   X86::R15,
471    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
472    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
473    X86::XMM14, X86::XMM15, 0
474  };
475
476  if (ghcCall) {
477    return GhcCalleeSavedRegs;
478  } else if (Is64Bit) {
479    if (IsWin64)
480      return CalleeSavedRegsWin64;
481    else
482      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
483  } else {
484    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
485  }
486}
487
488BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
489  BitVector Reserved(getNumRegs());
490  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
491
492  // Set the stack-pointer register and its aliases as reserved.
493  Reserved.set(X86::RSP);
494  Reserved.set(X86::ESP);
495  Reserved.set(X86::SP);
496  Reserved.set(X86::SPL);
497
498  // Set the instruction pointer register and its aliases as reserved.
499  Reserved.set(X86::RIP);
500  Reserved.set(X86::EIP);
501  Reserved.set(X86::IP);
502
503  // Set the frame-pointer register and its aliases as reserved if needed.
504  if (TFI->hasFP(MF)) {
505    Reserved.set(X86::RBP);
506    Reserved.set(X86::EBP);
507    Reserved.set(X86::BP);
508    Reserved.set(X86::BPL);
509  }
510
511  // Mark the segment registers as reserved.
512  Reserved.set(X86::CS);
513  Reserved.set(X86::SS);
514  Reserved.set(X86::DS);
515  Reserved.set(X86::ES);
516  Reserved.set(X86::FS);
517  Reserved.set(X86::GS);
518
519  // Reserve the registers that only exist in 64-bit mode.
520  if (!Is64Bit) {
521    // These 8-bit registers are part of the x86-64 extension even though their
522    // super-registers are old 32-bits.
523    Reserved.set(X86::SIL);
524    Reserved.set(X86::DIL);
525    Reserved.set(X86::BPL);
526    Reserved.set(X86::SPL);
527
528    for (unsigned n = 0; n != 8; ++n) {
529      // R8, R9, ...
530      const unsigned GPR64[] = {
531        X86::R8,  X86::R9,  X86::R10, X86::R11,
532        X86::R12, X86::R13, X86::R14, X86::R15
533      };
534      for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
535        Reserved.set(Reg);
536
537      // XMM8, XMM9, ...
538      assert(X86::XMM15 == X86::XMM8+7);
539      for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
540           ++AI)
541        Reserved.set(Reg);
542    }
543  }
544
545  return Reserved;
546}
547
548//===----------------------------------------------------------------------===//
549// Stack Frame Processing methods
550//===----------------------------------------------------------------------===//
551
552bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
553  const MachineFrameInfo *MFI = MF.getFrameInfo();
554  return (RealignStack &&
555          !MFI->hasVarSizedObjects());
556}
557
558bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
559  const MachineFrameInfo *MFI = MF.getFrameInfo();
560  const Function *F = MF.getFunction();
561  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
562  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
563                               F->hasFnAttr(Attribute::StackAlignment));
564
565  // FIXME: Currently we don't support stack realignment for functions with
566  //        variable-sized allocas.
567  // FIXME: It's more complicated than this...
568  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
569    report_fatal_error(
570      "Stack realignment in presence of dynamic allocas is not supported");
571
572  // If we've requested that we force align the stack do so now.
573  if (ForceStackAlign)
574    return canRealignStack(MF);
575
576  return requiresRealignment && canRealignStack(MF);
577}
578
579bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
580                                           unsigned Reg, int &FrameIdx) const {
581  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
582
583  if (Reg == FramePtr && TFI->hasFP(MF)) {
584    FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
585    return true;
586  }
587  return false;
588}
589
590static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
591  if (is64Bit) {
592    if (isInt<8>(Imm))
593      return X86::SUB64ri8;
594    return X86::SUB64ri32;
595  } else {
596    if (isInt<8>(Imm))
597      return X86::SUB32ri8;
598    return X86::SUB32ri;
599  }
600}
601
602static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
603  if (is64Bit) {
604    if (isInt<8>(Imm))
605      return X86::ADD64ri8;
606    return X86::ADD64ri32;
607  } else {
608    if (isInt<8>(Imm))
609      return X86::ADD32ri8;
610    return X86::ADD32ri;
611  }
612}
613
614void X86RegisterInfo::
615eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
616                              MachineBasicBlock::iterator I) const {
617  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
618  bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
619  int Opcode = I->getOpcode();
620  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
621  DebugLoc DL = I->getDebugLoc();
622  uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
623  uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
624  I = MBB.erase(I);
625
626  if (!reseveCallFrame) {
627    // If the stack pointer can be changed after prologue, turn the
628    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
629    // adjcallstackdown instruction into 'add ESP, <amt>'
630    // TODO: consider using push / pop instead of sub + store / add
631    if (Amount == 0)
632      return;
633
634    // We need to keep the stack aligned properly.  To do this, we round the
635    // amount of space needed for the outgoing arguments up to the next
636    // alignment boundary.
637    unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
638    Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
639
640    MachineInstr *New = 0;
641    if (Opcode == TII.getCallFrameSetupOpcode()) {
642      New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
643                    StackPtr)
644        .addReg(StackPtr)
645        .addImm(Amount);
646    } else {
647      assert(Opcode == TII.getCallFrameDestroyOpcode());
648
649      // Factor out the amount the callee already popped.
650      Amount -= CalleeAmt;
651
652      if (Amount) {
653        unsigned Opc = getADDriOpcode(Is64Bit, Amount);
654        New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
655          .addReg(StackPtr).addImm(Amount);
656      }
657    }
658
659    if (New) {
660      // The EFLAGS implicit def is dead.
661      New->getOperand(3).setIsDead();
662
663      // Replace the pseudo instruction with a new instruction.
664      MBB.insert(I, New);
665    }
666
667    return;
668  }
669
670  if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
671    // If we are performing frame pointer elimination and if the callee pops
672    // something off the stack pointer, add it back.  We do this until we have
673    // more advanced stack pointer tracking ability.
674    unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
675    MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
676      .addReg(StackPtr).addImm(CalleeAmt);
677
678    // The EFLAGS implicit def is dead.
679    New->getOperand(3).setIsDead();
680
681    // We are not tracking the stack pointer adjustment by the callee, so make
682    // sure we restore the stack pointer immediately after the call, there may
683    // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
684    MachineBasicBlock::iterator B = MBB.begin();
685    while (I != B && !llvm::prior(I)->getDesc().isCall())
686      --I;
687    MBB.insert(I, New);
688  }
689}
690
691void
692X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
693                                     int SPAdj, RegScavenger *RS) const{
694  assert(SPAdj == 0 && "Unexpected");
695
696  unsigned i = 0;
697  MachineInstr &MI = *II;
698  MachineFunction &MF = *MI.getParent()->getParent();
699  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
700
701  while (!MI.getOperand(i).isFI()) {
702    ++i;
703    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
704  }
705
706  int FrameIndex = MI.getOperand(i).getIndex();
707  unsigned BasePtr;
708
709  unsigned Opc = MI.getOpcode();
710  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
711  if (needsStackRealignment(MF))
712    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
713  else if (AfterFPPop)
714    BasePtr = StackPtr;
715  else
716    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
717
718  // This must be part of a four operand memory reference.  Replace the
719  // FrameIndex with base register with EBP.  Add an offset to the offset.
720  MI.getOperand(i).ChangeToRegister(BasePtr, false);
721
722  // Now add the frame object offset to the offset from EBP.
723  int FIOffset;
724  if (AfterFPPop) {
725    // Tail call jmp happens after FP is popped.
726    const MachineFrameInfo *MFI = MF.getFrameInfo();
727    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
728  } else
729    FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
730
731  if (MI.getOperand(i+3).isImm()) {
732    // Offset is a 32-bit integer.
733    int Imm = (int)(MI.getOperand(i + 3).getImm());
734    int Offset = FIOffset + Imm;
735    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
736           "Requesting 64-bit offset in 32-bit immediate!");
737    MI.getOperand(i + 3).ChangeToImmediate(Offset);
738  } else {
739    // Offset is symbolic. This is extremely rare.
740    uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
741    MI.getOperand(i+3).setOffset(Offset);
742  }
743}
744
745unsigned X86RegisterInfo::getRARegister() const {
746  return Is64Bit ? X86::RIP     // Should have dwarf #16.
747                 : X86::EIP;    // Should have dwarf #8.
748}
749
750unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
751  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
752  return TFI->hasFP(MF) ? FramePtr : StackPtr;
753}
754
755unsigned X86RegisterInfo::getEHExceptionRegister() const {
756  llvm_unreachable("What is the exception register");
757  return 0;
758}
759
760unsigned X86RegisterInfo::getEHHandlerRegister() const {
761  llvm_unreachable("What is the exception handler register");
762  return 0;
763}
764
765namespace llvm {
766unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
767  switch (VT.getSimpleVT().SimpleTy) {
768  default: return Reg;
769  case MVT::i8:
770    if (High) {
771      switch (Reg) {
772      default: return 0;
773      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
774        return X86::AH;
775      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
776        return X86::DH;
777      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
778        return X86::CH;
779      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
780        return X86::BH;
781      }
782    } else {
783      switch (Reg) {
784      default: return 0;
785      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
786        return X86::AL;
787      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
788        return X86::DL;
789      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
790        return X86::CL;
791      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
792        return X86::BL;
793      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
794        return X86::SIL;
795      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
796        return X86::DIL;
797      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
798        return X86::BPL;
799      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
800        return X86::SPL;
801      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
802        return X86::R8B;
803      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
804        return X86::R9B;
805      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
806        return X86::R10B;
807      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
808        return X86::R11B;
809      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
810        return X86::R12B;
811      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
812        return X86::R13B;
813      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
814        return X86::R14B;
815      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
816        return X86::R15B;
817      }
818    }
819  case MVT::i16:
820    switch (Reg) {
821    default: return Reg;
822    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
823      return X86::AX;
824    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
825      return X86::DX;
826    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
827      return X86::CX;
828    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
829      return X86::BX;
830    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
831      return X86::SI;
832    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
833      return X86::DI;
834    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
835      return X86::BP;
836    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
837      return X86::SP;
838    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
839      return X86::R8W;
840    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
841      return X86::R9W;
842    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
843      return X86::R10W;
844    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
845      return X86::R11W;
846    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
847      return X86::R12W;
848    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
849      return X86::R13W;
850    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
851      return X86::R14W;
852    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
853      return X86::R15W;
854    }
855  case MVT::i32:
856    switch (Reg) {
857    default: return Reg;
858    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
859      return X86::EAX;
860    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
861      return X86::EDX;
862    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
863      return X86::ECX;
864    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
865      return X86::EBX;
866    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
867      return X86::ESI;
868    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
869      return X86::EDI;
870    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
871      return X86::EBP;
872    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
873      return X86::ESP;
874    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
875      return X86::R8D;
876    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
877      return X86::R9D;
878    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
879      return X86::R10D;
880    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
881      return X86::R11D;
882    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
883      return X86::R12D;
884    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
885      return X86::R13D;
886    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
887      return X86::R14D;
888    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
889      return X86::R15D;
890    }
891  case MVT::i64:
892    switch (Reg) {
893    default: return Reg;
894    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
895      return X86::RAX;
896    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
897      return X86::RDX;
898    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
899      return X86::RCX;
900    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
901      return X86::RBX;
902    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
903      return X86::RSI;
904    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
905      return X86::RDI;
906    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
907      return X86::RBP;
908    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
909      return X86::RSP;
910    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
911      return X86::R8;
912    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
913      return X86::R9;
914    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
915      return X86::R10;
916    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
917      return X86::R11;
918    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
919      return X86::R12;
920    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
921      return X86::R13;
922    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
923      return X86::R14;
924    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
925      return X86::R15;
926    }
927  }
928
929  return Reg;
930}
931}
932
933namespace {
934  struct MSAH : public MachineFunctionPass {
935    static char ID;
936    MSAH() : MachineFunctionPass(ID) {}
937
938    virtual bool runOnMachineFunction(MachineFunction &MF) {
939      const X86TargetMachine *TM =
940        static_cast<const X86TargetMachine *>(&MF.getTarget());
941      const TargetFrameLowering *TFI = TM->getFrameLowering();
942      MachineRegisterInfo &RI = MF.getRegInfo();
943      X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
944      unsigned StackAlignment = TFI->getStackAlignment();
945
946      // Be over-conservative: scan over all vreg defs and find whether vector
947      // registers are used. If yes, there is a possibility that vector register
948      // will be spilled and thus require dynamic stack realignment.
949      for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
950        unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
951        if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
952          FuncInfo->setReserveFP(true);
953          return true;
954        }
955      }
956      // Nothing to do
957      return false;
958    }
959
960    virtual const char *getPassName() const {
961      return "X86 Maximal Stack Alignment Check";
962    }
963
964    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
965      AU.setPreservesCFG();
966      MachineFunctionPass::getAnalysisUsage(AU);
967    }
968  };
969
970  char MSAH::ID = 0;
971}
972
973FunctionPass*
974llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
975