X86RegisterInfo.cpp revision 933be3318be64ec08687ac3ee92e8405662fb88f
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the MRegisterInfo class. This 11// file is responsible for the frame pointer elimination optimization on X86. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86RegisterInfo.h" 17#include "X86InstrBuilder.h" 18#include "llvm/Constants.h" 19#include "llvm/Type.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/Target/TargetFrameInfo.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/ADT/STLExtras.h" 29#include <iostream> 30 31using namespace llvm; 32 33namespace { 34 cl::opt<bool> 35 NoFusing("disable-spill-fusing", 36 cl::desc("Disable fusing of spill code into instructions")); 37 cl::opt<bool> 38 PrintFailedFusing("print-failed-fuse-candidates", 39 cl::desc("Print instructions that the allocator wants to" 40 " fuse, but the X86 backend currently can't"), 41 cl::Hidden); 42} 43 44X86RegisterInfo::X86RegisterInfo() 45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {} 46 47void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 48 MachineBasicBlock::iterator MI, 49 unsigned SrcReg, int FrameIdx, 50 const TargetRegisterClass *RC) const { 51 unsigned Opc; 52 if (RC == &X86::R32RegClass) { 53 Opc = X86::MOV32mr; 54 } else if (RC == &X86::R8RegClass) { 55 Opc = X86::MOV8mr; 56 } else if (RC == &X86::R16RegClass) { 57 Opc = X86::MOV16mr; 58 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 59 Opc = X86::FpST64m; 60 } else if (RC == &X86::FR32RegClass) { 61 Opc = X86::MOVSSmr; 62 } else if (RC == &X86::FR64RegClass) { 63 Opc = X86::MOVSDmr; 64 } else if (RC == &X86::V4F32RegClass) { 65 Opc = X86::MOVAPSmr; 66 } else if (RC == &X86::V2F64RegClass) { 67 Opc = X86::MOVAPDmr; 68 } else { 69 assert(0 && "Unknown regclass"); 70 abort(); 71 } 72 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg); 73} 74 75void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator MI, 77 unsigned DestReg, int FrameIdx, 78 const TargetRegisterClass *RC) const{ 79 unsigned Opc; 80 if (RC == &X86::R32RegClass) { 81 Opc = X86::MOV32rm; 82 } else if (RC == &X86::R8RegClass) { 83 Opc = X86::MOV8rm; 84 } else if (RC == &X86::R16RegClass) { 85 Opc = X86::MOV16rm; 86 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 87 Opc = X86::FpLD64m; 88 } else if (RC == &X86::FR32RegClass) { 89 Opc = X86::MOVSSrm; 90 } else if (RC == &X86::FR64RegClass) { 91 Opc = X86::MOVSDrm; 92 } else if (RC == &X86::V4F32RegClass) { 93 Opc = X86::MOVAPSrm; 94 } else if (RC == &X86::V2F64RegClass) { 95 Opc = X86::MOVAPDrm; 96 } else { 97 assert(0 && "Unknown regclass"); 98 abort(); 99 } 100 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx); 101} 102 103void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MI, 105 unsigned DestReg, unsigned SrcReg, 106 const TargetRegisterClass *RC) const { 107 unsigned Opc; 108 if (RC == &X86::R32RegClass) { 109 Opc = X86::MOV32rr; 110 } else if (RC == &X86::R8RegClass) { 111 Opc = X86::MOV8rr; 112 } else if (RC == &X86::R16RegClass) { 113 Opc = X86::MOV16rr; 114 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 115 Opc = X86::FpMOV; 116 } else if (RC == &X86::FR32RegClass) { 117 Opc = X86::FsMOVAPSrr; 118 } else if (RC == &X86::FR64RegClass) { 119 Opc = X86::FsMOVAPDrr; 120 } else if (RC == &X86::V4F32RegClass) { 121 Opc = X86::MOVAPSrr; 122 } else if (RC == &X86::V2F64RegClass) { 123 Opc = X86::MOVAPDrr; 124 } else { 125 assert(0 && "Unknown regclass"); 126 abort(); 127 } 128 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg); 129} 130 131 132static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex, 133 MachineInstr *MI) { 134 return addFrameReference(BuildMI(Opcode, 4), FrameIndex); 135} 136 137static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex, 138 MachineInstr *MI) { 139 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 140 .addReg(MI->getOperand(1).getReg()); 141} 142 143static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex, 144 MachineInstr *MI) { 145 return addFrameReference(BuildMI(Opcode, 6), FrameIndex) 146 .addReg(MI->getOperand(1).getReg()) 147 .addZImm(MI->getOperand(2).getImmedValue()); 148} 149 150static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex, 151 MachineInstr *MI) { 152 if (MI->getOperand(1).isImmediate()) 153 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 154 .addZImm(MI->getOperand(1).getImmedValue()); 155 else if (MI->getOperand(1).isGlobalAddress()) 156 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 157 .addGlobalAddress(MI->getOperand(1).getGlobal()); 158 assert(0 && "Unknown operand for MakeMI!"); 159 return 0; 160} 161 162static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex, 163 MachineInstr *MI) { 164 const MachineOperand& op = MI->getOperand(0); 165 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()), 166 FrameIndex); 167} 168 169static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex, 170 MachineInstr *MI) { 171 const MachineOperand& op = MI->getOperand(0); 172 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()), 173 FrameIndex).addZImm(MI->getOperand(2).getImmedValue()); 174} 175 176 177MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI, 178 unsigned i, 179 int FrameIndex) const { 180 if (NoFusing) return NULL; 181 182 /// FIXME: This should obviously be autogenerated by tablegen when patterns 183 /// are available! 184 MachineBasicBlock& MBB = *MI->getParent(); 185 if (i == 0) { 186 switch(MI->getOpcode()) { 187 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI); 188 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI); 189 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI); 190 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI); 191 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI); 192 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI); 193 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI); 194 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI); 195 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI); 196 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI); 197 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI); 198 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI); 199 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI); 200 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI); 201 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI); 202 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI); 203 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI); 204 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI); 205 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI); 206 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI); 207 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI); 208 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI); 209 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI); 210 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI); 211 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI); 212 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI); 213 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI); 214 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI); 215 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI); 216 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI); 217 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI); 218 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI); 219 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI); 220 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI); 221 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI); 222 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI); 223 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); 224 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); 225 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI); 226 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI); 227 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI); 228 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI); 229 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI); 230 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI); 231 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); 232 case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI); 233 case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI); 234 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); 235 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI); 236 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI); 237 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI); 238 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI); 239 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI); 240 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI); 241 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI); 242 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI); 243 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI); 244 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI); 245 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI); 246 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI); 247 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI); 248 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI); 249 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI); 250 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI); 251 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI); 252 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI); 253 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI); 254 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI); 255 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI); 256 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI); 257 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI); 258 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI); 259 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI); 260 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI); 261 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI); 262 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI); 263 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI); 264 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI); 265 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI); 266 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI); 267 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI); 268 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI); 269 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI); 270 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI); 271 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI); 272 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI); 273 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI); 274 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI); 275 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI); 276 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI); 277 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI); 278 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI); 279 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI); 280 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI); 281 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI); 282 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI); 283 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI); 284 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI); 285 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI); 286 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI); 287 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI); 288 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI); 289 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI); 290 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI); 291 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI); 292 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI); 293 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI); 294 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI); 295 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI); 296 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI); 297 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI); 298 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI); 299 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI); 300 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI); 301 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI); 302 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI); 303 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI); 304 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI); 305 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI); 306 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI); 307 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI); 308 case X86::TEST8rr: return MakeMRInst(X86::TEST8mr ,FrameIndex, MI); 309 case X86::TEST16rr: return MakeMRInst(X86::TEST16mr,FrameIndex, MI); 310 case X86::TEST32rr: return MakeMRInst(X86::TEST32mr,FrameIndex, MI); 311 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI); 312 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI); 313 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI); 314 case X86::CMP8rr: return MakeMRInst(X86::CMP8mr , FrameIndex, MI); 315 case X86::CMP16rr: return MakeMRInst(X86::CMP16mr, FrameIndex, MI); 316 case X86::CMP32rr: return MakeMRInst(X86::CMP32mr, FrameIndex, MI); 317 case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI); 318 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); 319 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); 320 // Alias scalar SSE instructions 321 case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); 322 case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); 323 // Scalar SSE instructions 324 case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); 325 case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); 326#if 0 327 // Packed SSE instructions 328 // FIXME: Can't use these until we are spilling XMM registers to 329 // 128-bit locations. 330 case X86::MOVAPSrr: return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI); 331 case X86::MOVAPDrr: return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI); 332#endif 333 } 334 } else if (i == 1) { 335 switch(MI->getOpcode()) { 336 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI); 337 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI); 338 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI); 339 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI); 340 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI); 341 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI); 342 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI); 343 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI); 344 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI); 345 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI); 346 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI); 347 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI); 348 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI); 349 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI); 350 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI); 351 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI); 352 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI); 353 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI); 354 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI); 355 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI); 356 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI); 357 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI); 358 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI); 359 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI); 360 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI); 361 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI); 362 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI); 363 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI); 364 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI); 365 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI); 366 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI); 367 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI); 368 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI); 369 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI); 370 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI); 371 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI); 372 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI); 373 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI); 374 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI); 375 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI); 376 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI); 377 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI); 378 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI); 379 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI); 380 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI); 381 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI); 382 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI); 383 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI); 384 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI); 385 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI); 386 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI); 387 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI); 388 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI); 389 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI); 390 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI); 391 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); 392 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); 393 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI); 394 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI); 395 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI); 396 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI); 397 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI); 398 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI); 399 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI); 400 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI); 401 case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI); 402 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI); 403 // Alias scalar SSE instructions 404 case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI); 405 case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI); 406 // Scalar SSE instructions 407 case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI); 408 case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI); 409 case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI); 410 case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI); 411 case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI); 412 case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI); 413 case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI); 414 case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI); 415 case X86::SQRTSSrr: return MakeRMInst(X86::SQRTSSrm, FrameIndex, MI); 416 case X86::SQRTSDrr: return MakeRMInst(X86::SQRTSDrm, FrameIndex, MI); 417 case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI); 418 case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI); 419 case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI); 420 case X86::ADDSDrr: return MakeRMInst(X86::ADDSDrm, FrameIndex, MI); 421 case X86::MULSSrr: return MakeRMInst(X86::MULSSrm, FrameIndex, MI); 422 case X86::MULSDrr: return MakeRMInst(X86::MULSDrm, FrameIndex, MI); 423 case X86::DIVSSrr: return MakeRMInst(X86::DIVSSrm, FrameIndex, MI); 424 case X86::DIVSDrr: return MakeRMInst(X86::DIVSDrm, FrameIndex, MI); 425 case X86::SUBSSrr: return MakeRMInst(X86::SUBSSrm, FrameIndex, MI); 426 case X86::SUBSDrr: return MakeRMInst(X86::SUBSDrm, FrameIndex, MI); 427 case X86::CMPSSrr: return MakeRMInst(X86::CMPSSrm, FrameIndex, MI); 428 case X86::CMPSDrr: return MakeRMInst(X86::CMPSDrm, FrameIndex, MI); 429#if 0 430 // Packed SSE instructions 431 // FIXME: Can't use these until we are spilling XMM registers to 432 // 128-bit locations. 433 case X86::ANDPSrr: return MakeRMInst(X86::ANDPSrm, FrameIndex, MI); 434 case X86::ANDPDrr: return MakeRMInst(X86::ANDPDrm, FrameIndex, MI); 435 case X86::ORPSrr: return MakeRMInst(X86::ORPSrm, FrameIndex, MI); 436 case X86::ORPDrr: return MakeRMInst(X86::ORPDrm, FrameIndex, MI); 437 case X86::XORPSrr: return MakeRMInst(X86::XORPSrm, FrameIndex, MI); 438 case X86::XORPDrr: return MakeRMInst(X86::XORPDrm, FrameIndex, MI); 439 case X86::ANDNPSrr: return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI); 440 case X86::ANDNPDrr: return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI); 441 case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI); 442 case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI); 443#endif 444 } 445 } 446 if (PrintFailedFusing) 447 std::cerr << "We failed to fuse: " << *MI; 448 return NULL; 449} 450 451//===----------------------------------------------------------------------===// 452// Stack Frame Processing methods 453//===----------------------------------------------------------------------===// 454 455// hasFP - Return true if the specified function should have a dedicated frame 456// pointer register. This is true if the function has variable sized allocas or 457// if frame pointer elimination is disabled. 458// 459static bool hasFP(MachineFunction &MF) { 460 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 461} 462 463void X86RegisterInfo:: 464eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 465 MachineBasicBlock::iterator I) const { 466 if (hasFP(MF)) { 467 // If we have a frame pointer, turn the adjcallstackup instruction into a 468 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP, 469 // <amt>' 470 MachineInstr *Old = I; 471 unsigned Amount = Old->getOperand(0).getImmedValue(); 472 if (Amount != 0) { 473 // We need to keep the stack aligned properly. To do this, we round the 474 // amount of space needed for the outgoing arguments up to the next 475 // alignment boundary. 476 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 477 Amount = (Amount+Align-1)/Align*Align; 478 479 MachineInstr *New = 0; 480 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { 481 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) 482 .addZImm(Amount); 483 } else { 484 assert(Old->getOpcode() == X86::ADJCALLSTACKUP); 485 // factor out the amount the callee already popped. 486 unsigned CalleeAmt = Old->getOperand(1).getImmedValue(); 487 Amount -= CalleeAmt; 488 if (Amount) { 489 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri; 490 New = BuildMI(Opc, 1, X86::ESP, 491 MachineOperand::UseAndDef).addZImm(Amount); 492 } 493 } 494 495 // Replace the pseudo instruction with a new instruction... 496 if (New) MBB.insert(I, New); 497 } 498 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { 499 // If we are performing frame pointer elimination and if the callee pops 500 // something off the stack pointer, add it back. We do this until we have 501 // more advanced stack pointer tracking ability. 502 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) { 503 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri; 504 MachineInstr *New = 505 BuildMI(Opc, 1, X86::ESP, 506 MachineOperand::UseAndDef).addZImm(CalleeAmt); 507 MBB.insert(I, New); 508 } 509 } 510 511 MBB.erase(I); 512} 513 514void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 515 unsigned i = 0; 516 MachineInstr &MI = *II; 517 MachineFunction &MF = *MI.getParent()->getParent(); 518 while (!MI.getOperand(i).isFrameIndex()) { 519 ++i; 520 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 521 } 522 523 int FrameIndex = MI.getOperand(i).getFrameIndex(); 524 525 // This must be part of a four operand memory reference. Replace the 526 // FrameIndex with base register with EBP. Add add an offset to the offset. 527 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP); 528 529 // Now add the frame object offset to the offset from EBP. 530 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 531 MI.getOperand(i+3).getImmedValue()+4; 532 533 if (!hasFP(MF)) 534 Offset += MF.getFrameInfo()->getStackSize(); 535 else 536 Offset += 4; // Skip the saved EBP 537 538 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset); 539} 540 541void 542X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ 543 if (hasFP(MF)) { 544 // Create a frame entry for the EBP register that must be saved. 545 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8); 546 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 547 "Slot for EBP register must be last in order to be found!"); 548 } 549} 550 551void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { 552 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 553 MachineBasicBlock::iterator MBBI = MBB.begin(); 554 MachineFrameInfo *MFI = MF.getFrameInfo(); 555 MachineInstr *MI; 556 557 // Get the number of bytes to allocate from the FrameInfo 558 unsigned NumBytes = MFI->getStackSize(); 559 if (hasFP(MF)) { 560 // Get the offset of the stack slot for the EBP register... which is 561 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 562 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4; 563 564 if (NumBytes) { // adjust stack pointer: ESP -= numbytes 565 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; 566 MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes); 567 MBB.insert(MBBI, MI); 568 } 569 570 // Save EBP into the appropriate stack slot... 571 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP 572 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); 573 MBB.insert(MBBI, MI); 574 575 // Update EBP with the new base value... 576 if (NumBytes == 4) // mov EBP, ESP 577 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP); 578 else // lea EBP, [ESP+StackSize] 579 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4); 580 581 MBB.insert(MBBI, MI); 582 583 } else { 584 if (MFI->hasCalls()) { 585 // When we have no frame pointer, we reserve argument space for call sites 586 // in the function immediately on entry to the current function. This 587 // eliminates the need for add/sub ESP brackets around call sites. 588 // 589 NumBytes += MFI->getMaxCallFrameSize(); 590 591 // Round the size to a multiple of the alignment (don't forget the 4 byte 592 // offset though). 593 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 594 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4; 595 } 596 597 // Update frame info to pretend that this is part of the stack... 598 MFI->setStackSize(NumBytes); 599 600 if (NumBytes) { 601 // adjust stack pointer: ESP -= numbytes 602 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; 603 MI= BuildMI(Opc, 1, X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes); 604 MBB.insert(MBBI, MI); 605 } 606 } 607} 608 609void X86RegisterInfo::emitEpilogue(MachineFunction &MF, 610 MachineBasicBlock &MBB) const { 611 const MachineFrameInfo *MFI = MF.getFrameInfo(); 612 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 613 614 switch (MBBI->getOpcode()) { 615 case X86::RET: 616 case X86::RETI: 617 case X86::TAILJMPd: 618 case X86::TAILJMPr: 619 case X86::TAILJMPm: break; // These are ok 620 default: 621 assert(0 && "Can only insert epilog into returning blocks"); 622 } 623 624 if (hasFP(MF)) { 625 // Get the offset of the stack slot for the EBP register... which is 626 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 627 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4; 628 629 // mov ESP, EBP 630 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP); 631 632 // pop EBP 633 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP); 634 } else { 635 // Get the number of bytes allocated from the FrameInfo... 636 unsigned NumBytes = MFI->getStackSize(); 637 638 if (NumBytes) { // adjust stack pointer back: ESP += numbytes 639 // If there is an ADD32ri or SUB32ri of ESP immediately before this 640 // instruction, merge the two instructions. 641 if (MBBI != MBB.begin()) { 642 MachineBasicBlock::iterator PI = prior(MBBI); 643 if ((PI->getOpcode() == X86::ADD32ri || 644 PI->getOpcode() == X86::ADD32ri8) && 645 PI->getOperand(0).getReg() == X86::ESP) { 646 NumBytes += PI->getOperand(1).getImmedValue(); 647 MBB.erase(PI); 648 } else if ((PI->getOpcode() == X86::SUB32ri || 649 PI->getOpcode() == X86::SUB32ri8) && 650 PI->getOperand(0).getReg() == X86::ESP) { 651 NumBytes -= PI->getOperand(1).getImmedValue(); 652 MBB.erase(PI); 653 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) { 654 NumBytes += PI->getOperand(1).getImmedValue(); 655 MBB.erase(PI); 656 } 657 } 658 659 if (NumBytes > 0) { 660 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri; 661 BuildMI(MBB, MBBI, Opc, 2) 662 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes); 663 } else if ((int)NumBytes < 0) { 664 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; 665 BuildMI(MBB, MBBI, Opc, 2) 666 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes); 667 } 668 } 669 } 670} 671 672#include "X86GenRegisterInfo.inc" 673 674