X86RegisterInfo.cpp revision 97de9138217d6f76f25100df272ec1a3c4d31aad 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the MRegisterInfo class.  This
11// file is responsible for the frame pointer elimination optimization on X86.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86RegisterInfo.h"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineLocation.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetInstrInfo.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/STLExtras.h"
36using namespace llvm;
37
38namespace {
39  cl::opt<bool>
40  NoFusing("disable-spill-fusing",
41           cl::desc("Disable fusing of spill code into instructions"));
42  cl::opt<bool>
43  PrintFailedFusing("print-failed-fuse-candidates",
44                    cl::desc("Print instructions that the allocator wants to"
45                             " fuse, but the X86 backend currently can't"),
46                    cl::Hidden);
47}
48
49X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
50                                 const TargetInstrInfo &tii)
51  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
52    TM(tm), TII(tii) {
53  // Cache some information.
54  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55  Is64Bit = Subtarget->is64Bit();
56  if (Is64Bit) {
57    SlotSize = 8;
58    StackPtr = X86::RSP;
59    FramePtr = X86::RBP;
60  } else {
61    SlotSize = 4;
62    StackPtr = X86::ESP;
63    FramePtr = X86::EBP;
64  }
65}
66
67void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
68                                          MachineBasicBlock::iterator MI,
69                                          unsigned SrcReg, int FrameIdx,
70                                          const TargetRegisterClass *RC) const {
71  unsigned Opc;
72  if (RC == &X86::GR64RegClass) {
73    Opc = X86::MOV64mr;
74  } else if (RC == &X86::GR32RegClass) {
75    Opc = X86::MOV32mr;
76  } else if (RC == &X86::GR16RegClass) {
77    Opc = X86::MOV16mr;
78  } else if (RC == &X86::GR8RegClass) {
79    Opc = X86::MOV8mr;
80  } else if (RC == &X86::GR32_RegClass) {
81    Opc = X86::MOV32_mr;
82  } else if (RC == &X86::GR16_RegClass) {
83    Opc = X86::MOV16_mr;
84  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
85    Opc = X86::FpST64m;
86  } else if (RC == &X86::FR32RegClass) {
87    Opc = X86::MOVSSmr;
88  } else if (RC == &X86::FR64RegClass) {
89    Opc = X86::MOVSDmr;
90  } else if (RC == &X86::VR128RegClass) {
91    Opc = X86::MOVAPSmr;
92  } else if (RC == &X86::VR64RegClass) {
93    Opc = X86::MMX_MOVQ64mr;
94  } else {
95    assert(0 && "Unknown regclass");
96    abort();
97  }
98  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
99    .addReg(SrcReg, false, false, true);
100}
101
102void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
103                                           MachineBasicBlock::iterator MI,
104                                           unsigned DestReg, int FrameIdx,
105                                           const TargetRegisterClass *RC) const{
106  unsigned Opc;
107  if (RC == &X86::GR64RegClass) {
108    Opc = X86::MOV64rm;
109  } else if (RC == &X86::GR32RegClass) {
110    Opc = X86::MOV32rm;
111  } else if (RC == &X86::GR16RegClass) {
112    Opc = X86::MOV16rm;
113  } else if (RC == &X86::GR8RegClass) {
114    Opc = X86::MOV8rm;
115  } else if (RC == &X86::GR32_RegClass) {
116    Opc = X86::MOV32_rm;
117  } else if (RC == &X86::GR16_RegClass) {
118    Opc = X86::MOV16_rm;
119  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
120    Opc = X86::FpLD64m;
121  } else if (RC == &X86::FR32RegClass) {
122    Opc = X86::MOVSSrm;
123  } else if (RC == &X86::FR64RegClass) {
124    Opc = X86::MOVSDrm;
125  } else if (RC == &X86::VR128RegClass) {
126    Opc = X86::MOVAPSrm;
127  } else if (RC == &X86::VR64RegClass) {
128    Opc = X86::MMX_MOVQ64rm;
129  } else {
130    assert(0 && "Unknown regclass");
131    abort();
132  }
133  addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
134}
135
136void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
137                                   MachineBasicBlock::iterator MI,
138                                   unsigned DestReg, unsigned SrcReg,
139                                   const TargetRegisterClass *RC) const {
140  unsigned Opc;
141  if (RC == &X86::GR64RegClass) {
142    Opc = X86::MOV64rr;
143  } else if (RC == &X86::GR32RegClass) {
144    Opc = X86::MOV32rr;
145  } else if (RC == &X86::GR16RegClass) {
146    Opc = X86::MOV16rr;
147  } else if (RC == &X86::GR8RegClass) {
148    Opc = X86::MOV8rr;
149  } else if (RC == &X86::GR32_RegClass) {
150    Opc = X86::MOV32_rr;
151  } else if (RC == &X86::GR16_RegClass) {
152    Opc = X86::MOV16_rr;
153  } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
154    Opc = X86::FpMOV;
155  } else if (RC == &X86::FR32RegClass) {
156    Opc = X86::FsMOVAPSrr;
157  } else if (RC == &X86::FR64RegClass) {
158    Opc = X86::FsMOVAPDrr;
159  } else if (RC == &X86::VR128RegClass) {
160    Opc = X86::MOVAPSrr;
161  } else if (RC == &X86::VR64RegClass) {
162    Opc = X86::MMX_MOVQ64rr;
163  } else {
164    assert(0 && "Unknown regclass");
165    abort();
166  }
167  BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
168}
169
170
171void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
172                                    MachineBasicBlock::iterator I,
173                                    unsigned DestReg,
174                                    const MachineInstr *Orig) const {
175  MachineInstr *MI = Orig->clone();
176  MI->getOperand(0).setReg(DestReg);
177  MBB.insert(I, MI);
178}
179
180static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
181                                     MachineInstr *MI,
182                                     const TargetInstrInfo &TII) {
183  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
184  // Create the base instruction with the memory operand as the first part.
185  MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
186                                              FrameIndex);
187
188  // Loop over the rest of the ri operands, converting them over.
189  for (unsigned i = 0; i != NumOps; ++i) {
190    MachineOperand &MO = MI->getOperand(i+2);
191    if (MO.isReg())
192      MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
193    else if (MO.isImm())
194      MIB = MIB.addImm(MO.getImm());
195    else if (MO.isGlobalAddress())
196      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
197    else if (MO.isJumpTableIndex())
198      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
199    else if (MO.isExternalSymbol())
200      MIB = MIB.addExternalSymbol(MO.getSymbolName());
201    else
202      assert(0 && "Unknown operand type!");
203  }
204  return MIB;
205}
206
207static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
208                              unsigned FrameIndex, MachineInstr *MI,
209                              const TargetInstrInfo &TII) {
210  MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
211
212  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
213    MachineOperand &MO = MI->getOperand(i);
214    if (i == OpNo) {
215      assert(MO.isReg() && "Expected to fold into reg operand!");
216      MIB = addFrameReference(MIB, FrameIndex);
217    } else if (MO.isReg())
218      MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
219    else if (MO.isImm())
220      MIB = MIB.addImm(MO.getImm());
221    else if (MO.isGlobalAddress())
222      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
223    else if (MO.isJumpTableIndex())
224      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
225    else if (MO.isExternalSymbol())
226      MIB = MIB.addExternalSymbol(MO.getSymbolName());
227    else
228      assert(0 && "Unknown operand for FuseInst!");
229  }
230  return MIB;
231}
232
233static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
234                                unsigned Opcode, unsigned FrameIndex,
235                                MachineInstr *MI) {
236  return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
237}
238
239
240//===----------------------------------------------------------------------===//
241// Efficient Lookup Table Support
242//===----------------------------------------------------------------------===//
243
244namespace {
245  /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
246  ///
247  struct TableEntry {
248    unsigned from;                      // Original opcode.
249    unsigned to;                        // New opcode.
250
251    // less operators used by STL search.
252    bool operator<(const TableEntry &TE) const { return from < TE.from; }
253    friend bool operator<(const TableEntry &TE, unsigned V) {
254      return TE.from < V;
255    }
256    friend bool operator<(unsigned V, const TableEntry &TE) {
257      return V < TE.from;
258    }
259  };
260}
261
262/// TableIsSorted - Return true if the table is in 'from' opcode order.
263///
264static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
265  for (unsigned i = 1; i != NumEntries; ++i)
266    if (!(Table[i-1] < Table[i])) {
267      cerr << "Entries out of order " << Table[i-1].from
268           << " " << Table[i].from << "\n";
269      return false;
270    }
271  return true;
272}
273
274/// TableLookup - Return the table entry matching the specified opcode.
275/// Otherwise return NULL.
276static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
277                                unsigned Opcode) {
278  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
279  if (I != Table+N && I->from == Opcode)
280    return I;
281  return NULL;
282}
283
284#define ARRAY_SIZE(TABLE)  \
285   (sizeof(TABLE)/sizeof(TABLE[0]))
286
287#ifdef NDEBUG
288#define ASSERT_SORTED(TABLE)
289#else
290#define ASSERT_SORTED(TABLE)                                              \
291  { static bool TABLE##Checked = false;                                   \
292    if (!TABLE##Checked) {                                                \
293       assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
294              "All lookup tables must be sorted for efficient access!");  \
295       TABLE##Checked = true;                                             \
296    }                                                                     \
297  }
298#endif
299
300
301MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
302                                                 unsigned i,
303                                                 int FrameIndex) const {
304  // Check switch flag
305  if (NoFusing) return NULL;
306
307  // Table (and size) to search
308  const TableEntry *OpcodeTablePtr = NULL;
309  unsigned OpcodeTableSize = 0;
310  bool isTwoAddrFold = false;
311  unsigned NumOps = TII.getNumOperands(MI->getOpcode());
312  bool isTwoAddr = NumOps > 1 &&
313    MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
314
315  MachineInstr *NewMI = NULL;
316  // Folding a memory location into the two-address part of a two-address
317  // instruction is different than folding it other places.  It requires
318  // replacing the *two* registers with the memory location.
319  if (isTwoAddr && NumOps >= 2 && i < 2 &&
320      MI->getOperand(0).isReg() &&
321      MI->getOperand(1).isReg() &&
322      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
323    static const TableEntry OpcodeTable[] = {
324      { X86::ADC32ri,     X86::ADC32mi },
325      { X86::ADC32ri8,    X86::ADC32mi8 },
326      { X86::ADC32rr,     X86::ADC32mr },
327      { X86::ADC64ri32,   X86::ADC64mi32 },
328      { X86::ADC64ri8,    X86::ADC64mi8 },
329      { X86::ADC64rr,     X86::ADC64mr },
330      { X86::ADD16ri,     X86::ADD16mi },
331      { X86::ADD16ri8,    X86::ADD16mi8 },
332      { X86::ADD16rr,     X86::ADD16mr },
333      { X86::ADD32ri,     X86::ADD32mi },
334      { X86::ADD32ri8,    X86::ADD32mi8 },
335      { X86::ADD32rr,     X86::ADD32mr },
336      { X86::ADD64ri32,   X86::ADD64mi32 },
337      { X86::ADD64ri8,    X86::ADD64mi8 },
338      { X86::ADD64rr,     X86::ADD64mr },
339      { X86::ADD8ri,      X86::ADD8mi },
340      { X86::ADD8rr,      X86::ADD8mr },
341      { X86::AND16ri,     X86::AND16mi },
342      { X86::AND16ri8,    X86::AND16mi8 },
343      { X86::AND16rr,     X86::AND16mr },
344      { X86::AND32ri,     X86::AND32mi },
345      { X86::AND32ri8,    X86::AND32mi8 },
346      { X86::AND32rr,     X86::AND32mr },
347      { X86::AND64ri32,   X86::AND64mi32 },
348      { X86::AND64ri8,    X86::AND64mi8 },
349      { X86::AND64rr,     X86::AND64mr },
350      { X86::AND8ri,      X86::AND8mi },
351      { X86::AND8rr,      X86::AND8mr },
352      { X86::DEC16r,      X86::DEC16m },
353      { X86::DEC32r,      X86::DEC32m },
354      { X86::DEC64_16r,   X86::DEC16m },
355      { X86::DEC64_32r,   X86::DEC32m },
356      { X86::DEC64r,      X86::DEC64m },
357      { X86::DEC8r,       X86::DEC8m },
358      { X86::INC16r,      X86::INC16m },
359      { X86::INC32r,      X86::INC32m },
360      { X86::INC64_16r,   X86::INC16m },
361      { X86::INC64_32r,   X86::INC32m },
362      { X86::INC64r,      X86::INC64m },
363      { X86::INC8r,       X86::INC8m },
364      { X86::NEG16r,      X86::NEG16m },
365      { X86::NEG32r,      X86::NEG32m },
366      { X86::NEG64r,      X86::NEG64m },
367      { X86::NEG8r,       X86::NEG8m },
368      { X86::NOT16r,      X86::NOT16m },
369      { X86::NOT32r,      X86::NOT32m },
370      { X86::NOT64r,      X86::NOT64m },
371      { X86::NOT8r,       X86::NOT8m },
372      { X86::OR16ri,      X86::OR16mi },
373      { X86::OR16ri8,     X86::OR16mi8 },
374      { X86::OR16rr,      X86::OR16mr },
375      { X86::OR32ri,      X86::OR32mi },
376      { X86::OR32ri8,     X86::OR32mi8 },
377      { X86::OR32rr,      X86::OR32mr },
378      { X86::OR64ri32,    X86::OR64mi32 },
379      { X86::OR64ri8,     X86::OR64mi8 },
380      { X86::OR64rr,      X86::OR64mr },
381      { X86::OR8ri,       X86::OR8mi },
382      { X86::OR8rr,       X86::OR8mr },
383      { X86::ROL16r1,     X86::ROL16m1 },
384      { X86::ROL16rCL,    X86::ROL16mCL },
385      { X86::ROL16ri,     X86::ROL16mi },
386      { X86::ROL32r1,     X86::ROL32m1 },
387      { X86::ROL32rCL,    X86::ROL32mCL },
388      { X86::ROL32ri,     X86::ROL32mi },
389      { X86::ROL64r1,     X86::ROL64m1 },
390      { X86::ROL64rCL,    X86::ROL64mCL },
391      { X86::ROL64ri,     X86::ROL64mi },
392      { X86::ROL8r1,      X86::ROL8m1 },
393      { X86::ROL8rCL,     X86::ROL8mCL },
394      { X86::ROL8ri,      X86::ROL8mi },
395      { X86::ROR16r1,     X86::ROR16m1 },
396      { X86::ROR16rCL,    X86::ROR16mCL },
397      { X86::ROR16ri,     X86::ROR16mi },
398      { X86::ROR32r1,     X86::ROR32m1 },
399      { X86::ROR32rCL,    X86::ROR32mCL },
400      { X86::ROR32ri,     X86::ROR32mi },
401      { X86::ROR64r1,     X86::ROR64m1 },
402      { X86::ROR64rCL,    X86::ROR64mCL },
403      { X86::ROR64ri,     X86::ROR64mi },
404      { X86::ROR8r1,      X86::ROR8m1 },
405      { X86::ROR8rCL,     X86::ROR8mCL },
406      { X86::ROR8ri,      X86::ROR8mi },
407      { X86::SAR16r1,     X86::SAR16m1 },
408      { X86::SAR16rCL,    X86::SAR16mCL },
409      { X86::SAR16ri,     X86::SAR16mi },
410      { X86::SAR32r1,     X86::SAR32m1 },
411      { X86::SAR32rCL,    X86::SAR32mCL },
412      { X86::SAR32ri,     X86::SAR32mi },
413      { X86::SAR64r1,     X86::SAR64m1 },
414      { X86::SAR64rCL,    X86::SAR64mCL },
415      { X86::SAR64ri,     X86::SAR64mi },
416      { X86::SAR8r1,      X86::SAR8m1 },
417      { X86::SAR8rCL,     X86::SAR8mCL },
418      { X86::SAR8ri,      X86::SAR8mi },
419      { X86::SBB32ri,     X86::SBB32mi },
420      { X86::SBB32ri8,    X86::SBB32mi8 },
421      { X86::SBB32rr,     X86::SBB32mr },
422      { X86::SBB64ri32,   X86::SBB64mi32 },
423      { X86::SBB64ri8,    X86::SBB64mi8 },
424      { X86::SBB64rr,     X86::SBB64mr },
425      { X86::SHL16r1,     X86::SHL16m1 },
426      { X86::SHL16rCL,    X86::SHL16mCL },
427      { X86::SHL16ri,     X86::SHL16mi },
428      { X86::SHL32r1,     X86::SHL32m1 },
429      { X86::SHL32rCL,    X86::SHL32mCL },
430      { X86::SHL32ri,     X86::SHL32mi },
431      { X86::SHL64r1,     X86::SHL64m1 },
432      { X86::SHL64rCL,    X86::SHL64mCL },
433      { X86::SHL64ri,     X86::SHL64mi },
434      { X86::SHL8r1,      X86::SHL8m1 },
435      { X86::SHL8rCL,     X86::SHL8mCL },
436      { X86::SHL8ri,      X86::SHL8mi },
437      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
438      { X86::SHLD16rri8,  X86::SHLD16mri8 },
439      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
440      { X86::SHLD32rri8,  X86::SHLD32mri8 },
441      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
442      { X86::SHLD64rri8,  X86::SHLD64mri8 },
443      { X86::SHR16r1,     X86::SHR16m1 },
444      { X86::SHR16rCL,    X86::SHR16mCL },
445      { X86::SHR16ri,     X86::SHR16mi },
446      { X86::SHR32r1,     X86::SHR32m1 },
447      { X86::SHR32rCL,    X86::SHR32mCL },
448      { X86::SHR32ri,     X86::SHR32mi },
449      { X86::SHR64r1,     X86::SHR64m1 },
450      { X86::SHR64rCL,    X86::SHR64mCL },
451      { X86::SHR64ri,     X86::SHR64mi },
452      { X86::SHR8r1,      X86::SHR8m1 },
453      { X86::SHR8rCL,     X86::SHR8mCL },
454      { X86::SHR8ri,      X86::SHR8mi },
455      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
456      { X86::SHRD16rri8,  X86::SHRD16mri8 },
457      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
458      { X86::SHRD32rri8,  X86::SHRD32mri8 },
459      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
460      { X86::SHRD64rri8,  X86::SHRD64mri8 },
461      { X86::SUB16ri,     X86::SUB16mi },
462      { X86::SUB16ri8,    X86::SUB16mi8 },
463      { X86::SUB16rr,     X86::SUB16mr },
464      { X86::SUB32ri,     X86::SUB32mi },
465      { X86::SUB32ri8,    X86::SUB32mi8 },
466      { X86::SUB32rr,     X86::SUB32mr },
467      { X86::SUB64ri32,   X86::SUB64mi32 },
468      { X86::SUB64ri8,    X86::SUB64mi8 },
469      { X86::SUB64rr,     X86::SUB64mr },
470      { X86::SUB8ri,      X86::SUB8mi },
471      { X86::SUB8rr,      X86::SUB8mr },
472      { X86::XOR16ri,     X86::XOR16mi },
473      { X86::XOR16ri8,    X86::XOR16mi8 },
474      { X86::XOR16rr,     X86::XOR16mr },
475      { X86::XOR32ri,     X86::XOR32mi },
476      { X86::XOR32ri8,    X86::XOR32mi8 },
477      { X86::XOR32rr,     X86::XOR32mr },
478      { X86::XOR64ri32,   X86::XOR64mi32 },
479      { X86::XOR64ri8,    X86::XOR64mi8 },
480      { X86::XOR64rr,     X86::XOR64mr },
481      { X86::XOR8ri,      X86::XOR8mi },
482      { X86::XOR8rr,      X86::XOR8mr }
483    };
484    ASSERT_SORTED(OpcodeTable);
485    OpcodeTablePtr = OpcodeTable;
486    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
487    isTwoAddrFold = true;
488  } else if (i == 0) { // If operand 0
489    if (MI->getOpcode() == X86::MOV16r0)
490      NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
491    else if (MI->getOpcode() == X86::MOV32r0)
492      NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
493    else if (MI->getOpcode() == X86::MOV64r0)
494      NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
495    else if (MI->getOpcode() == X86::MOV8r0)
496      NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
497    if (NewMI) {
498      NewMI->copyKillDeadInfo(MI);
499      return NewMI;
500    }
501
502    static const TableEntry OpcodeTable[] = {
503      { X86::CMP16ri,     X86::CMP16mi },
504      { X86::CMP16ri8,    X86::CMP16mi8 },
505      { X86::CMP32ri,     X86::CMP32mi },
506      { X86::CMP32ri8,    X86::CMP32mi8 },
507      { X86::CMP8ri,      X86::CMP8mi },
508      { X86::DIV16r,      X86::DIV16m },
509      { X86::DIV32r,      X86::DIV32m },
510      { X86::DIV64r,      X86::DIV64m },
511      { X86::DIV8r,       X86::DIV8m },
512      { X86::FsMOVAPDrr,  X86::MOVSDmr },
513      { X86::FsMOVAPSrr,  X86::MOVSSmr },
514      { X86::IDIV16r,     X86::IDIV16m },
515      { X86::IDIV32r,     X86::IDIV32m },
516      { X86::IDIV64r,     X86::IDIV64m },
517      { X86::IDIV8r,      X86::IDIV8m },
518      { X86::IMUL16r,     X86::IMUL16m },
519      { X86::IMUL32r,     X86::IMUL32m },
520      { X86::IMUL64r,     X86::IMUL64m },
521      { X86::IMUL8r,      X86::IMUL8m },
522      { X86::MOV16ri,     X86::MOV16mi },
523      { X86::MOV16rr,     X86::MOV16mr },
524      { X86::MOV32ri,     X86::MOV32mi },
525      { X86::MOV32rr,     X86::MOV32mr },
526      { X86::MOV64ri32,   X86::MOV64mi32 },
527      { X86::MOV64rr,     X86::MOV64mr },
528      { X86::MOV8ri,      X86::MOV8mi },
529      { X86::MOV8rr,      X86::MOV8mr },
530      { X86::MOVAPDrr,    X86::MOVAPDmr },
531      { X86::MOVAPSrr,    X86::MOVAPSmr },
532      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
533      { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
534      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
535      { X86::MOVSDrr,     X86::MOVSDmr },
536      { X86::MOVSDto64rr, X86::MOVSDto64mr },
537      { X86::MOVSS2DIrr,  X86::MOVSS2DImr },
538      { X86::MOVSSrr,     X86::MOVSSmr },
539      { X86::MOVUPDrr,    X86::MOVUPDmr },
540      { X86::MOVUPSrr,    X86::MOVUPSmr },
541      { X86::MUL16r,      X86::MUL16m },
542      { X86::MUL32r,      X86::MUL32m },
543      { X86::MUL64r,      X86::MUL64m },
544      { X86::MUL8r,       X86::MUL8m },
545      { X86::SETAEr,      X86::SETAEm },
546      { X86::SETAr,       X86::SETAm },
547      { X86::SETBEr,      X86::SETBEm },
548      { X86::SETBr,       X86::SETBm },
549      { X86::SETEr,       X86::SETEm },
550      { X86::SETGEr,      X86::SETGEm },
551      { X86::SETGr,       X86::SETGm },
552      { X86::SETLEr,      X86::SETLEm },
553      { X86::SETLr,       X86::SETLm },
554      { X86::SETNEr,      X86::SETNEm },
555      { X86::SETNPr,      X86::SETNPm },
556      { X86::SETNSr,      X86::SETNSm },
557      { X86::SETPr,       X86::SETPm },
558      { X86::SETSr,       X86::SETSm },
559      { X86::TEST16ri,    X86::TEST16mi },
560      { X86::TEST32ri,    X86::TEST32mi },
561      { X86::TEST64ri32,  X86::TEST64mi32 },
562      { X86::TEST8ri,     X86::TEST8mi },
563      { X86::XCHG16rr,    X86::XCHG16mr },
564      { X86::XCHG32rr,    X86::XCHG32mr },
565      { X86::XCHG64rr,    X86::XCHG64mr },
566      { X86::XCHG8rr,     X86::XCHG8mr }
567    };
568    ASSERT_SORTED(OpcodeTable);
569    OpcodeTablePtr = OpcodeTable;
570    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
571  } else if (i == 1) {
572    static const TableEntry OpcodeTable[] = {
573      { X86::CMP16rr,         X86::CMP16rm },
574      { X86::CMP32rr,         X86::CMP32rm },
575      { X86::CMP64ri32,       X86::CMP64mi32 },
576      { X86::CMP64ri8,        X86::CMP64mi8 },
577      { X86::CMP64rr,         X86::CMP64rm },
578      { X86::CMP8rr,          X86::CMP8rm },
579      { X86::CMPPDrri,        X86::CMPPDrmi },
580      { X86::CMPPSrri,        X86::CMPPSrmi },
581      { X86::CMPSDrr,         X86::CMPSDrm },
582      { X86::CMPSSrr,         X86::CMPSSrm },
583      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
584      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
585      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
586      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
587      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
588      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
589      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
590      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
591      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
592      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
593      { X86::FsMOVAPDrr,      X86::MOVSDrm },
594      { X86::FsMOVAPSrr,      X86::MOVSSrm },
595      { X86::IMUL16rri,       X86::IMUL16rmi },
596      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
597      { X86::IMUL32rri,       X86::IMUL32rmi },
598      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
599      { X86::IMUL64rr,        X86::IMUL64rm },
600      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
601      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
602      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
603      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
604      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
605      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
606      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
607      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
608      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
609      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
610      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
611      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
612      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
613      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
614      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
615      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
616      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
617      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
618      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
619      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
620      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
621      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
622      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
623      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
624      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
625      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
626      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
627      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
628      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
629      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
630      { X86::MOV16rr,         X86::MOV16rm },
631      { X86::MOV32rr,         X86::MOV32rm },
632      { X86::MOV64rr,         X86::MOV64rm },
633      { X86::MOV64toPQIrr,    X86::MOV64toPQIrm },
634      { X86::MOV64toSDrr,     X86::MOV64toSDrm },
635      { X86::MOV8rr,          X86::MOV8rm },
636      { X86::MOVAPDrr,        X86::MOVAPDrm },
637      { X86::MOVAPSrr,        X86::MOVAPSrm },
638      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
639      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
640      { X86::MOVDI2SSrr,      X86::MOVDI2SSrm },
641      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
642      { X86::MOVSDrr,         X86::MOVSDrm },
643      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
644      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
645      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
646      { X86::MOVSSrr,         X86::MOVSSrm },
647      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
648      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
649      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
650      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
651      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
652      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
653      { X86::MOVUPDrr,        X86::MOVUPDrm },
654      { X86::MOVUPSrr,        X86::MOVUPSrm },
655      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
656      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
657      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
658      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
659      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
660      { X86::PSHUFDri,        X86::PSHUFDmi },
661      { X86::PSHUFHWri,       X86::PSHUFHWmi },
662      { X86::PSHUFLWri,       X86::PSHUFLWmi },
663      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
664      { X86::TEST16rr,        X86::TEST16rm },
665      { X86::TEST32rr,        X86::TEST32rm },
666      { X86::TEST64rr,        X86::TEST64rm },
667      { X86::TEST8rr,         X86::TEST8rm },
668      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
669      { X86::UCOMISDrr,       X86::UCOMISDrm },
670      { X86::UCOMISSrr,       X86::UCOMISSrm },
671      { X86::XCHG16rr,        X86::XCHG16rm },
672      { X86::XCHG32rr,        X86::XCHG32rm },
673      { X86::XCHG64rr,        X86::XCHG64rm },
674      { X86::XCHG8rr,         X86::XCHG8rm }
675    };
676    ASSERT_SORTED(OpcodeTable);
677    OpcodeTablePtr = OpcodeTable;
678    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
679  } else if (i == 2) {
680    static const TableEntry OpcodeTable[] = {
681      { X86::ADC32rr,         X86::ADC32rm },
682      { X86::ADC64rr,         X86::ADC64rm },
683      { X86::ADD16rr,         X86::ADD16rm },
684      { X86::ADD32rr,         X86::ADD32rm },
685      { X86::ADD64rr,         X86::ADD64rm },
686      { X86::ADD8rr,          X86::ADD8rm },
687      { X86::ADDPDrr,         X86::ADDPDrm },
688      { X86::ADDPSrr,         X86::ADDPSrm },
689      { X86::ADDSDrr,         X86::ADDSDrm },
690      { X86::ADDSSrr,         X86::ADDSSrm },
691      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
692      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
693      { X86::AND16rr,         X86::AND16rm },
694      { X86::AND32rr,         X86::AND32rm },
695      { X86::AND64rr,         X86::AND64rm },
696      { X86::AND8rr,          X86::AND8rm },
697      { X86::ANDNPDrr,        X86::ANDNPDrm },
698      { X86::ANDNPSrr,        X86::ANDNPSrm },
699      { X86::ANDPDrr,         X86::ANDPDrm },
700      { X86::ANDPSrr,         X86::ANDPSrm },
701      { X86::CMOVA16rr,       X86::CMOVA16rm },
702      { X86::CMOVA32rr,       X86::CMOVA32rm },
703      { X86::CMOVA64rr,       X86::CMOVA64rm },
704      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
705      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
706      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
707      { X86::CMOVB16rr,       X86::CMOVB16rm },
708      { X86::CMOVB32rr,       X86::CMOVB32rm },
709      { X86::CMOVB64rr,       X86::CMOVB64rm },
710      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
711      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
712      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
713      { X86::CMOVE16rr,       X86::CMOVE16rm },
714      { X86::CMOVE32rr,       X86::CMOVE32rm },
715      { X86::CMOVE64rr,       X86::CMOVE64rm },
716      { X86::CMOVG16rr,       X86::CMOVG16rm },
717      { X86::CMOVG32rr,       X86::CMOVG32rm },
718      { X86::CMOVG64rr,       X86::CMOVG64rm },
719      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
720      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
721      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
722      { X86::CMOVL16rr,       X86::CMOVL16rm },
723      { X86::CMOVL32rr,       X86::CMOVL32rm },
724      { X86::CMOVL64rr,       X86::CMOVL64rm },
725      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
726      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
727      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
728      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
729      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
730      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
731      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
732      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
733      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
734      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
735      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
736      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
737      { X86::CMOVP16rr,       X86::CMOVP16rm },
738      { X86::CMOVP32rr,       X86::CMOVP32rm },
739      { X86::CMOVP64rr,       X86::CMOVP64rm },
740      { X86::CMOVS16rr,       X86::CMOVS16rm },
741      { X86::CMOVS32rr,       X86::CMOVS32rm },
742      { X86::CMOVS64rr,       X86::CMOVS64rm },
743      { X86::DIVPDrr,         X86::DIVPDrm },
744      { X86::DIVPSrr,         X86::DIVPSrm },
745      { X86::DIVSDrr,         X86::DIVSDrm },
746      { X86::DIVSSrr,         X86::DIVSSrm },
747      { X86::HADDPDrr,        X86::HADDPDrm },
748      { X86::HADDPSrr,        X86::HADDPSrm },
749      { X86::HSUBPDrr,        X86::HSUBPDrm },
750      { X86::HSUBPSrr,        X86::HSUBPSrm },
751      { X86::IMUL16rr,        X86::IMUL16rm },
752      { X86::IMUL32rr,        X86::IMUL32rm },
753      { X86::MAXPDrr,         X86::MAXPDrm },
754      { X86::MAXPSrr,         X86::MAXPSrm },
755      { X86::MINPDrr,         X86::MINPDrm },
756      { X86::MINPSrr,         X86::MINPSrm },
757      { X86::MULPDrr,         X86::MULPDrm },
758      { X86::MULPSrr,         X86::MULPSrm },
759      { X86::MULSDrr,         X86::MULSDrm },
760      { X86::MULSSrr,         X86::MULSSrm },
761      { X86::OR16rr,          X86::OR16rm },
762      { X86::OR32rr,          X86::OR32rm },
763      { X86::OR64rr,          X86::OR64rm },
764      { X86::OR8rr,           X86::OR8rm },
765      { X86::ORPDrr,          X86::ORPDrm },
766      { X86::ORPSrr,          X86::ORPSrm },
767      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
768      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
769      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
770      { X86::PADDBrr,         X86::PADDBrm },
771      { X86::PADDDrr,         X86::PADDDrm },
772      { X86::PADDQrr,         X86::PADDQrm },
773      { X86::PADDSBrr,        X86::PADDSBrm },
774      { X86::PADDSWrr,        X86::PADDSWrm },
775      { X86::PADDWrr,         X86::PADDWrm },
776      { X86::PANDNrr,         X86::PANDNrm },
777      { X86::PANDrr,          X86::PANDrm },
778      { X86::PAVGBrr,         X86::PAVGBrm },
779      { X86::PAVGWrr,         X86::PAVGWrm },
780      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
781      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
782      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
783      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
784      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
785      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
786      { X86::PINSRWrri,       X86::PINSRWrmi },
787      { X86::PMADDWDrr,       X86::PMADDWDrm },
788      { X86::PMAXSWrr,        X86::PMAXSWrm },
789      { X86::PMAXUBrr,        X86::PMAXUBrm },
790      { X86::PMINSWrr,        X86::PMINSWrm },
791      { X86::PMINUBrr,        X86::PMINUBrm },
792      { X86::PMULHUWrr,       X86::PMULHUWrm },
793      { X86::PMULHWrr,        X86::PMULHWrm },
794      { X86::PMULLWrr,        X86::PMULLWrm },
795      { X86::PMULUDQrr,       X86::PMULUDQrm },
796      { X86::PORrr,           X86::PORrm },
797      { X86::PSADBWrr,        X86::PSADBWrm },
798      { X86::PSLLDrr,         X86::PSLLDrm },
799      { X86::PSLLQrr,         X86::PSLLQrm },
800      { X86::PSLLWrr,         X86::PSLLWrm },
801      { X86::PSRADrr,         X86::PSRADrm },
802      { X86::PSRAWrr,         X86::PSRAWrm },
803      { X86::PSRLDrr,         X86::PSRLDrm },
804      { X86::PSRLQrr,         X86::PSRLQrm },
805      { X86::PSRLWrr,         X86::PSRLWrm },
806      { X86::PSUBBrr,         X86::PSUBBrm },
807      { X86::PSUBDrr,         X86::PSUBDrm },
808      { X86::PSUBSBrr,        X86::PSUBSBrm },
809      { X86::PSUBSWrr,        X86::PSUBSWrm },
810      { X86::PSUBWrr,         X86::PSUBWrm },
811      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
812      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
813      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
814      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
815      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
816      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
817      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
818      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
819      { X86::PXORrr,          X86::PXORrm },
820      { X86::RCPPSr,          X86::RCPPSm },
821      { X86::RSQRTPSr,        X86::RSQRTPSm },
822      { X86::SBB32rr,         X86::SBB32rm },
823      { X86::SBB64rr,         X86::SBB64rm },
824      { X86::SHUFPDrri,       X86::SHUFPDrmi },
825      { X86::SHUFPSrri,       X86::SHUFPSrmi },
826      { X86::SQRTPDr,         X86::SQRTPDm },
827      { X86::SQRTPSr,         X86::SQRTPSm },
828      { X86::SQRTSDr,         X86::SQRTSDm },
829      { X86::SQRTSSr,         X86::SQRTSSm },
830      { X86::SUB16rr,         X86::SUB16rm },
831      { X86::SUB32rr,         X86::SUB32rm },
832      { X86::SUB64rr,         X86::SUB64rm },
833      { X86::SUB8rr,          X86::SUB8rm },
834      { X86::SUBPDrr,         X86::SUBPDrm },
835      { X86::SUBPSrr,         X86::SUBPSrm },
836      { X86::SUBSDrr,         X86::SUBSDrm },
837      { X86::SUBSSrr,         X86::SUBSSrm },
838      // FIXME: TEST*rr -> swapped operand of TEST*mr.
839      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
840      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
841      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
842      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
843      { X86::XOR16rr,         X86::XOR16rm },
844      { X86::XOR32rr,         X86::XOR32rm },
845      { X86::XOR64rr,         X86::XOR64rm },
846      { X86::XOR8rr,          X86::XOR8rm },
847      { X86::XORPDrr,         X86::XORPDrm },
848      { X86::XORPSrr,         X86::XORPSrm }
849    };
850    ASSERT_SORTED(OpcodeTable);
851    OpcodeTablePtr = OpcodeTable;
852    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
853  }
854
855  // If table selected...
856  if (OpcodeTablePtr) {
857    // Find the Opcode to fuse
858    unsigned fromOpcode = MI->getOpcode();
859    // Lookup fromOpcode in table
860    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
861                                              fromOpcode)) {
862      if (isTwoAddrFold)
863        NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
864      else
865        NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
866      NewMI->copyKillDeadInfo(MI);
867      return NewMI;
868    }
869  }
870
871  // No fusion
872  if (PrintFailedFusing)
873    cerr << "We failed to fuse ("
874         << ((i == 1) ? "r" : "s") << "): " << *MI;
875  return NULL;
876}
877
878
879const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
880  static const unsigned CalleeSavedRegs32Bit[] = {
881    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
882  };
883  static const unsigned CalleeSavedRegs64Bit[] = {
884    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
885  };
886
887  return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
888}
889
890const TargetRegisterClass* const*
891X86RegisterInfo::getCalleeSavedRegClasses() const {
892  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
893    &X86::GR32RegClass, &X86::GR32RegClass,
894    &X86::GR32RegClass, &X86::GR32RegClass,  0
895  };
896  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
897    &X86::GR64RegClass, &X86::GR64RegClass,
898    &X86::GR64RegClass, &X86::GR64RegClass,
899    &X86::GR64RegClass, &X86::GR64RegClass, 0
900  };
901
902  return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
903}
904
905BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
906  BitVector Reserved(getNumRegs());
907  Reserved.set(X86::RSP);
908  Reserved.set(X86::ESP);
909  Reserved.set(X86::SP);
910  Reserved.set(X86::SPL);
911  if (hasFP(MF)) {
912    Reserved.set(X86::RBP);
913    Reserved.set(X86::EBP);
914    Reserved.set(X86::BP);
915    Reserved.set(X86::BPL);
916  }
917  return Reserved;
918}
919
920//===----------------------------------------------------------------------===//
921// Stack Frame Processing methods
922//===----------------------------------------------------------------------===//
923
924// hasFP - Return true if the specified function should have a dedicated frame
925// pointer register.  This is true if the function has variable sized allocas or
926// if frame pointer elimination is disabled.
927//
928bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
929  return (NoFramePointerElim ||
930          MF.getFrameInfo()->hasVarSizedObjects() ||
931          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer());
932}
933
934void X86RegisterInfo::
935eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
936                              MachineBasicBlock::iterator I) const {
937  if (hasFP(MF)) {
938    // If we have a frame pointer, turn the adjcallstackup instruction into a
939    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
940    // <amt>'
941    MachineInstr *Old = I;
942    uint64_t Amount = Old->getOperand(0).getImm();
943    if (Amount != 0) {
944      // We need to keep the stack aligned properly.  To do this, we round the
945      // amount of space needed for the outgoing arguments up to the next
946      // alignment boundary.
947      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
948      Amount = (Amount+Align-1)/Align*Align;
949
950      MachineInstr *New = 0;
951      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
952        New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
953          .addReg(StackPtr).addImm(Amount);
954      } else {
955        assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
956        // factor out the amount the callee already popped.
957        uint64_t CalleeAmt = Old->getOperand(1).getImm();
958        Amount -= CalleeAmt;
959        if (Amount) {
960          unsigned Opc = (Amount < 128) ?
961            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
962            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
963          New = BuildMI(TII.get(Opc),  StackPtr)
964                        .addReg(StackPtr).addImm(Amount);
965        }
966      }
967
968      // Replace the pseudo instruction with a new instruction...
969      if (New) MBB.insert(I, New);
970    }
971  } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
972    // If we are performing frame pointer elimination and if the callee pops
973    // something off the stack pointer, add it back.  We do this until we have
974    // more advanced stack pointer tracking ability.
975    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
976      unsigned Opc = (CalleeAmt < 128) ?
977        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
978        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
979      MachineInstr *New =
980        BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
981      MBB.insert(I, New);
982    }
983  }
984
985  MBB.erase(I);
986}
987
988void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
989                                          int SPAdj, RegScavenger *RS) const{
990  assert(SPAdj == 0 && "Unexpected");
991
992  unsigned i = 0;
993  MachineInstr &MI = *II;
994  MachineFunction &MF = *MI.getParent()->getParent();
995  while (!MI.getOperand(i).isFrameIndex()) {
996    ++i;
997    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
998  }
999
1000  int FrameIndex = MI.getOperand(i).getFrameIndex();
1001  // This must be part of a four operand memory reference.  Replace the
1002  // FrameIndex with base register with EBP.  Add an offset to the offset.
1003  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
1004
1005  // Now add the frame object offset to the offset from EBP.
1006  int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1007                   MI.getOperand(i+3).getImm()+SlotSize;
1008
1009  if (!hasFP(MF))
1010    Offset += MF.getFrameInfo()->getStackSize();
1011  else
1012    Offset += SlotSize;  // Skip the saved EBP
1013
1014  MI.getOperand(i+3).ChangeToImmediate(Offset);
1015}
1016
1017void
1018X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1019  if (hasFP(MF)) {
1020    // Create a frame entry for the EBP register that must be saved.
1021    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1022                                                        (int)SlotSize * -2);
1023    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1024           "Slot for EBP register must be last in order to be found!");
1025  }
1026}
1027
1028/// emitSPUpdate - Emit a series of instructions to increment / decrement the
1029/// stack pointer by a constant value.
1030static
1031void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1032                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
1033                  const TargetInstrInfo &TII) {
1034  bool isSub = NumBytes < 0;
1035  uint64_t Offset = isSub ? -NumBytes : NumBytes;
1036  unsigned Opc = isSub
1037    ? ((Offset < 128) ?
1038       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1039       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
1040    : ((Offset < 128) ?
1041       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1042       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
1043  uint64_t Chunk = (1LL << 31) - 1;
1044
1045  while (Offset) {
1046    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
1047    BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
1048    Offset -= ThisVal;
1049  }
1050}
1051
1052void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1053  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
1054  MachineBasicBlock::iterator MBBI = MBB.begin();
1055  MachineFrameInfo *MFI = MF.getFrameInfo();
1056  unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1057  const Function* Fn = MF.getFunction();
1058  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1059  MachineInstr *MI;
1060  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1061
1062  // Prepare for frame info.
1063  unsigned FrameLabelId = 0;
1064
1065  // Get the number of bytes to allocate from the FrameInfo
1066  uint64_t NumBytes = MFI->getStackSize();
1067
1068  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
1069    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1070      // Check, whether EAX is livein for this function
1071      bool isEAXAlive = false;
1072      for (MachineFunction::livein_iterator II = MF.livein_begin(),
1073             EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1074        unsigned Reg = II->first;
1075        isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1076                      Reg == X86::AH || Reg == X86::AL);
1077      }
1078
1079      // Function prologue calls _alloca to probe the stack when allocating
1080      // more than 4k bytes in one go. Touching the stack at 4K increments is
1081      // necessary to ensure that the guard pages used by the OS virtual memory
1082      // manager are allocated in correct sequence.
1083      if (!isEAXAlive) {
1084        MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1085        MBB.insert(MBBI, MI);
1086        MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1087        MBB.insert(MBBI, MI);
1088      } else {
1089        // Save EAX
1090        MI = BuildMI(TII.get(X86::PUSH32r), X86::EAX);
1091        MBB.insert(MBBI, MI);
1092        // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1093        // allocated bytes for EAX.
1094        MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
1095        MBB.insert(MBBI, MI);
1096        MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1097        MBB.insert(MBBI, MI);
1098        // Restore EAX
1099        MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm), X86::EAX),
1100                          StackPtr, NumBytes-4);
1101        MBB.insert(MBBI, MI);
1102      }
1103    } else {
1104      emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1105    }
1106  }
1107
1108  if (MMI && MMI->needsFrameInfo()) {
1109    // Mark effective beginning of when frame pointer becomes valid.
1110    FrameLabelId = MMI->NextLabelID();
1111    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1112  }
1113
1114  if (hasFP(MF)) {
1115    // Get the offset of the stack slot for the EBP register... which is
1116    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1117    int64_t EBPOffset =
1118      MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1119    // Update the frame offset adjustment.
1120    MFI->setOffsetAdjustment(SlotSize-NumBytes);
1121
1122    // Save EBP into the appropriate stack slot...
1123    // mov [ESP-<offset>], EBP
1124    MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
1125                      StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1126    MBB.insert(MBBI, MI);
1127
1128    // Update EBP with the new base value...
1129    if (NumBytes == SlotSize)    // mov EBP, ESP
1130      MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
1131        addReg(StackPtr);
1132    else                  // lea EBP, [ESP+StackSize]
1133      MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1134                                FramePtr), StackPtr, NumBytes-SlotSize);
1135
1136    MBB.insert(MBBI, MI);
1137  }
1138
1139  if (MMI && MMI->needsFrameInfo()) {
1140    std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1141
1142    if (NumBytes) {
1143      // Show update of SP.
1144      MachineLocation SPDst(MachineLocation::VirtualFP);
1145      MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
1146      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1147    } else {
1148      MachineLocation SP(StackPtr);
1149      Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1150    }
1151
1152    // Add callee saved registers to move list.
1153    const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1154    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1155      int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1156      unsigned Reg = CSI[I].getReg();
1157      MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1158      MachineLocation CSSrc(Reg);
1159      Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1160    }
1161
1162    // Mark effective beginning of when frame pointer is ready.
1163    unsigned ReadyLabelId = MMI->NextLabelID();
1164    BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1165
1166    MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1167    MachineLocation FPSrc(MachineLocation::VirtualFP);
1168    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1169  }
1170
1171  // If it's main() on Cygwin\Mingw32 we should align stack as well
1172  if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1173      Subtarget->isTargetCygMing()) {
1174    MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
1175                .addReg(X86::ESP).addImm(-Align);
1176    MBB.insert(MBBI, MI);
1177
1178    // Probe the stack
1179    MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1180    MBB.insert(MBBI, MI);
1181    MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1182    MBB.insert(MBBI, MI);
1183  }
1184}
1185
1186void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1187                                   MachineBasicBlock &MBB) const {
1188  const MachineFrameInfo *MFI = MF.getFrameInfo();
1189  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1190
1191  switch (MBBI->getOpcode()) {
1192  case X86::RET:
1193  case X86::RETI:
1194  case X86::TAILJMPd:
1195  case X86::TAILJMPr:
1196  case X86::TAILJMPm: break;  // These are ok
1197  default:
1198    assert(0 && "Can only insert epilog into returning blocks");
1199  }
1200
1201  if (hasFP(MF)) {
1202    // mov ESP, EBP
1203    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1204      addReg(FramePtr);
1205
1206    // pop EBP
1207    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1208  } else {
1209    // Get the number of bytes allocated from the FrameInfo.
1210    uint64_t NumBytes = MFI->getStackSize();
1211
1212    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
1213      // If there is an ADD32ri or SUB32ri of ESP immediately before this
1214      // instruction, merge the two instructions.
1215      if (MBBI != MBB.begin()) {
1216        MachineBasicBlock::iterator PI = prior(MBBI);
1217        unsigned Opc = PI->getOpcode();
1218        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1219             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1220            PI->getOperand(0).getReg() == StackPtr) {
1221          NumBytes += PI->getOperand(2).getImm();
1222          MBB.erase(PI);
1223        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1224                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1225                   PI->getOperand(0).getReg() == StackPtr) {
1226          NumBytes -= PI->getOperand(2).getImm();
1227          MBB.erase(PI);
1228        }
1229      }
1230
1231      if (NumBytes)
1232        emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1233    }
1234  }
1235}
1236
1237unsigned X86RegisterInfo::getRARegister() const {
1238  return X86::ST0;  // use a non-register register
1239}
1240
1241unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1242  return hasFP(MF) ? FramePtr : StackPtr;
1243}
1244
1245void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1246                                                                         const {
1247  // Initial state of the frame pointer is esp.
1248  MachineLocation Dst(MachineLocation::VirtualFP);
1249  MachineLocation Src(StackPtr, 0);
1250  Moves.push_back(MachineMove(0, Dst, Src));
1251}
1252
1253unsigned X86RegisterInfo::getEHExceptionRegister() const {
1254  assert(0 && "What is the exception register");
1255  return 0;
1256}
1257
1258unsigned X86RegisterInfo::getEHHandlerRegister() const {
1259  assert(0 && "What is the exception handler register");
1260  return 0;
1261}
1262
1263namespace llvm {
1264unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1265  switch (VT) {
1266  default: return Reg;
1267  case MVT::i8:
1268    if (High) {
1269      switch (Reg) {
1270      default: return 0;
1271      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1272        return X86::AH;
1273      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1274        return X86::DH;
1275      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1276        return X86::CH;
1277      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1278        return X86::BH;
1279      }
1280    } else {
1281      switch (Reg) {
1282      default: return 0;
1283      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1284        return X86::AL;
1285      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1286        return X86::DL;
1287      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1288        return X86::CL;
1289      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1290        return X86::BL;
1291      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1292        return X86::SIL;
1293      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1294        return X86::DIL;
1295      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1296        return X86::BPL;
1297      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1298        return X86::SPL;
1299      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1300        return X86::R8B;
1301      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1302        return X86::R9B;
1303      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1304        return X86::R10B;
1305      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1306        return X86::R11B;
1307      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1308        return X86::R12B;
1309      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1310        return X86::R13B;
1311      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1312        return X86::R14B;
1313      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1314        return X86::R15B;
1315      }
1316    }
1317  case MVT::i16:
1318    switch (Reg) {
1319    default: return Reg;
1320    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1321      return X86::AX;
1322    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1323      return X86::DX;
1324    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1325      return X86::CX;
1326    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1327      return X86::BX;
1328    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1329      return X86::SI;
1330    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1331      return X86::DI;
1332    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1333      return X86::BP;
1334    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1335      return X86::SP;
1336    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1337      return X86::R8W;
1338    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1339      return X86::R9W;
1340    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1341      return X86::R10W;
1342    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1343      return X86::R11W;
1344    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1345      return X86::R12W;
1346    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1347      return X86::R13W;
1348    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1349      return X86::R14W;
1350    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1351      return X86::R15W;
1352    }
1353  case MVT::i32:
1354    switch (Reg) {
1355    default: return Reg;
1356    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1357      return X86::EAX;
1358    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1359      return X86::EDX;
1360    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1361      return X86::ECX;
1362    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1363      return X86::EBX;
1364    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1365      return X86::ESI;
1366    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1367      return X86::EDI;
1368    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1369      return X86::EBP;
1370    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1371      return X86::ESP;
1372    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1373      return X86::R8D;
1374    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1375      return X86::R9D;
1376    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1377      return X86::R10D;
1378    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1379      return X86::R11D;
1380    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1381      return X86::R12D;
1382    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1383      return X86::R13D;
1384    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1385      return X86::R14D;
1386    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1387      return X86::R15D;
1388    }
1389  case MVT::i64:
1390    switch (Reg) {
1391    default: return Reg;
1392    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1393      return X86::RAX;
1394    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1395      return X86::RDX;
1396    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1397      return X86::RCX;
1398    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1399      return X86::RBX;
1400    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1401      return X86::RSI;
1402    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1403      return X86::RDI;
1404    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1405      return X86::RBP;
1406    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1407      return X86::RSP;
1408    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1409      return X86::R8;
1410    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1411      return X86::R9;
1412    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1413      return X86::R10;
1414    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1415      return X86::R11;
1416    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1417      return X86::R12;
1418    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1419      return X86::R13;
1420    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1421      return X86::R14;
1422    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1423      return X86::R15;
1424    }
1425  }
1426
1427  return Reg;
1428}
1429}
1430
1431#include "X86GenRegisterInfo.inc"
1432
1433