X86RegisterInfo.cpp revision 9dea41d9e1c9e288630db503668468560aa4286e
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the MRegisterInfo class. This 11// file is responsible for the frame pointer elimination optimization on X86. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86RegisterInfo.h" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/Type.h" 24#include "llvm/CodeGen/ValueTypes.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineLocation.h" 29#include "llvm/Target/TargetFrameInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/ADT/STLExtras.h" 34#include <iostream> 35 36using namespace llvm; 37 38namespace { 39 cl::opt<bool> 40 NoFusing("disable-spill-fusing", 41 cl::desc("Disable fusing of spill code into instructions")); 42 cl::opt<bool> 43 PrintFailedFusing("print-failed-fuse-candidates", 44 cl::desc("Print instructions that the allocator wants to" 45 " fuse, but the X86 backend currently can't"), 46 cl::Hidden); 47} 48 49X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, 50 const TargetInstrInfo &tii) 51 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), 52 TM(tm), TII(tii) { 53 // Cache some information. 54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 55 Is64Bit = Subtarget->is64Bit(); 56 if (Is64Bit) { 57 SlotSize = 8; 58 StackPtr = X86::RSP; 59 FramePtr = X86::RBP; 60 } else { 61 SlotSize = 4; 62 StackPtr = X86::ESP; 63 FramePtr = X86::EBP; 64 } 65} 66 67void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator MI, 69 unsigned SrcReg, int FrameIdx, 70 const TargetRegisterClass *RC) const { 71 unsigned Opc; 72 if (RC == &X86::GR64RegClass) { 73 Opc = X86::MOV64mr; 74 } else if (RC == &X86::GR32RegClass) { 75 Opc = X86::MOV32mr; 76 } else if (RC == &X86::GR16RegClass) { 77 Opc = X86::MOV16mr; 78 } else if (RC == &X86::GR8RegClass) { 79 Opc = X86::MOV8mr; 80 } else if (RC == &X86::GR32_RegClass) { 81 Opc = X86::MOV32_mr; 82 } else if (RC == &X86::GR16_RegClass) { 83 Opc = X86::MOV16_mr; 84 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 85 Opc = X86::FpST64m; 86 } else if (RC == &X86::FR32RegClass) { 87 Opc = X86::MOVSSmr; 88 } else if (RC == &X86::FR64RegClass) { 89 Opc = X86::MOVSDmr; 90 } else if (RC == &X86::VR128RegClass) { 91 Opc = X86::MOVAPSmr; 92 } else { 93 assert(0 && "Unknown regclass"); 94 abort(); 95 } 96 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg); 97} 98 99void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 100 MachineBasicBlock::iterator MI, 101 unsigned DestReg, int FrameIdx, 102 const TargetRegisterClass *RC) const{ 103 unsigned Opc; 104 if (RC == &X86::GR64RegClass) { 105 Opc = X86::MOV64rm; 106 } else if (RC == &X86::GR32RegClass) { 107 Opc = X86::MOV32rm; 108 } else if (RC == &X86::GR16RegClass) { 109 Opc = X86::MOV16rm; 110 } else if (RC == &X86::GR8RegClass) { 111 Opc = X86::MOV8rm; 112 } else if (RC == &X86::GR32_RegClass) { 113 Opc = X86::MOV32_rm; 114 } else if (RC == &X86::GR16_RegClass) { 115 Opc = X86::MOV16_rm; 116 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 117 Opc = X86::FpLD64m; 118 } else if (RC == &X86::FR32RegClass) { 119 Opc = X86::MOVSSrm; 120 } else if (RC == &X86::FR64RegClass) { 121 Opc = X86::MOVSDrm; 122 } else if (RC == &X86::VR128RegClass) { 123 Opc = X86::MOVAPSrm; 124 } else { 125 assert(0 && "Unknown regclass"); 126 abort(); 127 } 128 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx); 129} 130 131void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 132 MachineBasicBlock::iterator MI, 133 unsigned DestReg, unsigned SrcReg, 134 const TargetRegisterClass *RC) const { 135 unsigned Opc; 136 if (RC == &X86::GR64RegClass) { 137 Opc = X86::MOV64rr; 138 } else if (RC == &X86::GR32RegClass) { 139 Opc = X86::MOV32rr; 140 } else if (RC == &X86::GR16RegClass) { 141 Opc = X86::MOV16rr; 142 } else if (RC == &X86::GR8RegClass) { 143 Opc = X86::MOV8rr; 144 } else if (RC == &X86::GR32_RegClass) { 145 Opc = X86::MOV32_rr; 146 } else if (RC == &X86::GR16_RegClass) { 147 Opc = X86::MOV16_rr; 148 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 149 Opc = X86::FpMOV; 150 } else if (RC == &X86::FR32RegClass) { 151 Opc = X86::FsMOVAPSrr; 152 } else if (RC == &X86::FR64RegClass) { 153 Opc = X86::FsMOVAPDrr; 154 } else if (RC == &X86::VR128RegClass) { 155 Opc = X86::MOVAPSrr; 156 } else { 157 assert(0 && "Unknown regclass"); 158 abort(); 159 } 160 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg); 161} 162 163static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex, 164 MachineInstr *MI, 165 const TargetInstrInfo &TII) { 166 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; 167 // Create the base instruction with the memory operand as the first part. 168 MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps), 169 FrameIndex); 170 171 // Loop over the rest of the ri operands, converting them over. 172 for (unsigned i = 0; i != NumOps; ++i) { 173 MachineOperand &MO = MI->getOperand(i+2); 174 if (MO.isReg()) 175 MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit()); 176 else if (MO.isImm()) 177 MIB = MIB.addImm(MO.getImm()); 178 else if (MO.isGlobalAddress()) 179 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); 180 else if (MO.isJumpTableIndex()) 181 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex()); 182 else 183 assert(0 && "Unknown operand type!"); 184 } 185 return MIB; 186} 187 188static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, 189 unsigned FrameIndex, MachineInstr *MI, 190 const TargetInstrInfo &TII) { 191 MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3); 192 193 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 194 MachineOperand &MO = MI->getOperand(i); 195 if (i == OpNo) { 196 assert(MO.isReg() && "Expected to fold into reg operand!"); 197 MIB = addFrameReference(MIB, FrameIndex); 198 } else if (MO.isReg()) 199 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); 200 else if (MO.isImm()) 201 MIB = MIB.addImm(MO.getImm()); 202 else if (MO.isGlobalAddress()) 203 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); 204 else if (MO.isJumpTableIndex()) 205 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex()); 206 else 207 assert(0 && "Unknown operand for FuseInst!"); 208 } 209 return MIB; 210} 211 212static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, 213 unsigned Opcode, unsigned FrameIndex, 214 MachineInstr *MI) { 215 return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0); 216} 217 218 219//===----------------------------------------------------------------------===// 220// Efficient Lookup Table Support 221//===----------------------------------------------------------------------===// 222 223namespace { 224 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode. 225 /// 226 struct TableEntry { 227 unsigned from; // Original opcode. 228 unsigned to; // New opcode. 229 230 // less operators used by STL search. 231 bool operator<(const TableEntry &TE) const { return from < TE.from; } 232 friend bool operator<(const TableEntry &TE, unsigned V) { 233 return TE.from < V; 234 } 235 friend bool operator<(unsigned V, const TableEntry &TE) { 236 return V < TE.from; 237 } 238 }; 239} 240 241/// TableIsSorted - Return true if the table is in 'from' opcode order. 242/// 243static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 244 for (unsigned i = 1; i != NumEntries; ++i) 245 if (!(Table[i-1] < Table[i])) { 246 std::cerr << "Entries out of order " << Table[i-1].from 247 << " " << Table[i].from << "\n"; 248 return false; 249 } 250 return true; 251} 252 253/// TableLookup - Return the table entry matching the specified opcode. 254/// Otherwise return NULL. 255static const TableEntry *TableLookup(const TableEntry *Table, unsigned N, 256 unsigned Opcode) { 257 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 258 if (I != Table+N && I->from == Opcode) 259 return I; 260 return NULL; 261} 262 263#define ARRAY_SIZE(TABLE) \ 264 (sizeof(TABLE)/sizeof(TABLE[0])) 265 266#ifdef NDEBUG 267#define ASSERT_SORTED(TABLE) 268#else 269#define ASSERT_SORTED(TABLE) \ 270 { static bool TABLE##Checked = false; \ 271 if (!TABLE##Checked) { \ 272 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ 273 "All lookup tables must be sorted for efficient access!"); \ 274 TABLE##Checked = true; \ 275 } \ 276 } 277#endif 278 279 280MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, 281 unsigned i, 282 int FrameIndex) const { 283 // Check switch flag 284 if (NoFusing) return NULL; 285 286 // Table (and size) to search 287 const TableEntry *OpcodeTablePtr = NULL; 288 unsigned OpcodeTableSize = 0; 289 bool isTwoAddrFold = false; 290 unsigned NumOps = TII.getNumOperands(MI->getOpcode()); 291 bool isTwoAddr = NumOps > 1 && 292 TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1; 293 294 MachineInstr *NewMI = NULL; 295 // Folding a memory location into the two-address part of a two-address 296 // instruction is different than folding it other places. It requires 297 // replacing the *two* registers with the memory location. 298 if (isTwoAddr && NumOps >= 2 && i < 2 && 299 MI->getOperand(0).isReg() && 300 MI->getOperand(1).isReg() && 301 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 302 static const TableEntry OpcodeTable[] = { 303 { X86::ADC32ri, X86::ADC32mi }, 304 { X86::ADC32ri8, X86::ADC32mi8 }, 305 { X86::ADC32rr, X86::ADC32mr }, 306 { X86::ADC64ri32, X86::ADC64mi32 }, 307 { X86::ADC64ri8, X86::ADC64mi8 }, 308 { X86::ADC64rr, X86::ADC64mr }, 309 { X86::ADD16ri, X86::ADD16mi }, 310 { X86::ADD16ri8, X86::ADD16mi8 }, 311 { X86::ADD16rr, X86::ADD16mr }, 312 { X86::ADD32ri, X86::ADD32mi }, 313 { X86::ADD32ri8, X86::ADD32mi8 }, 314 { X86::ADD32rr, X86::ADD32mr }, 315 { X86::ADD64ri32, X86::ADD64mi32 }, 316 { X86::ADD64ri8, X86::ADD64mi8 }, 317 { X86::ADD64rr, X86::ADD64mr }, 318 { X86::ADD8ri, X86::ADD8mi }, 319 { X86::ADD8rr, X86::ADD8mr }, 320 { X86::AND16ri, X86::AND16mi }, 321 { X86::AND16ri8, X86::AND16mi8 }, 322 { X86::AND16rr, X86::AND16mr }, 323 { X86::AND32ri, X86::AND32mi }, 324 { X86::AND32ri8, X86::AND32mi8 }, 325 { X86::AND32rr, X86::AND32mr }, 326 { X86::AND64ri32, X86::AND64mi32 }, 327 { X86::AND64ri8, X86::AND64mi8 }, 328 { X86::AND64rr, X86::AND64mr }, 329 { X86::AND8ri, X86::AND8mi }, 330 { X86::AND8rr, X86::AND8mr }, 331 { X86::DEC16r, X86::DEC16m }, 332 { X86::DEC32r, X86::DEC32m }, 333 { X86::DEC64_16r, X86::DEC16m }, 334 { X86::DEC64_32r, X86::DEC32m }, 335 { X86::DEC64r, X86::DEC64m }, 336 { X86::DEC8r, X86::DEC8m }, 337 { X86::INC16r, X86::INC16m }, 338 { X86::INC32r, X86::INC32m }, 339 { X86::INC64_16r, X86::INC16m }, 340 { X86::INC64_32r, X86::INC32m }, 341 { X86::INC64r, X86::INC64m }, 342 { X86::INC8r, X86::INC8m }, 343 { X86::NEG16r, X86::NEG16m }, 344 { X86::NEG32r, X86::NEG32m }, 345 { X86::NEG64r, X86::NEG64m }, 346 { X86::NEG8r, X86::NEG8m }, 347 { X86::NOT16r, X86::NOT16m }, 348 { X86::NOT32r, X86::NOT32m }, 349 { X86::NOT64r, X86::NOT64m }, 350 { X86::NOT8r, X86::NOT8m }, 351 { X86::OR16ri, X86::OR16mi }, 352 { X86::OR16ri8, X86::OR16mi8 }, 353 { X86::OR16rr, X86::OR16mr }, 354 { X86::OR32ri, X86::OR32mi }, 355 { X86::OR32ri8, X86::OR32mi8 }, 356 { X86::OR32rr, X86::OR32mr }, 357 { X86::OR64ri32, X86::OR64mi32 }, 358 { X86::OR64ri8, X86::OR64mi8 }, 359 { X86::OR64rr, X86::OR64mr }, 360 { X86::OR8ri, X86::OR8mi }, 361 { X86::OR8rr, X86::OR8mr }, 362 { X86::ROL16r1, X86::ROL16m1 }, 363 { X86::ROL16rCL, X86::ROL16mCL }, 364 { X86::ROL16ri, X86::ROL16mi }, 365 { X86::ROL32r1, X86::ROL32m1 }, 366 { X86::ROL32rCL, X86::ROL32mCL }, 367 { X86::ROL32ri, X86::ROL32mi }, 368 { X86::ROL64r1, X86::ROL64m1 }, 369 { X86::ROL64rCL, X86::ROL64mCL }, 370 { X86::ROL64ri, X86::ROL64mi }, 371 { X86::ROL8r1, X86::ROL8m1 }, 372 { X86::ROL8rCL, X86::ROL8mCL }, 373 { X86::ROL8ri, X86::ROL8mi }, 374 { X86::ROR16r1, X86::ROR16m1 }, 375 { X86::ROR16rCL, X86::ROR16mCL }, 376 { X86::ROR16ri, X86::ROR16mi }, 377 { X86::ROR32r1, X86::ROR32m1 }, 378 { X86::ROR32rCL, X86::ROR32mCL }, 379 { X86::ROR32ri, X86::ROR32mi }, 380 { X86::ROR64r1, X86::ROR64m1 }, 381 { X86::ROR64rCL, X86::ROR64mCL }, 382 { X86::ROR64ri, X86::ROR64mi }, 383 { X86::ROR8r1, X86::ROR8m1 }, 384 { X86::ROR8rCL, X86::ROR8mCL }, 385 { X86::ROR8ri, X86::ROR8mi }, 386 { X86::SAR16r1, X86::SAR16m1 }, 387 { X86::SAR16rCL, X86::SAR16mCL }, 388 { X86::SAR16ri, X86::SAR16mi }, 389 { X86::SAR32r1, X86::SAR32m1 }, 390 { X86::SAR32rCL, X86::SAR32mCL }, 391 { X86::SAR32ri, X86::SAR32mi }, 392 { X86::SAR64r1, X86::SAR64m1 }, 393 { X86::SAR64rCL, X86::SAR64mCL }, 394 { X86::SAR64ri, X86::SAR64mi }, 395 { X86::SAR8r1, X86::SAR8m1 }, 396 { X86::SAR8rCL, X86::SAR8mCL }, 397 { X86::SAR8ri, X86::SAR8mi }, 398 { X86::SBB32ri, X86::SBB32mi }, 399 { X86::SBB32ri8, X86::SBB32mi8 }, 400 { X86::SBB32rr, X86::SBB32mr }, 401 { X86::SBB64ri32, X86::SBB64mi32 }, 402 { X86::SBB64ri8, X86::SBB64mi8 }, 403 { X86::SBB64rr, X86::SBB64mr }, 404 { X86::SHL16r1, X86::SHL16m1 }, 405 { X86::SHL16rCL, X86::SHL16mCL }, 406 { X86::SHL16ri, X86::SHL16mi }, 407 { X86::SHL32r1, X86::SHL32m1 }, 408 { X86::SHL32rCL, X86::SHL32mCL }, 409 { X86::SHL32ri, X86::SHL32mi }, 410 { X86::SHL64r1, X86::SHL64m1 }, 411 { X86::SHL64rCL, X86::SHL64mCL }, 412 { X86::SHL64ri, X86::SHL64mi }, 413 { X86::SHL8r1, X86::SHL8m1 }, 414 { X86::SHL8rCL, X86::SHL8mCL }, 415 { X86::SHL8ri, X86::SHL8mi }, 416 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 417 { X86::SHLD16rri8, X86::SHLD16mri8 }, 418 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 419 { X86::SHLD32rri8, X86::SHLD32mri8 }, 420 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 421 { X86::SHLD64rri8, X86::SHLD64mri8 }, 422 { X86::SHR16r1, X86::SHR16m1 }, 423 { X86::SHR16rCL, X86::SHR16mCL }, 424 { X86::SHR16ri, X86::SHR16mi }, 425 { X86::SHR32r1, X86::SHR32m1 }, 426 { X86::SHR32rCL, X86::SHR32mCL }, 427 { X86::SHR32ri, X86::SHR32mi }, 428 { X86::SHR64r1, X86::SHR64m1 }, 429 { X86::SHR64rCL, X86::SHR64mCL }, 430 { X86::SHR64ri, X86::SHR64mi }, 431 { X86::SHR8r1, X86::SHR8m1 }, 432 { X86::SHR8rCL, X86::SHR8mCL }, 433 { X86::SHR8ri, X86::SHR8mi }, 434 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 435 { X86::SHRD16rri8, X86::SHRD16mri8 }, 436 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 437 { X86::SHRD32rri8, X86::SHRD32mri8 }, 438 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 439 { X86::SHRD64rri8, X86::SHRD64mri8 }, 440 { X86::SUB16ri, X86::SUB16mi }, 441 { X86::SUB16ri8, X86::SUB16mi8 }, 442 { X86::SUB16rr, X86::SUB16mr }, 443 { X86::SUB32ri, X86::SUB32mi }, 444 { X86::SUB32ri8, X86::SUB32mi8 }, 445 { X86::SUB32rr, X86::SUB32mr }, 446 { X86::SUB64ri32, X86::SUB64mi32 }, 447 { X86::SUB64ri8, X86::SUB64mi8 }, 448 { X86::SUB64rr, X86::SUB64mr }, 449 { X86::SUB8ri, X86::SUB8mi }, 450 { X86::SUB8rr, X86::SUB8mr }, 451 { X86::XOR16ri, X86::XOR16mi }, 452 { X86::XOR16ri8, X86::XOR16mi8 }, 453 { X86::XOR16rr, X86::XOR16mr }, 454 { X86::XOR32ri, X86::XOR32mi }, 455 { X86::XOR32ri8, X86::XOR32mi8 }, 456 { X86::XOR32rr, X86::XOR32mr }, 457 { X86::XOR64ri32, X86::XOR64mi32 }, 458 { X86::XOR64ri8, X86::XOR64mi8 }, 459 { X86::XOR64rr, X86::XOR64mr }, 460 { X86::XOR8ri, X86::XOR8mi }, 461 { X86::XOR8rr, X86::XOR8mr } 462 }; 463 ASSERT_SORTED(OpcodeTable); 464 OpcodeTablePtr = OpcodeTable; 465 OpcodeTableSize = ARRAY_SIZE(OpcodeTable); 466 isTwoAddrFold = true; 467 } else if (i == 0) { // If operand 0 468 if (MI->getOpcode() == X86::MOV16r0) 469 NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI); 470 else if (MI->getOpcode() == X86::MOV32r0) 471 NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI); 472 else if (MI->getOpcode() == X86::MOV64r0) 473 NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI); 474 else if (MI->getOpcode() == X86::MOV8r0) 475 NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI); 476 if (NewMI) { 477 NewMI->copyKillDeadInfo(MI); 478 return NewMI; 479 } 480 481 static const TableEntry OpcodeTable[] = { 482 { X86::CMP16ri, X86::CMP16mi }, 483 { X86::CMP16ri8, X86::CMP16mi8 }, 484 { X86::CMP32ri, X86::CMP32mi }, 485 { X86::CMP32ri8, X86::CMP32mi8 }, 486 { X86::CMP8ri, X86::CMP8mi }, 487 { X86::DIV16r, X86::DIV16m }, 488 { X86::DIV32r, X86::DIV32m }, 489 { X86::DIV64r, X86::DIV64m }, 490 { X86::DIV8r, X86::DIV8m }, 491 { X86::FsMOVAPDrr, X86::MOVSDmr }, 492 { X86::FsMOVAPSrr, X86::MOVSSmr }, 493 { X86::IDIV16r, X86::IDIV16m }, 494 { X86::IDIV32r, X86::IDIV32m }, 495 { X86::IDIV64r, X86::IDIV64m }, 496 { X86::IDIV8r, X86::IDIV8m }, 497 { X86::IMUL16r, X86::IMUL16m }, 498 { X86::IMUL32r, X86::IMUL32m }, 499 { X86::IMUL64r, X86::IMUL64m }, 500 { X86::IMUL8r, X86::IMUL8m }, 501 { X86::MOV16ri, X86::MOV16mi }, 502 { X86::MOV16rr, X86::MOV16mr }, 503 { X86::MOV32ri, X86::MOV32mi }, 504 { X86::MOV32rr, X86::MOV32mr }, 505 { X86::MOV64ri32, X86::MOV64mi32 }, 506 { X86::MOV64rr, X86::MOV64mr }, 507 { X86::MOV8ri, X86::MOV8mi }, 508 { X86::MOV8rr, X86::MOV8mr }, 509 { X86::MOVAPDrr, X86::MOVAPDmr }, 510 { X86::MOVAPSrr, X86::MOVAPSmr }, 511 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr }, 512 { X86::MOVPQIto64rr,X86::MOVPQIto64mr }, 513 { X86::MOVPS2SSrr, X86::MOVPS2SSmr }, 514 { X86::MOVSDrr, X86::MOVSDmr }, 515 { X86::MOVSSrr, X86::MOVSSmr }, 516 { X86::MOVUPDrr, X86::MOVUPDmr }, 517 { X86::MOVUPSrr, X86::MOVUPSmr }, 518 { X86::MUL16r, X86::MUL16m }, 519 { X86::MUL32r, X86::MUL32m }, 520 { X86::MUL64r, X86::MUL64m }, 521 { X86::MUL8r, X86::MUL8m }, 522 { X86::SETAEr, X86::SETAEm }, 523 { X86::SETAr, X86::SETAm }, 524 { X86::SETBEr, X86::SETBEm }, 525 { X86::SETBr, X86::SETBm }, 526 { X86::SETEr, X86::SETEm }, 527 { X86::SETGEr, X86::SETGEm }, 528 { X86::SETGr, X86::SETGm }, 529 { X86::SETLEr, X86::SETLEm }, 530 { X86::SETLr, X86::SETLm }, 531 { X86::SETNEr, X86::SETNEm }, 532 { X86::SETNPr, X86::SETNPm }, 533 { X86::SETNSr, X86::SETNSm }, 534 { X86::SETPr, X86::SETPm }, 535 { X86::SETSr, X86::SETSm }, 536 { X86::TEST16ri, X86::TEST16mi }, 537 { X86::TEST32ri, X86::TEST32mi }, 538 { X86::TEST64ri32, X86::TEST64mi32 }, 539 { X86::TEST8ri, X86::TEST8mi }, 540 { X86::XCHG16rr, X86::XCHG16mr }, 541 { X86::XCHG32rr, X86::XCHG32mr }, 542 { X86::XCHG64rr, X86::XCHG64mr }, 543 { X86::XCHG8rr, X86::XCHG8mr } 544 }; 545 ASSERT_SORTED(OpcodeTable); 546 OpcodeTablePtr = OpcodeTable; 547 OpcodeTableSize = ARRAY_SIZE(OpcodeTable); 548 } else if (i == 1) { 549 static const TableEntry OpcodeTable[] = { 550 { X86::CMP16rr, X86::CMP16rm }, 551 { X86::CMP32rr, X86::CMP32rm }, 552 { X86::CMP64ri32, X86::CMP64mi32 }, 553 { X86::CMP64ri8, X86::CMP64mi8 }, 554 { X86::CMP64rr, X86::CMP64rm }, 555 { X86::CMP8rr, X86::CMP8rm }, 556 { X86::CMPPDrri, X86::CMPPDrmi }, 557 { X86::CMPPSrri, X86::CMPPSrmi }, 558 { X86::CMPSDrr, X86::CMPSDrm }, 559 { X86::CMPSSrr, X86::CMPSSrm }, 560 { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, 561 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, 562 { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, 563 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, 564 { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, 565 { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, 566 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, 567 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, 568 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, 569 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, 570 { X86::FsMOVAPDrr, X86::MOVSDrm }, 571 { X86::FsMOVAPSrr, X86::MOVSSrm }, 572 { X86::IMUL16rri, X86::IMUL16rmi }, 573 { X86::IMUL16rri8, X86::IMUL16rmi8 }, 574 { X86::IMUL32rri, X86::IMUL32rmi }, 575 { X86::IMUL32rri8, X86::IMUL32rmi8 }, 576 { X86::IMUL64rr, X86::IMUL64rm }, 577 { X86::IMUL64rri32, X86::IMUL64rmi32 }, 578 { X86::IMUL64rri8, X86::IMUL64rmi8 }, 579 { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, 580 { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, 581 { X86::Int_COMISDrr, X86::Int_COMISDrm }, 582 { X86::Int_COMISSrr, X86::Int_COMISSrm }, 583 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, 584 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, 585 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, 586 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, 587 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, 588 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, 589 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, 590 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, 591 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, 592 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, 593 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, 594 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, 595 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, 596 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, 597 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, 598 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, 599 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, 600 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, 601 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, 602 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, 603 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, 604 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, 605 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, 606 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, 607 { X86::MOV16rr, X86::MOV16rm }, 608 { X86::MOV32rr, X86::MOV32rm }, 609 { X86::MOV64rr, X86::MOV64rm }, 610 { X86::MOV64toPQIrr, X86::MOV64toPQIrm }, 611 { X86::MOV8rr, X86::MOV8rm }, 612 { X86::MOVAPDrr, X86::MOVAPDrm }, 613 { X86::MOVAPSrr, X86::MOVAPSrm }, 614 { X86::MOVDDUPrr, X86::MOVDDUPrm }, 615 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, 616 { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, 617 { X86::MOVSDrr, X86::MOVSDrm }, 618 { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, 619 { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, 620 { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, 621 { X86::MOVSSrr, X86::MOVSSrm }, 622 { X86::MOVSX16rr8, X86::MOVSX16rm8 }, 623 { X86::MOVSX32rr16, X86::MOVSX32rm16 }, 624 { X86::MOVSX32rr8, X86::MOVSX32rm8 }, 625 { X86::MOVSX64rr16, X86::MOVSX64rm16 }, 626 { X86::MOVSX64rr32, X86::MOVSX64rm32 }, 627 { X86::MOVSX64rr8, X86::MOVSX64rm8 }, 628 { X86::MOVUPDrr, X86::MOVUPDrm }, 629 { X86::MOVUPSrr, X86::MOVUPSrm }, 630 { X86::MOVZX16rr8, X86::MOVZX16rm8 }, 631 { X86::MOVZX32rr16, X86::MOVZX32rm16 }, 632 { X86::MOVZX32rr8, X86::MOVZX32rm8 }, 633 { X86::MOVZX64rr16, X86::MOVZX64rm16 }, 634 { X86::MOVZX64rr8, X86::MOVZX64rm8 }, 635 { X86::PSHUFDri, X86::PSHUFDmi }, 636 { X86::PSHUFHWri, X86::PSHUFHWmi }, 637 { X86::PSHUFLWri, X86::PSHUFLWmi }, 638 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 }, 639 { X86::TEST16rr, X86::TEST16rm }, 640 { X86::TEST32rr, X86::TEST32rm }, 641 { X86::TEST64rr, X86::TEST64rm }, 642 { X86::TEST8rr, X86::TEST8rm }, 643 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 644 { X86::UCOMISDrr, X86::UCOMISDrm }, 645 { X86::UCOMISSrr, X86::UCOMISSrm }, 646 { X86::XCHG16rr, X86::XCHG16rm }, 647 { X86::XCHG32rr, X86::XCHG32rm }, 648 { X86::XCHG64rr, X86::XCHG64rm }, 649 { X86::XCHG8rr, X86::XCHG8rm } 650 }; 651 ASSERT_SORTED(OpcodeTable); 652 OpcodeTablePtr = OpcodeTable; 653 OpcodeTableSize = ARRAY_SIZE(OpcodeTable); 654 } else if (i == 2) { 655 static const TableEntry OpcodeTable[] = { 656 { X86::ADC32rr, X86::ADC32rm }, 657 { X86::ADC64rr, X86::ADC64rm }, 658 { X86::ADD16rr, X86::ADD16rm }, 659 { X86::ADD32rr, X86::ADD32rm }, 660 { X86::ADD64rr, X86::ADD64rm }, 661 { X86::ADD8rr, X86::ADD8rm }, 662 { X86::ADDPDrr, X86::ADDPDrm }, 663 { X86::ADDPSrr, X86::ADDPSrm }, 664 { X86::ADDSDrr, X86::ADDSDrm }, 665 { X86::ADDSSrr, X86::ADDSSrm }, 666 { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, 667 { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, 668 { X86::AND16rr, X86::AND16rm }, 669 { X86::AND32rr, X86::AND32rm }, 670 { X86::AND64rr, X86::AND64rm }, 671 { X86::AND8rr, X86::AND8rm }, 672 { X86::ANDNPDrr, X86::ANDNPDrm }, 673 { X86::ANDNPSrr, X86::ANDNPSrm }, 674 { X86::ANDPDrr, X86::ANDPDrm }, 675 { X86::ANDPSrr, X86::ANDPSrm }, 676 { X86::CMOVA16rr, X86::CMOVA16rm }, 677 { X86::CMOVA32rr, X86::CMOVA32rm }, 678 { X86::CMOVA64rr, X86::CMOVA64rm }, 679 { X86::CMOVAE16rr, X86::CMOVAE16rm }, 680 { X86::CMOVAE32rr, X86::CMOVAE32rm }, 681 { X86::CMOVAE64rr, X86::CMOVAE64rm }, 682 { X86::CMOVB16rr, X86::CMOVB16rm }, 683 { X86::CMOVB32rr, X86::CMOVB32rm }, 684 { X86::CMOVB64rr, X86::CMOVB64rm }, 685 { X86::CMOVBE16rr, X86::CMOVBE16rm }, 686 { X86::CMOVBE32rr, X86::CMOVBE32rm }, 687 { X86::CMOVBE64rr, X86::CMOVBE64rm }, 688 { X86::CMOVE16rr, X86::CMOVE16rm }, 689 { X86::CMOVE32rr, X86::CMOVE32rm }, 690 { X86::CMOVE64rr, X86::CMOVE64rm }, 691 { X86::CMOVG16rr, X86::CMOVG16rm }, 692 { X86::CMOVG32rr, X86::CMOVG32rm }, 693 { X86::CMOVG64rr, X86::CMOVG64rm }, 694 { X86::CMOVGE16rr, X86::CMOVGE16rm }, 695 { X86::CMOVGE32rr, X86::CMOVGE32rm }, 696 { X86::CMOVGE64rr, X86::CMOVGE64rm }, 697 { X86::CMOVL16rr, X86::CMOVL16rm }, 698 { X86::CMOVL32rr, X86::CMOVL32rm }, 699 { X86::CMOVL64rr, X86::CMOVL64rm }, 700 { X86::CMOVLE16rr, X86::CMOVLE16rm }, 701 { X86::CMOVLE32rr, X86::CMOVLE32rm }, 702 { X86::CMOVLE64rr, X86::CMOVLE64rm }, 703 { X86::CMOVNE16rr, X86::CMOVNE16rm }, 704 { X86::CMOVNE32rr, X86::CMOVNE32rm }, 705 { X86::CMOVNE64rr, X86::CMOVNE64rm }, 706 { X86::CMOVNP16rr, X86::CMOVNP16rm }, 707 { X86::CMOVNP32rr, X86::CMOVNP32rm }, 708 { X86::CMOVNP64rr, X86::CMOVNP64rm }, 709 { X86::CMOVNS16rr, X86::CMOVNS16rm }, 710 { X86::CMOVNS32rr, X86::CMOVNS32rm }, 711 { X86::CMOVNS64rr, X86::CMOVNS64rm }, 712 { X86::CMOVP16rr, X86::CMOVP16rm }, 713 { X86::CMOVP32rr, X86::CMOVP32rm }, 714 { X86::CMOVP64rr, X86::CMOVP64rm }, 715 { X86::CMOVS16rr, X86::CMOVS16rm }, 716 { X86::CMOVS32rr, X86::CMOVS32rm }, 717 { X86::CMOVS64rr, X86::CMOVS64rm }, 718 { X86::DIVPDrr, X86::DIVPDrm }, 719 { X86::DIVPSrr, X86::DIVPSrm }, 720 { X86::DIVSDrr, X86::DIVSDrm }, 721 { X86::DIVSSrr, X86::DIVSSrm }, 722 { X86::HADDPDrr, X86::HADDPDrm }, 723 { X86::HADDPSrr, X86::HADDPSrm }, 724 { X86::HSUBPDrr, X86::HSUBPDrm }, 725 { X86::HSUBPSrr, X86::HSUBPSrm }, 726 { X86::IMUL16rr, X86::IMUL16rm }, 727 { X86::IMUL32rr, X86::IMUL32rm }, 728 { X86::MAXPDrr, X86::MAXPDrm }, 729 { X86::MAXPSrr, X86::MAXPSrm }, 730 { X86::MINPDrr, X86::MINPDrm }, 731 { X86::MINPSrr, X86::MINPSrm }, 732 { X86::MULPDrr, X86::MULPDrm }, 733 { X86::MULPSrr, X86::MULPSrm }, 734 { X86::MULSDrr, X86::MULSDrm }, 735 { X86::MULSSrr, X86::MULSSrm }, 736 { X86::OR16rr, X86::OR16rm }, 737 { X86::OR32rr, X86::OR32rm }, 738 { X86::OR64rr, X86::OR64rm }, 739 { X86::OR8rr, X86::OR8rm }, 740 { X86::ORPDrr, X86::ORPDrm }, 741 { X86::ORPSrr, X86::ORPSrm }, 742 { X86::PACKSSDWrr, X86::PACKSSDWrm }, 743 { X86::PACKSSWBrr, X86::PACKSSWBrm }, 744 { X86::PACKUSWBrr, X86::PACKUSWBrm }, 745 { X86::PADDBrr, X86::PADDBrm }, 746 { X86::PADDDrr, X86::PADDDrm }, 747 { X86::PADDSBrr, X86::PADDSBrm }, 748 { X86::PADDSWrr, X86::PADDSWrm }, 749 { X86::PADDWrr, X86::PADDWrm }, 750 { X86::PANDNrr, X86::PANDNrm }, 751 { X86::PANDrr, X86::PANDrm }, 752 { X86::PAVGBrr, X86::PAVGBrm }, 753 { X86::PAVGWrr, X86::PAVGWrm }, 754 { X86::PCMPEQBrr, X86::PCMPEQBrm }, 755 { X86::PCMPEQDrr, X86::PCMPEQDrm }, 756 { X86::PCMPEQWrr, X86::PCMPEQWrm }, 757 { X86::PCMPGTBrr, X86::PCMPGTBrm }, 758 { X86::PCMPGTDrr, X86::PCMPGTDrm }, 759 { X86::PCMPGTWrr, X86::PCMPGTWrm }, 760 { X86::PINSRWrri, X86::PINSRWrmi }, 761 { X86::PMADDWDrr, X86::PMADDWDrm }, 762 { X86::PMAXSWrr, X86::PMAXSWrm }, 763 { X86::PMAXUBrr, X86::PMAXUBrm }, 764 { X86::PMINSWrr, X86::PMINSWrm }, 765 { X86::PMINUBrr, X86::PMINUBrm }, 766 { X86::PMULHUWrr, X86::PMULHUWrm }, 767 { X86::PMULHWrr, X86::PMULHWrm }, 768 { X86::PMULLWrr, X86::PMULLWrm }, 769 { X86::PMULUDQrr, X86::PMULUDQrm }, 770 { X86::PORrr, X86::PORrm }, 771 { X86::PSADBWrr, X86::PSADBWrm }, 772 { X86::PSLLDrr, X86::PSLLDrm }, 773 { X86::PSLLQrr, X86::PSLLQrm }, 774 { X86::PSLLWrr, X86::PSLLWrm }, 775 { X86::PSRADrr, X86::PSRADrm }, 776 { X86::PSRAWrr, X86::PSRAWrm }, 777 { X86::PSRLDrr, X86::PSRLDrm }, 778 { X86::PSRLQrr, X86::PSRLQrm }, 779 { X86::PSRLWrr, X86::PSRLWrm }, 780 { X86::PSUBBrr, X86::PSUBBrm }, 781 { X86::PSUBDrr, X86::PSUBDrm }, 782 { X86::PSUBSBrr, X86::PSUBSBrm }, 783 { X86::PSUBSWrr, X86::PSUBSWrm }, 784 { X86::PSUBWrr, X86::PSUBWrm }, 785 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, 786 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, 787 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, 788 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, 789 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, 790 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, 791 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, 792 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, 793 { X86::PXORrr, X86::PXORrm }, 794 { X86::RCPPSr, X86::RCPPSm }, 795 { X86::RSQRTPSr, X86::RSQRTPSm }, 796 { X86::SBB32rr, X86::SBB32rm }, 797 { X86::SBB64rr, X86::SBB64rm }, 798 { X86::SHUFPDrri, X86::SHUFPDrmi }, 799 { X86::SHUFPSrri, X86::SHUFPSrmi }, 800 { X86::SQRTPDr, X86::SQRTPDm }, 801 { X86::SQRTPSr, X86::SQRTPSm }, 802 { X86::SQRTSDr, X86::SQRTSDm }, 803 { X86::SQRTSSr, X86::SQRTSSm }, 804 { X86::SUB16rr, X86::SUB16rm }, 805 { X86::SUB32rr, X86::SUB32rm }, 806 { X86::SUB64rr, X86::SUB64rm }, 807 { X86::SUB8rr, X86::SUB8rm }, 808 { X86::SUBPDrr, X86::SUBPDrm }, 809 { X86::SUBPSrr, X86::SUBPSrm }, 810 { X86::SUBSDrr, X86::SUBSDrm }, 811 { X86::SUBSSrr, X86::SUBSSrm }, 812 // FIXME: TEST*rr -> swapped operand of TEST*mr. 813 { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, 814 { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, 815 { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, 816 { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, 817 { X86::XOR16rr, X86::XOR16rm }, 818 { X86::XOR32rr, X86::XOR32rm }, 819 { X86::XOR64rr, X86::XOR64rm }, 820 { X86::XOR8rr, X86::XOR8rm }, 821 { X86::XORPDrr, X86::XORPDrm }, 822 { X86::XORPSrr, X86::XORPSrm } 823 }; 824 ASSERT_SORTED(OpcodeTable); 825 OpcodeTablePtr = OpcodeTable; 826 OpcodeTableSize = ARRAY_SIZE(OpcodeTable); 827 } 828 829 // If table selected... 830 if (OpcodeTablePtr) { 831 // Find the Opcode to fuse 832 unsigned fromOpcode = MI->getOpcode(); 833 // Lookup fromOpcode in table 834 if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize, 835 fromOpcode)) { 836 if (isTwoAddrFold) 837 NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII); 838 else 839 NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII); 840 NewMI->copyKillDeadInfo(MI); 841 return NewMI; 842 } 843 } 844 845 // No fusion 846 if (PrintFailedFusing) 847 std::cerr << "We failed to fuse (" 848 << ((i == 1) ? "r" : "s") << "): " << *MI; 849 return NULL; 850} 851 852 853const unsigned *X86RegisterInfo::getCalleeSaveRegs() const { 854 static const unsigned CalleeSaveRegs32Bit[] = { 855 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 856 }; 857 static const unsigned CalleeSaveRegs64Bit[] = { 858 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 859 }; 860 861 return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit; 862} 863 864const TargetRegisterClass* const* 865X86RegisterInfo::getCalleeSaveRegClasses() const { 866 static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = { 867 &X86::GR32RegClass, &X86::GR32RegClass, 868 &X86::GR32RegClass, &X86::GR32RegClass, 0 869 }; 870 static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = { 871 &X86::GR64RegClass, &X86::GR64RegClass, 872 &X86::GR64RegClass, &X86::GR64RegClass, 873 &X86::GR64RegClass, &X86::GR64RegClass, 0 874 }; 875 876 return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit; 877} 878 879//===----------------------------------------------------------------------===// 880// Stack Frame Processing methods 881//===----------------------------------------------------------------------===// 882 883// hasFP - Return true if the specified function should have a dedicated frame 884// pointer register. This is true if the function has variable sized allocas or 885// if frame pointer elimination is disabled. 886// 887static bool hasFP(const MachineFunction &MF) { 888 return (NoFramePointerElim || 889 MF.getFrameInfo()->hasVarSizedObjects() || 890 MF.getInfo<X86FunctionInfo>()->getForceFramePointer()); 891} 892 893void X86RegisterInfo:: 894eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 895 MachineBasicBlock::iterator I) const { 896 if (hasFP(MF)) { 897 // If we have a frame pointer, turn the adjcallstackup instruction into a 898 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP, 899 // <amt>' 900 MachineInstr *Old = I; 901 unsigned Amount = Old->getOperand(0).getImmedValue(); 902 if (Amount != 0) { 903 // We need to keep the stack aligned properly. To do this, we round the 904 // amount of space needed for the outgoing arguments up to the next 905 // alignment boundary. 906 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 907 Amount = (Amount+Align-1)/Align*Align; 908 909 MachineInstr *New = 0; 910 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { 911 New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr) 912 .addReg(StackPtr).addImm(Amount); 913 } else { 914 assert(Old->getOpcode() == X86::ADJCALLSTACKUP); 915 // factor out the amount the callee already popped. 916 unsigned CalleeAmt = Old->getOperand(1).getImmedValue(); 917 Amount -= CalleeAmt; 918 if (Amount) { 919 unsigned Opc = (Amount < 128) ? 920 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : 921 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); 922 New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount); 923 } 924 } 925 926 // Replace the pseudo instruction with a new instruction... 927 if (New) MBB.insert(I, New); 928 } 929 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { 930 // If we are performing frame pointer elimination and if the callee pops 931 // something off the stack pointer, add it back. We do this until we have 932 // more advanced stack pointer tracking ability. 933 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) { 934 unsigned Opc = (CalleeAmt < 128) ? 935 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : 936 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); 937 MachineInstr *New = 938 BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt); 939 MBB.insert(I, New); 940 } 941 } 942 943 MBB.erase(I); 944} 945 946void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 947 unsigned i = 0; 948 MachineInstr &MI = *II; 949 MachineFunction &MF = *MI.getParent()->getParent(); 950 while (!MI.getOperand(i).isFrameIndex()) { 951 ++i; 952 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 953 } 954 955 int FrameIndex = MI.getOperand(i).getFrameIndex(); 956 // This must be part of a four operand memory reference. Replace the 957 // FrameIndex with base register with EBP. Add an offset to the offset. 958 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false); 959 960 // Now add the frame object offset to the offset from EBP. 961 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 962 MI.getOperand(i+3).getImmedValue()+SlotSize; 963 964 if (!hasFP(MF)) 965 Offset += MF.getFrameInfo()->getStackSize(); 966 else 967 Offset += SlotSize; // Skip the saved EBP 968 969 MI.getOperand(i+3).ChangeToImmediate(Offset); 970} 971 972void 973X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ 974 if (hasFP(MF)) { 975 // Create a frame entry for the EBP register that must be saved. 976 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2); 977 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 978 "Slot for EBP register must be last in order to be found!"); 979 } 980} 981 982void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { 983 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 984 MachineBasicBlock::iterator MBBI = MBB.begin(); 985 MachineFrameInfo *MFI = MF.getFrameInfo(); 986 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 987 const Function* Fn = MF.getFunction(); 988 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); 989 MachineInstr *MI; 990 991 // Get the number of bytes to allocate from the FrameInfo 992 unsigned NumBytes = MFI->getStackSize(); 993 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) { 994 // When we have no frame pointer, we reserve argument space for call sites 995 // in the function immediately on entry to the current function. This 996 // eliminates the need for add/sub ESP brackets around call sites. 997 // 998 if (!hasFP(MF)) 999 NumBytes += MFI->getMaxCallFrameSize(); 1000 1001 // Round the size to a multiple of the alignment (don't forget the 4/8 byte 1002 // offset though). 1003 NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize; 1004 } 1005 1006 // Update frame info to pretend that this is part of the stack... 1007 MFI->setStackSize(NumBytes); 1008 1009 if (NumBytes) { // adjust stack pointer: ESP -= numbytes 1010 if (NumBytes >= 4096 && Subtarget->isTargetCygwin()) { 1011 // Function prologue calls _alloca to probe the stack when allocating 1012 // more than 4k bytes in one go. Touching the stack at 4K increments is 1013 // necessary to ensure that the guard pages used by the OS virtual memory 1014 // manager are allocated in correct sequence. 1015 MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes); 1016 MBB.insert(MBBI, MI); 1017 MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); 1018 MBB.insert(MBBI, MI); 1019 } else { 1020 unsigned Opc = (NumBytes < 128) ? 1021 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : 1022 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); 1023 MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes); 1024 MBB.insert(MBBI, MI); 1025 } 1026 } 1027 1028 if (hasFP(MF)) { 1029 // Get the offset of the stack slot for the EBP register... which is 1030 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 1031 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize; 1032 // Update the frame offset adjustment. 1033 MFI->setOffsetAdjustment(SlotSize-NumBytes); 1034 1035 // Save EBP into the appropriate stack slot... 1036 // mov [ESP-<offset>], EBP 1037 MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5), 1038 StackPtr, EBPOffset+NumBytes).addReg(FramePtr); 1039 MBB.insert(MBBI, MI); 1040 1041 // Update EBP with the new base value... 1042 if (NumBytes == SlotSize) // mov EBP, ESP 1043 MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr). 1044 addReg(StackPtr); 1045 else // lea EBP, [ESP+StackSize] 1046 MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r, 1047 5, FramePtr), StackPtr, NumBytes-SlotSize); 1048 1049 MBB.insert(MBBI, MI); 1050 } 1051 1052 // If it's main() on Cygwin\Mingw32 we should align stack as well 1053 if (Fn->hasExternalLinkage() && Fn->getName() == "main" && 1054 Subtarget->isTargetCygwin()) { 1055 MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align); 1056 MBB.insert(MBBI, MI); 1057 1058 // Probe the stack 1059 MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align); 1060 MBB.insert(MBBI, MI); 1061 MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); 1062 MBB.insert(MBBI, MI); 1063 } 1064} 1065 1066void X86RegisterInfo::emitEpilogue(MachineFunction &MF, 1067 MachineBasicBlock &MBB) const { 1068 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1069 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1070 1071 switch (MBBI->getOpcode()) { 1072 case X86::RET: 1073 case X86::RETI: 1074 case X86::TAILJMPd: 1075 case X86::TAILJMPr: 1076 case X86::TAILJMPm: break; // These are ok 1077 default: 1078 assert(0 && "Can only insert epilog into returning blocks"); 1079 } 1080 1081 if (hasFP(MF)) { 1082 // mov ESP, EBP 1083 BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr). 1084 addReg(FramePtr); 1085 1086 // pop EBP 1087 BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr); 1088 } else { 1089 // Get the number of bytes allocated from the FrameInfo... 1090 unsigned NumBytes = MFI->getStackSize(); 1091 1092 if (NumBytes) { // adjust stack pointer back: ESP += numbytes 1093 // If there is an ADD32ri or SUB32ri of ESP immediately before this 1094 // instruction, merge the two instructions. 1095 if (MBBI != MBB.begin()) { 1096 MachineBasicBlock::iterator PI = prior(MBBI); 1097 unsigned Opc = PI->getOpcode(); 1098 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 1099 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 1100 PI->getOperand(0).getReg() == StackPtr) { 1101 NumBytes += PI->getOperand(2).getImmedValue(); 1102 MBB.erase(PI); 1103 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 1104 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 1105 PI->getOperand(0).getReg() == StackPtr) { 1106 NumBytes -= PI->getOperand(2).getImmedValue(); 1107 MBB.erase(PI); 1108 } 1109 } 1110 1111 if (NumBytes > 0) { 1112 unsigned Opc = (NumBytes < 128) ? 1113 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : 1114 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); 1115 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes); 1116 } else if ((int)NumBytes < 0) { 1117 unsigned Opc = (-NumBytes < 128) ? 1118 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : 1119 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); 1120 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes); 1121 } 1122 } 1123 } 1124} 1125 1126unsigned X86RegisterInfo::getRARegister() const { 1127 return X86::ST0; // use a non-register register 1128} 1129 1130unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { 1131 return hasFP(MF) ? FramePtr : StackPtr; 1132} 1133 1134namespace llvm { 1135unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { 1136 switch (VT) { 1137 default: return Reg; 1138 case MVT::i8: 1139 if (High) { 1140 switch (Reg) { 1141 default: return 0; 1142 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1143 return X86::AH; 1144 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1145 return X86::DH; 1146 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1147 return X86::CH; 1148 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1149 return X86::BH; 1150 } 1151 } else { 1152 switch (Reg) { 1153 default: return 0; 1154 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1155 return X86::AL; 1156 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1157 return X86::DL; 1158 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1159 return X86::CL; 1160 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1161 return X86::BL; 1162 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1163 return X86::SIL; 1164 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1165 return X86::DIL; 1166 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1167 return X86::BPL; 1168 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1169 return X86::SPL; 1170 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1171 return X86::R8B; 1172 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1173 return X86::R9B; 1174 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1175 return X86::R10B; 1176 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1177 return X86::R11B; 1178 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1179 return X86::R12B; 1180 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1181 return X86::R13B; 1182 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1183 return X86::R14B; 1184 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1185 return X86::R15B; 1186 } 1187 } 1188 case MVT::i16: 1189 switch (Reg) { 1190 default: return Reg; 1191 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1192 return X86::AX; 1193 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1194 return X86::DX; 1195 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1196 return X86::CX; 1197 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1198 return X86::BX; 1199 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1200 return X86::SI; 1201 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1202 return X86::DI; 1203 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1204 return X86::BP; 1205 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1206 return X86::SP; 1207 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1208 return X86::R8W; 1209 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1210 return X86::R9W; 1211 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1212 return X86::R10W; 1213 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1214 return X86::R11W; 1215 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1216 return X86::R12W; 1217 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1218 return X86::R13W; 1219 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1220 return X86::R14W; 1221 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1222 return X86::R15W; 1223 } 1224 case MVT::i32: 1225 switch (Reg) { 1226 default: return Reg; 1227 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1228 return X86::EAX; 1229 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1230 return X86::EDX; 1231 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1232 return X86::ECX; 1233 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1234 return X86::EBX; 1235 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1236 return X86::ESI; 1237 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1238 return X86::EDI; 1239 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1240 return X86::EBP; 1241 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1242 return X86::ESP; 1243 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1244 return X86::R8D; 1245 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1246 return X86::R9D; 1247 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1248 return X86::R10D; 1249 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1250 return X86::R11D; 1251 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1252 return X86::R12D; 1253 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1254 return X86::R13D; 1255 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1256 return X86::R14D; 1257 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1258 return X86::R15D; 1259 } 1260 case MVT::i64: 1261 switch (Reg) { 1262 default: return Reg; 1263 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 1264 return X86::RAX; 1265 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 1266 return X86::RDX; 1267 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 1268 return X86::RCX; 1269 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 1270 return X86::RBX; 1271 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 1272 return X86::RSI; 1273 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 1274 return X86::RDI; 1275 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 1276 return X86::RBP; 1277 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 1278 return X86::RSP; 1279 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 1280 return X86::R8; 1281 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 1282 return X86::R9; 1283 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 1284 return X86::R10; 1285 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 1286 return X86::R11; 1287 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 1288 return X86::R12; 1289 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 1290 return X86::R13; 1291 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 1292 return X86::R14; 1293 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 1294 return X86::R15; 1295 } 1296 } 1297 1298 return Reg; 1299} 1300} 1301 1302#include "X86GenRegisterInfo.inc" 1303 1304