X86RegisterInfo.cpp revision aa09b75d2257545c4583265c7ce10f2d0e3be72b 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3// This file contains the X86 implementation of the MRegisterInfo class.  This
4// file is responsible for the frame pointer elimination optimization on X86.
5//
6//===----------------------------------------------------------------------===//
7
8#include "X86.h"
9#include "X86RegisterInfo.h"
10#include "X86InstrBuilder.h"
11#include "llvm/Constants.h"
12#include "llvm/Type.h"
13#include "llvm/CodeGen/MachineInstrBuilder.h"
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineFrameInfo.h"
16#include "Support/CommandLine.h"
17
18namespace {
19  cl::opt<bool>
20  NoFPElim("no-fp-elim",
21	   cl::desc("Disable frame pointer elimination optimization"));
22}
23
24static unsigned getIdx(const TargetRegisterClass *RC) {
25  switch (RC->getSize()) {
26  default: assert(0 && "Invalid data size!");
27  case 1:  return 0;
28  case 2:  return 1;
29  case 4:  return 2;
30  case 10: return 3;
31  }
32}
33
34void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
35					  MachineBasicBlock::iterator &MBBI,
36					  unsigned SrcReg, int FrameIdx,
37					  const TargetRegisterClass *RC) const {
38  static const unsigned Opcode[] =
39    { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
40  MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
41				       FrameIdx).addReg(SrcReg);
42  MBBI = MBB.insert(MBBI, MI)+1;
43}
44
45void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
46					   MachineBasicBlock::iterator &MBBI,
47					   unsigned DestReg, int FrameIdx,
48					   const TargetRegisterClass *RC) const{
49  static const unsigned Opcode[] =
50    { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
51  MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
52				       FrameIdx);
53  MBBI = MBB.insert(MBBI, MI)+1;
54}
55
56void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
57				   MachineBasicBlock::iterator &MBBI,
58				   unsigned DestReg, unsigned SrcReg,
59				   const TargetRegisterClass *RC) const {
60  static const unsigned Opcode[] =
61    { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
62  MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
63  MBBI = MBB.insert(MBBI, MI)+1;
64}
65
66const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
67  static const unsigned CalleeSaveRegs[] = {
68    X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
69  };
70  return CalleeSaveRegs;
71}
72
73
74//===----------------------------------------------------------------------===//
75// Stack Frame Processing methods
76//===----------------------------------------------------------------------===//
77
78// hasFP - Return true if the specified function should have a dedicated frame
79// pointer register.  This is true if the function has variable sized allocas or
80// if frame pointer elimination is disabled.
81//
82static bool hasFP(MachineFunction &MF) {
83  return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
84}
85
86// hasSPAdjust - Return true if this function has ESP adjustment instructions in
87// the prolog and epilog which allocate local stack space.  This is neccesary
88// because we elide these instructions if there are no function calls in the
89// current function (ie, this is a leaf function).  In this case, we can refer
90// beyond the stack pointer because we know that nothing will trample on that
91// part of the stack.
92//
93static bool hasSPAdjust(MachineFunction &MF) {
94  assert(!hasFP(MF) && "Can only eliminate SP adjustment if no frame-pointer!");
95  return MF.getFrameInfo()->hasCalls();
96}
97
98void X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
99						    MachineBasicBlock &MBB,
100	                                 MachineBasicBlock::iterator &I) const {
101  MachineInstr *New = 0, *Old = *I;;
102  if (hasFP(MF)) {
103    // If we have a frame pointer, turn the adjcallstackup instruction into a
104    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
105    // <amt>'
106    unsigned Amount = Old->getOperand(0).getImmedValue();
107    if (Amount != 0) {
108      if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
109	New=BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
110      } else {
111	assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
112	New=BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
113      }
114    }
115  }
116
117  if (New)
118    *I = New;        // Replace the pseudo instruction with a new instruction...
119  else
120    I = MBB.erase(I);// Just delete the pseudo instruction...
121  delete Old;
122}
123
124void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
125					MachineBasicBlock::iterator &II) const {
126  unsigned i = 3;
127  MachineInstr &MI = **II;
128  while (!MI.getOperand(i).isFrameIndex()) {
129    ++i;
130    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
131  }
132
133  // This must be part of a four operand memory reference.  Replace the
134  // FrameIndex with the offset and the base register with EBP.
135  MI.SetMachineOperandReg(i-3, hasFP(MF) ? X86::EBP : X86::ESP);
136
137  // Now replace the frame index itself with the offset from EBP.
138  int FrameIndex = MI.getOperand(i).getFrameIndex();
139  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
140
141  if (!hasFP(MF) && hasSPAdjust(MF)) {
142    const MachineFrameInfo *MFI = MF.getFrameInfo();
143    Offset += MFI->getStackSize() + MFI->getMaxCallFrameSize();
144  }
145
146  MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
147}
148
149void X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
150  const {
151  if (hasFP(MF)) {
152    // Create a frame entry for the EBP register that must be saved.
153    int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
154    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexEnd()-1 &&
155	   "Slot for EBP register must be last in order to be found!");
156  }
157}
158
159void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
160  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
161  MachineBasicBlock::iterator MBBI = MBB.begin();
162  const MachineFrameInfo *MFI = MF.getFrameInfo();
163  MachineInstr *MI;
164
165  // Get the number of bytes to allocate from the FrameInfo
166  unsigned NumBytes = MFI->getStackSize();
167  if (hasFP(MF)) {
168    // Get the offset of the stack slot for the EBP register... which is
169    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
170    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1);
171
172    MI = addRegOffset(BuildMI(X86::MOVrm32, 5),    // mov [ESP-<offset>], EBP
173		      X86::ESP, EBPOffset).addReg(X86::EBP);
174    MBBI = MBB.insert(MBBI, MI)+1;
175
176    MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
177    MBBI = MBB.insert(MBBI, MI)+1;
178  } else {
179    // If we don't have a frame pointer, and the function contains no call sites
180    // (it's a leaf function), we don't have to emit ANY stack adjustment
181    // instructions at all, we can just refer to the area beyond the stack
182    // pointer.  This can be important for small functions.
183    //
184    if (!hasSPAdjust(MF)) return;
185
186    // When we have no frame pointer, we reserve argument space for call sites
187    // in the function immediately on entry to the current function.  This
188    // eliminates the need for add/sub ESP brackets around call sites.
189    //
190    NumBytes += MFI->getMaxCallFrameSize();
191  }
192
193  if (NumBytes) {
194    // adjust stack pointer: ESP -= numbytes
195    MI  = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
196    MBBI = 1+MBB.insert(MBBI, MI);
197  }
198}
199
200void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
201				   MachineBasicBlock &MBB) const {
202  const MachineFrameInfo *MFI = MF.getFrameInfo();
203  MachineBasicBlock::iterator MBBI = MBB.end()-1;
204  MachineInstr *MI;
205  assert((*MBBI)->getOpcode() == X86::RET &&
206         "Can only insert epilog into returning blocks");
207
208  if (hasFP(MF)) {
209    // Get the offset of the stack slot for the EBP register... which is
210    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
211    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1);
212
213    // mov ESP, EBP
214    MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
215    MBBI = 1+MBB.insert(MBBI, MI);
216
217    // mov EBP, [ESP-<offset>]
218    MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
219    MBBI = 1+MBB.insert(MBBI, MI);
220  } else {
221    if (!hasSPAdjust(MF)) return;
222
223    // Get the number of bytes allocated from the FrameInfo...
224    unsigned NumBytes = MFI->getStackSize();
225    NumBytes += MFI->getMaxCallFrameSize();
226
227    if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
228      MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
229      MBBI = 1+MBB.insert(MBBI, MI);
230    }
231  }
232}
233
234
235//===----------------------------------------------------------------------===//
236// Register Class Implementation Code
237//===----------------------------------------------------------------------===//
238
239//===----------------------------------------------------------------------===//
240//   8 Bit Integer Registers
241//
242namespace {
243  const unsigned ByteRegClassRegs[] = {
244    X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
245  };
246
247  TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
248 ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
249
250//===----------------------------------------------------------------------===//
251//   16 Bit Integer Registers
252//
253  const unsigned ShortRegClassRegs[] = {
254    X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
255  };
256
257  struct R16CL : public TargetRegisterClass {
258    R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
259    iterator allocation_order_end(MachineFunction &MF)   const {
260      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
261	return end()-2;  // Don't allocate SP or BP
262      else
263	return end()-1;  // Don't allocate SP
264    }
265  } X86ShortRegisterClassInstance;
266
267//===----------------------------------------------------------------------===//
268//   32 Bit Integer Registers
269//
270  const unsigned IntRegClassRegs[] = {
271    X86::EAX, X86::ECX, X86::EDX, X86::EBX,
272    X86::ESI, X86::EDI, X86::EBP, X86::ESP
273  };
274
275  struct R32CL : public TargetRegisterClass {
276    R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
277    iterator allocation_order_end(MachineFunction &MF)   const {
278      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
279	return end()-2;  // Don't allocate ESP or EBP
280      else
281	return end()-1;  // Don't allocate ESP
282    }
283  } X86IntRegisterClassInstance;
284
285//===----------------------------------------------------------------------===//
286//   Pseudo Floating Point Registers
287//
288  const unsigned PFPRegClassRegs[] = {
289#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
290#include "X86RegisterInfo.def"
291  };
292
293  TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
294      PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
295
296//===----------------------------------------------------------------------===//
297// Register class array...
298//
299  const TargetRegisterClass * const X86RegClasses[] = {
300    &X86ByteRegisterClassInstance,
301    &X86ShortRegisterClassInstance,
302    &X86IntRegisterClassInstance,
303    &X86FPRegisterClassInstance,
304  };
305}
306
307
308// Create static lists to contain register alias sets...
309#define ALIASLIST(NAME, ...) \
310  static const unsigned NAME[] = { __VA_ARGS__ };
311#include "X86RegisterInfo.def"
312
313
314// X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
315// descriptors
316//
317static const MRegisterDesc X86Regs[] = {
318#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
319         { NAME, ALIAS_SET, FLAGS, TSFLAGS },
320#include "X86RegisterInfo.def"
321};
322
323X86RegisterInfo::X86RegisterInfo()
324  : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
325                  X86RegClasses,
326                  X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
327		  X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
328}
329
330
331
332const TargetRegisterClass*
333X86RegisterInfo::getRegClassForType(const Type* Ty) const {
334  switch (Ty->getPrimitiveID()) {
335  default:                assert(0 && "Invalid type to getClass!");
336  case Type::BoolTyID:
337  case Type::SByteTyID:
338  case Type::UByteTyID:   return &X86ByteRegisterClassInstance;
339  case Type::ShortTyID:
340  case Type::UShortTyID:  return &X86ShortRegisterClassInstance;
341  case Type::LongTyID:    // FIXME: Longs are not handled yet!
342  case Type::ULongTyID:   // FIXME: Treat these like ints, this is bogus!
343
344  case Type::IntTyID:
345  case Type::UIntTyID:
346  case Type::PointerTyID: return &X86IntRegisterClassInstance;
347
348  case Type::FloatTyID:
349  case Type::DoubleTyID: return &X86FPRegisterClassInstance;
350  }
351}
352