X86RegisterInfo.cpp revision d293e0d2dcd3dc4e6030e9644846ed4d0b1bbde3 
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86.h"
17#include "X86RegisterInfo.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/Constants.h"
23#include "llvm/Function.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/Target/TargetAsmInfo.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40#include "llvm/Support/Compiler.h"
41using namespace llvm;
42
43X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44                                 const TargetInstrInfo &tii)
45  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46                         X86::ADJCALLSTACKDOWN64 :
47                         X86::ADJCALLSTACKDOWN32,
48                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
49                         X86::ADJCALLSTACKUP64 :
50                         X86::ADJCALLSTACKUP32),
51    TM(tm), TII(tii) {
52  // Cache some information.
53  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54  Is64Bit = Subtarget->is64Bit();
55  IsWin64 = Subtarget->isTargetWin64();
56  StackAlign = TM.getFrameInfo()->getStackAlignment();
57  if (Is64Bit) {
58    SlotSize = 8;
59    StackPtr = X86::RSP;
60    FramePtr = X86::RBP;
61  } else {
62    SlotSize = 4;
63    StackPtr = X86::ESP;
64    FramePtr = X86::EBP;
65  }
66}
67
68// getDwarfRegNum - This function maps LLVM register identifiers to the
69// Dwarf specific numbering, used in debug info and exception tables.
70
71int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73  unsigned Flavour = DWARFFlavour::X86_64;
74  if (!Subtarget->is64Bit()) {
75    if (Subtarget->isTargetDarwin()) {
76      if (isEH)
77        Flavour = DWARFFlavour::X86_32_DarwinEH;
78      else
79        Flavour = DWARFFlavour::X86_32_Generic;
80    } else if (Subtarget->isTargetCygMing()) {
81      // Unsupported by now, just quick fallback
82      Flavour = DWARFFlavour::X86_32_Generic;
83    } else {
84      Flavour = DWARFFlavour::X86_32_Generic;
85    }
86  }
87
88  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
89}
90
91// getX86RegNum - This function maps LLVM register identifiers to their X86
92// specific numbering, which is used in various places encoding instructions.
93//
94unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
95  switch(RegNo) {
96  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
101    return N86::ESP;
102  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
103    return N86::EBP;
104  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
105    return N86::ESI;
106  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
107    return N86::EDI;
108
109  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
110    return N86::EAX;
111  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
112    return N86::ECX;
113  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
114    return N86::EDX;
115  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
116    return N86::EBX;
117  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
118    return N86::ESP;
119  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
120    return N86::EBP;
121  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
122    return N86::ESI;
123  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
124    return N86::EDI;
125
126  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128    return RegNo-X86::ST0;
129
130  case X86::XMM0: case X86::XMM8: case X86::MM0:
131    return 0;
132  case X86::XMM1: case X86::XMM9: case X86::MM1:
133    return 1;
134  case X86::XMM2: case X86::XMM10: case X86::MM2:
135    return 2;
136  case X86::XMM3: case X86::XMM11: case X86::MM3:
137    return 3;
138  case X86::XMM4: case X86::XMM12: case X86::MM4:
139    return 4;
140  case X86::XMM5: case X86::XMM13: case X86::MM5:
141    return 5;
142  case X86::XMM6: case X86::XMM14: case X86::MM6:
143    return 6;
144  case X86::XMM7: case X86::XMM15: case X86::MM7:
145    return 7;
146
147  default:
148    assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
150    return 0;
151  }
152}
153
154const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
155  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
156  if (Subtarget->is64Bit())
157    return &X86::GR64RegClass;
158  else
159    return &X86::GR32RegClass;
160}
161
162const TargetRegisterClass *
163X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
164  if (RC == &X86::CCRRegClass) {
165    if (Is64Bit)
166      return &X86::GR64RegClass;
167    else
168      return &X86::GR32RegClass;
169  }
170  return NULL;
171}
172
173const unsigned *
174X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
175  bool callsEHReturn = false;
176
177  if (MF) {
178    const MachineFrameInfo *MFI = MF->getFrameInfo();
179    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
180    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
181  }
182
183  static const unsigned CalleeSavedRegs32Bit[] = {
184    X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
185  };
186
187  static const unsigned CalleeSavedRegs32EHRet[] = {
188    X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
189  };
190
191  static const unsigned CalleeSavedRegs64Bit[] = {
192    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
193  };
194
195  static const unsigned CalleeSavedRegs64EHRet[] = {
196    X86::RAX, X86::RDX, X86::RBX, X86::R12,
197    X86::R13, X86::R14, X86::R15, X86::RBP, 0
198  };
199
200  static const unsigned CalleeSavedRegsWin64[] = {
201    X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
202    X86::R12,   X86::R13,   X86::R14,   X86::R15,
203    X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
204    X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
205    X86::XMM14, X86::XMM15, 0
206  };
207
208  if (Is64Bit) {
209    if (IsWin64)
210      return CalleeSavedRegsWin64;
211    else
212      return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
213  } else {
214    return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
215  }
216}
217
218const TargetRegisterClass* const*
219X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
220  bool callsEHReturn = false;
221
222  if (MF) {
223    const MachineFrameInfo *MFI = MF->getFrameInfo();
224    const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225    callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
226  }
227
228  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
229    &X86::GR32RegClass, &X86::GR32RegClass,
230    &X86::GR32RegClass, &X86::GR32RegClass,  0
231  };
232  static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
233    &X86::GR32RegClass, &X86::GR32RegClass,
234    &X86::GR32RegClass, &X86::GR32RegClass,
235    &X86::GR32RegClass, &X86::GR32RegClass,  0
236  };
237  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
238    &X86::GR64RegClass, &X86::GR64RegClass,
239    &X86::GR64RegClass, &X86::GR64RegClass,
240    &X86::GR64RegClass, &X86::GR64RegClass, 0
241  };
242  static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
243    &X86::GR64RegClass, &X86::GR64RegClass,
244    &X86::GR64RegClass, &X86::GR64RegClass,
245    &X86::GR64RegClass, &X86::GR64RegClass,
246    &X86::GR64RegClass, &X86::GR64RegClass, 0
247  };
248  static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
249    &X86::GR64RegClass,  &X86::GR64RegClass,
250    &X86::GR64RegClass,  &X86::GR64RegClass,
251    &X86::GR64RegClass,  &X86::GR64RegClass,
252    &X86::GR64RegClass,  &X86::GR64RegClass,
253    &X86::VR128RegClass, &X86::VR128RegClass,
254    &X86::VR128RegClass, &X86::VR128RegClass,
255    &X86::VR128RegClass, &X86::VR128RegClass,
256    &X86::VR128RegClass, &X86::VR128RegClass,
257    &X86::VR128RegClass, &X86::VR128RegClass, 0
258  };
259
260  if (Is64Bit) {
261    if (IsWin64)
262      return CalleeSavedRegClassesWin64;
263    else
264      return (callsEHReturn ?
265              CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
266  } else {
267    return (callsEHReturn ?
268            CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
269  }
270}
271
272BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273  BitVector Reserved(getNumRegs());
274  // Set the stack-pointer register and its aliases as reserved.
275  Reserved.set(X86::RSP);
276  Reserved.set(X86::ESP);
277  Reserved.set(X86::SP);
278  Reserved.set(X86::SPL);
279  // Set the frame-pointer register and its aliases as reserved if needed.
280  if (hasFP(MF)) {
281    Reserved.set(X86::RBP);
282    Reserved.set(X86::EBP);
283    Reserved.set(X86::BP);
284    Reserved.set(X86::BPL);
285  }
286  // Mark the x87 stack registers as reserved, since they don't
287  // behave normally with respect to liveness. We don't fully
288  // model the effects of x87 stack pushes and pops after
289  // stackification.
290  Reserved.set(X86::ST0);
291  Reserved.set(X86::ST1);
292  Reserved.set(X86::ST2);
293  Reserved.set(X86::ST3);
294  Reserved.set(X86::ST4);
295  Reserved.set(X86::ST5);
296  Reserved.set(X86::ST6);
297  Reserved.set(X86::ST7);
298  return Reserved;
299}
300
301//===----------------------------------------------------------------------===//
302// Stack Frame Processing methods
303//===----------------------------------------------------------------------===//
304
305static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
306  unsigned MaxAlign = 0;
307  for (int i = FFI->getObjectIndexBegin(),
308         e = FFI->getObjectIndexEnd(); i != e; ++i) {
309    if (FFI->isDeadObjectIndex(i))
310      continue;
311    unsigned Align = FFI->getObjectAlignment(i);
312    MaxAlign = std::max(MaxAlign, Align);
313  }
314
315  return MaxAlign;
316}
317
318// hasFP - Return true if the specified function should have a dedicated frame
319// pointer register.  This is true if the function has variable sized allocas or
320// if frame pointer elimination is disabled.
321//
322bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
323  const MachineFrameInfo *MFI = MF.getFrameInfo();
324  const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
325
326  return (NoFramePointerElim ||
327          needsStackRealignment(MF) ||
328          MFI->hasVarSizedObjects() ||
329          MFI->isFrameAddressTaken() ||
330          MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
331          (MMI && MMI->callsUnwindInit()));
332}
333
334bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
335  const MachineFrameInfo *MFI = MF.getFrameInfo();;
336
337  // FIXME: Currently we don't support stack realignment for functions with
338  // variable-sized allocas
339  return (RealignStack &&
340          (MFI->getMaxAlignment() > StackAlign &&
341           !MFI->hasVarSizedObjects()));
342}
343
344bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
345  return !MF.getFrameInfo()->hasVarSizedObjects();
346}
347
348int
349X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
350  int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
351  uint64_t StackSize = MF.getFrameInfo()->getStackSize();
352
353  if (needsStackRealignment(MF)) {
354    if (FI < 0)
355      // Skip the saved EBP
356      Offset += SlotSize;
357    else {
358      unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
359      assert( (-(Offset + StackSize)) % Align == 0);
360      Align = 0;
361      return Offset + StackSize;
362    }
363
364    // FIXME: Support tail calls
365  } else {
366    if (!hasFP(MF))
367      return Offset + StackSize;
368
369    // Skip the saved EBP
370    Offset += SlotSize;
371
372    // Skip the RETADDR move area
373    X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
374    int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
375    if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
376  }
377
378  return Offset;
379}
380
381void X86RegisterInfo::
382eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
383                              MachineBasicBlock::iterator I) const {
384  if (!hasReservedCallFrame(MF)) {
385    // If the stack pointer can be changed after prologue, turn the
386    // adjcallstackup instruction into a 'sub ESP, <amt>' and the
387    // adjcallstackdown instruction into 'add ESP, <amt>'
388    // TODO: consider using push / pop instead of sub + store / add
389    MachineInstr *Old = I;
390    uint64_t Amount = Old->getOperand(0).getImm();
391    if (Amount != 0) {
392      // We need to keep the stack aligned properly.  To do this, we round the
393      // amount of space needed for the outgoing arguments up to the next
394      // alignment boundary.
395      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
396
397      MachineInstr *New = 0;
398      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
399        New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
400                      StackPtr).addReg(StackPtr).addImm(Amount);
401      } else {
402        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
403        // factor out the amount the callee already popped.
404        uint64_t CalleeAmt = Old->getOperand(1).getImm();
405        Amount -= CalleeAmt;
406        if (Amount) {
407          unsigned Opc = (Amount < 128) ?
408            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
409            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
410          New = BuildMI(MF, TII.get(Opc), StackPtr)
411            .addReg(StackPtr).addImm(Amount);
412        }
413      }
414
415      if (New) {
416        // The EFLAGS implicit def is dead.
417        New->getOperand(3).setIsDead();
418
419        // Replace the pseudo instruction with a new instruction...
420        MBB.insert(I, New);
421      }
422    }
423  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
424    // If we are performing frame pointer elimination and if the callee pops
425    // something off the stack pointer, add it back.  We do this until we have
426    // more advanced stack pointer tracking ability.
427    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
428      unsigned Opc = (CalleeAmt < 128) ?
429        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
430        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
431      MachineInstr *New =
432        BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
433      // The EFLAGS implicit def is dead.
434      New->getOperand(3).setIsDead();
435
436      MBB.insert(I, New);
437    }
438  }
439
440  MBB.erase(I);
441}
442
443void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
444                                          int SPAdj, RegScavenger *RS) const{
445  assert(SPAdj == 0 && "Unexpected");
446
447  unsigned i = 0;
448  MachineInstr &MI = *II;
449  MachineFunction &MF = *MI.getParent()->getParent();
450  while (!MI.getOperand(i).isFI()) {
451    ++i;
452    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
453  }
454
455  int FrameIndex = MI.getOperand(i).getIndex();
456
457  unsigned BasePtr;
458  if (needsStackRealignment(MF))
459    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
460  else
461    BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
462
463  // This must be part of a four operand memory reference.  Replace the
464  // FrameIndex with base register with EBP.  Add an offset to the offset.
465  MI.getOperand(i).ChangeToRegister(BasePtr, false);
466
467  // Now add the frame object offset to the offset from EBP.
468  if (MI.getOperand(i+3).isImm()) {
469    // Offset is a 32-bit integer.
470    int Offset = getFrameIndexOffset(MF, FrameIndex) +
471      (int)(MI.getOperand(i+3).getImm());
472
473     MI.getOperand(i+3).ChangeToImmediate(Offset);
474  } else {
475    // Offset is symbolic. This is extremely rare.
476    uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
477                      (uint64_t)MI.getOperand(i+3).getOffset();
478    MI.getOperand(i+3).setOffset(Offset);
479  }
480}
481
482void
483X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
484                                                      RegScavenger *RS) const {
485  MachineFrameInfo *FFI = MF.getFrameInfo();
486
487  // Calculate and set max stack object alignment early, so we can decide
488  // whether we will need stack realignment (and thus FP).
489  unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
490                               calculateMaxStackAlignment(FFI));
491
492  FFI->setMaxAlignment(MaxAlign);
493}
494
495void
496X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
497  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
498  int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
499  if (TailCallReturnAddrDelta < 0) {
500    // create RETURNADDR area
501    //   arg
502    //   arg
503    //   RETADDR
504    //   { ...
505    //     RETADDR area
506    //     ...
507    //   }
508    //   [EBP]
509    MF.getFrameInfo()->
510      CreateFixedObject(-TailCallReturnAddrDelta,
511                        (-1*SlotSize)+TailCallReturnAddrDelta);
512  }
513  if (hasFP(MF)) {
514    assert((TailCallReturnAddrDelta <= 0) &&
515           "The Delta should always be zero or negative");
516    // Create a frame entry for the EBP register that must be saved.
517    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
518                                                        (int)SlotSize * -2+
519                                                       TailCallReturnAddrDelta);
520    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
521           "Slot for EBP register must be last in order to be found!");
522    FrameIdx = 0;
523  }
524}
525
526/// emitSPUpdate - Emit a series of instructions to increment / decrement the
527/// stack pointer by a constant value.
528static
529void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
530                  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
531                  const TargetInstrInfo &TII) {
532  bool isSub = NumBytes < 0;
533  uint64_t Offset = isSub ? -NumBytes : NumBytes;
534  unsigned Opc = isSub
535    ? ((Offset < 128) ?
536       (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
537       (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
538    : ((Offset < 128) ?
539       (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
540       (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
541  uint64_t Chunk = (1LL << 31) - 1;
542
543  while (Offset) {
544    uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
545    MachineInstr *MI =
546      BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
547    // The EFLAGS implicit def is dead.
548    MI->getOperand(3).setIsDead();
549    Offset -= ThisVal;
550  }
551}
552
553// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
554static
555void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
556                      unsigned StackPtr, uint64_t *NumBytes = NULL) {
557  if (MBBI == MBB.begin()) return;
558
559  MachineBasicBlock::iterator PI = prior(MBBI);
560  unsigned Opc = PI->getOpcode();
561  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
562       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
563      PI->getOperand(0).getReg() == StackPtr) {
564    if (NumBytes)
565      *NumBytes += PI->getOperand(2).getImm();
566    MBB.erase(PI);
567  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
568              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
569             PI->getOperand(0).getReg() == StackPtr) {
570    if (NumBytes)
571      *NumBytes -= PI->getOperand(2).getImm();
572    MBB.erase(PI);
573  }
574}
575
576// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
577static
578void mergeSPUpdatesDown(MachineBasicBlock &MBB,
579                        MachineBasicBlock::iterator &MBBI,
580                        unsigned StackPtr, uint64_t *NumBytes = NULL) {
581  return;
582
583  if (MBBI == MBB.end()) return;
584
585  MachineBasicBlock::iterator NI = next(MBBI);
586  if (NI == MBB.end()) return;
587
588  unsigned Opc = NI->getOpcode();
589  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
590       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
591      NI->getOperand(0).getReg() == StackPtr) {
592    if (NumBytes)
593      *NumBytes -= NI->getOperand(2).getImm();
594    MBB.erase(NI);
595    MBBI = NI;
596  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
597              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
598             NI->getOperand(0).getReg() == StackPtr) {
599    if (NumBytes)
600      *NumBytes += NI->getOperand(2).getImm();
601    MBB.erase(NI);
602    MBBI = NI;
603  }
604}
605
606/// mergeSPUpdates - Checks the instruction before/after the passed
607/// instruction. If it is an ADD/SUB instruction it is deleted
608/// argument and the stack adjustment is returned as a positive value for ADD
609/// and a negative for SUB.
610static int mergeSPUpdates(MachineBasicBlock &MBB,
611                           MachineBasicBlock::iterator &MBBI,
612                           unsigned StackPtr,
613                           bool doMergeWithPrevious) {
614
615  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
616      (!doMergeWithPrevious && MBBI == MBB.end()))
617    return 0;
618
619  int Offset = 0;
620
621  MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
622  MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
623  unsigned Opc = PI->getOpcode();
624  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
625       Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
626      PI->getOperand(0).getReg() == StackPtr){
627    Offset += PI->getOperand(2).getImm();
628    MBB.erase(PI);
629    if (!doMergeWithPrevious) MBBI = NI;
630  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
631              Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
632             PI->getOperand(0).getReg() == StackPtr) {
633    Offset -= PI->getOperand(2).getImm();
634    MBB.erase(PI);
635    if (!doMergeWithPrevious) MBBI = NI;
636  }
637
638  return Offset;
639}
640
641void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
642                                     unsigned FrameLabelId,
643                                     unsigned ReadyLabelId) const {
644  MachineFrameInfo *MFI = MF.getFrameInfo();
645  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
646  if (!MMI)
647    return;
648
649  uint64_t StackSize = MFI->getStackSize();
650  std::vector<MachineMove> &Moves = MMI->getFrameMoves();
651  const TargetData *TD = MF.getTarget().getTargetData();
652
653  // Calculate amount of bytes used for return address storing
654  int stackGrowth =
655    (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
656     TargetFrameInfo::StackGrowsUp ?
657     TD->getPointerSize() : -TD->getPointerSize());
658
659  if (StackSize) {
660    // Show update of SP.
661    if (hasFP(MF)) {
662      // Adjust SP
663      MachineLocation SPDst(MachineLocation::VirtualFP);
664      MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
665      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
666    } else {
667      MachineLocation SPDst(MachineLocation::VirtualFP);
668      MachineLocation SPSrc(MachineLocation::VirtualFP,
669                            -StackSize+stackGrowth);
670      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
671    }
672  } else {
673    //FIXME: Verify & implement for FP
674    MachineLocation SPDst(StackPtr);
675    MachineLocation SPSrc(StackPtr, stackGrowth);
676    Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
677  }
678
679  // Add callee saved registers to move list.
680  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
681
682  // FIXME: This is dirty hack. The code itself is pretty mess right now.
683  // It should be rewritten from scratch and generalized sometimes.
684
685  // Determine maximum offset (minumum due to stack growth)
686  int64_t MaxOffset = 0;
687  for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
688    MaxOffset = std::min(MaxOffset,
689                         MFI->getObjectOffset(CSI[I].getFrameIdx()));
690
691  // Calculate offsets
692  int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
693  for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
694    int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
695    unsigned Reg = CSI[I].getReg();
696    Offset = (MaxOffset-Offset+saveAreaOffset);
697    MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
698    MachineLocation CSSrc(Reg);
699    Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
700  }
701
702  if (hasFP(MF)) {
703    // Save FP
704    MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
705    MachineLocation FPSrc(FramePtr);
706    Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
707  }
708
709  MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
710  MachineLocation FPSrc(MachineLocation::VirtualFP);
711  Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
712}
713
714
715void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
716  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
717  MachineFrameInfo *MFI = MF.getFrameInfo();
718  const Function* Fn = MF.getFunction();
719  const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
720  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
721  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
722  MachineBasicBlock::iterator MBBI = MBB.begin();
723  bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
724                          !Fn->doesNotThrow() ||
725                          UnwindTablesMandatory;
726  // Prepare for frame info.
727  unsigned FrameLabelId = 0;
728
729  // Get the number of bytes to allocate from the FrameInfo.
730  uint64_t StackSize = MFI->getStackSize();
731  // Get desired stack alignment
732  uint64_t MaxAlign  = MFI->getMaxAlignment();
733
734  // Add RETADDR move area to callee saved frame size.
735  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
736  if (TailCallReturnAddrDelta < 0)
737    X86FI->setCalleeSavedFrameSize(
738          X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
739
740  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
741  // function, and use up to 128 bytes of stack space, don't have a frame
742  // pointer, calls, or dynamic alloca then we do not need to adjust the
743  // stack pointer (we fit in the Red Zone).
744  if (Is64Bit && !DisableRedZone &&
745      !needsStackRealignment(MF) &&
746      !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
747      !MFI->hasCalls()) {                          // No calls.
748    uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
749    if (hasFP(MF)) MinSize += SlotSize;
750    StackSize = std::max(MinSize,
751                         StackSize > 128 ? StackSize - 128 : 0);
752    MFI->setStackSize(StackSize);
753  }
754
755  // Insert stack pointer adjustment for later moving of return addr.  Only
756  // applies to tail call optimized functions where the callee argument stack
757  // size is bigger than the callers.
758  if (TailCallReturnAddrDelta < 0) {
759    MachineInstr *MI =
760      BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
761              StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
762    // The EFLAGS implicit def is dead.
763    MI->getOperand(3).setIsDead();
764  }
765
766  uint64_t NumBytes = 0;
767  if (hasFP(MF)) {
768    // Calculate required stack adjustment
769    uint64_t FrameSize = StackSize - SlotSize;
770    if (needsStackRealignment(MF))
771      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
772
773    NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
774
775    // Get the offset of the stack slot for the EBP register... which is
776    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
777    // Update the frame offset adjustment.
778    MFI->setOffsetAdjustment(-NumBytes);
779
780    // Save EBP into the appropriate stack slot...
781    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
782      .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
783
784    if (needsFrameMoves) {
785      // Mark effective beginning of when frame pointer becomes valid.
786      FrameLabelId = MMI->NextLabelID();
787      BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
788    }
789
790    // Update EBP with the new base value...
791    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
792      .addReg(StackPtr);
793
794    // Mark the FramePtr as live-in in every block except the entry.
795    for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
796         I != E; ++I)
797      I->addLiveIn(FramePtr);
798
799    // Realign stack
800    if (needsStackRealignment(MF)) {
801      MachineInstr *MI =
802        BuildMI(MBB, MBBI,
803                TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
804                StackPtr).addReg(StackPtr).addImm(-MaxAlign);
805      // The EFLAGS implicit def is dead.
806      MI->getOperand(3).setIsDead();
807    }
808  } else
809    NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
810
811  unsigned ReadyLabelId = 0;
812  if (needsFrameMoves) {
813    // Mark effective beginning of when frame pointer is ready.
814    ReadyLabelId = MMI->NextLabelID();
815    BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
816  }
817
818  // Skip the callee-saved push instructions.
819  while (MBBI != MBB.end() &&
820         (MBBI->getOpcode() == X86::PUSH32r ||
821          MBBI->getOpcode() == X86::PUSH64r))
822    ++MBBI;
823
824  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
825    if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
826      // Check, whether EAX is livein for this function
827      bool isEAXAlive = false;
828      for (MachineRegisterInfo::livein_iterator
829           II = MF.getRegInfo().livein_begin(),
830           EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
831        unsigned Reg = II->first;
832        isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
833                      Reg == X86::AH || Reg == X86::AL);
834      }
835
836      // Function prologue calls _alloca to probe the stack when allocating
837      // more than 4k bytes in one go. Touching the stack at 4K increments is
838      // necessary to ensure that the guard pages used by the OS virtual memory
839      // manager are allocated in correct sequence.
840      if (!isEAXAlive) {
841        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
842        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
843          .addExternalSymbol("_alloca");
844      } else {
845        // Save EAX
846        BuildMI(MBB, MBBI, TII.get(X86::PUSH32r))
847          .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
848        // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
849        // allocated bytes for EAX.
850        BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
851        BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
852          .addExternalSymbol("_alloca");
853        // Restore EAX
854        MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
855                                        StackPtr, false, NumBytes-4);
856        MBB.insert(MBBI, MI);
857      }
858    } else {
859      // If there is an SUB32ri of ESP immediately before this instruction,
860      // merge the two. This can be the case when tail call elimination is
861      // enabled and the callee has more arguments then the caller.
862      NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
863      // If there is an ADD32ri or SUB32ri of ESP immediately after this
864      // instruction, merge the two instructions.
865      mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
866
867      if (NumBytes)
868        emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
869    }
870  }
871
872  if (needsFrameMoves)
873    emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
874}
875
876void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
877                                   MachineBasicBlock &MBB) const {
878  const MachineFrameInfo *MFI = MF.getFrameInfo();
879  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
880  MachineBasicBlock::iterator MBBI = prior(MBB.end());
881  unsigned RetOpcode = MBBI->getOpcode();
882
883  switch (RetOpcode) {
884  case X86::RET:
885  case X86::RETI:
886  case X86::TCRETURNdi:
887  case X86::TCRETURNri:
888  case X86::TCRETURNri64:
889  case X86::TCRETURNdi64:
890  case X86::EH_RETURN:
891  case X86::EH_RETURN64:
892  case X86::TAILJMPd:
893  case X86::TAILJMPr:
894  case X86::TAILJMPm: break;  // These are ok
895  default:
896    assert(0 && "Can only insert epilog into returning blocks");
897  }
898
899  // Get the number of bytes to allocate from the FrameInfo
900  uint64_t StackSize = MFI->getStackSize();
901  uint64_t MaxAlign  = MFI->getMaxAlignment();
902  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
903  uint64_t NumBytes = 0;
904
905  if (hasFP(MF)) {
906    // Calculate required stack adjustment
907    uint64_t FrameSize = StackSize - SlotSize;
908    if (needsStackRealignment(MF))
909      FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
910
911    NumBytes = FrameSize - CSSize;
912
913    // pop EBP.
914    BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
915  } else
916    NumBytes = StackSize - CSSize;
917
918  // Skip the callee-saved pop instructions.
919  MachineBasicBlock::iterator LastCSPop = MBBI;
920  while (MBBI != MBB.begin()) {
921    MachineBasicBlock::iterator PI = prior(MBBI);
922    unsigned Opc = PI->getOpcode();
923    if (Opc != X86::POP32r && Opc != X86::POP64r &&
924        !PI->getDesc().isTerminator())
925      break;
926    --MBBI;
927  }
928
929  // If there is an ADD32ri or SUB32ri of ESP immediately before this
930  // instruction, merge the two instructions.
931  if (NumBytes || MFI->hasVarSizedObjects())
932    mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
933
934  // If dynamic alloca is used, then reset esp to point to the last callee-saved
935  // slot before popping them off! Same applies for the case, when stack was
936  // realigned
937  if (needsStackRealignment(MF)) {
938    // We cannot use LEA here, because stack pointer was realigned. We need to
939    // deallocate local frame back
940    if (CSSize) {
941      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
942      MBBI = prior(LastCSPop);
943    }
944
945    BuildMI(MBB, MBBI,
946            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
947            StackPtr).addReg(FramePtr);
948  } else if (MFI->hasVarSizedObjects()) {
949    if (CSSize) {
950      unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
951      MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
952                                      FramePtr, false, -CSSize);
953      MBB.insert(MBBI, MI);
954    } else
955      BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
956              StackPtr).addReg(FramePtr);
957
958  } else {
959    // adjust stack pointer back: ESP += numbytes
960    if (NumBytes)
961      emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
962  }
963
964  // We're returning from function via eh_return.
965  if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
966    MBBI = prior(MBB.end());
967    MachineOperand &DestAddr  = MBBI->getOperand(0);
968    assert(DestAddr.isReg() && "Offset should be in register!");
969    BuildMI(MBB, MBBI,
970            TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
971            StackPtr).addReg(DestAddr.getReg());
972  // Tail call return: adjust the stack pointer and jump to callee
973  } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
974             RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
975    MBBI = prior(MBB.end());
976    MachineOperand &JumpTarget = MBBI->getOperand(0);
977    MachineOperand &StackAdjust = MBBI->getOperand(1);
978    assert(StackAdjust.isImm() && "Expecting immediate value.");
979
980    // Adjust stack pointer.
981    int StackAdj = StackAdjust.getImm();
982    int MaxTCDelta = X86FI->getTCReturnAddrDelta();
983    int Offset = 0;
984    assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
985    // Incoporate the retaddr area.
986    Offset = StackAdj-MaxTCDelta;
987    assert(Offset >= 0 && "Offset should never be negative");
988    if (Offset) {
989      // Check for possible merge with preceeding ADD instruction.
990      Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
991      emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
992    }
993    // Jump to label or value in register.
994    if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
995      BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
996        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
997    else if (RetOpcode== X86::TCRETURNri64) {
998      BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
999    } else
1000       BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1001    // Delete the pseudo instruction TCRETURN.
1002    MBB.erase(MBBI);
1003  } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1004             (X86FI->getTCReturnAddrDelta() < 0)) {
1005    // Add the return addr area delta back since we are not tail calling.
1006    int delta = -1*X86FI->getTCReturnAddrDelta();
1007    MBBI = prior(MBB.end());
1008    // Check for possible merge with preceeding ADD instruction.
1009    delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1010    emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1011  }
1012}
1013
1014unsigned X86RegisterInfo::getRARegister() const {
1015  if (Is64Bit)
1016    return X86::RIP;  // Should have dwarf #16
1017  else
1018    return X86::EIP;  // Should have dwarf #8
1019}
1020
1021unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1022  return hasFP(MF) ? FramePtr : StackPtr;
1023}
1024
1025void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1026                                                                         const {
1027  // Calculate amount of bytes used for return address storing
1028  int stackGrowth = (Is64Bit ? -8 : -4);
1029
1030  // Initial state of the frame pointer is esp+4.
1031  MachineLocation Dst(MachineLocation::VirtualFP);
1032  MachineLocation Src(StackPtr, stackGrowth);
1033  Moves.push_back(MachineMove(0, Dst, Src));
1034
1035  // Add return address to move list
1036  MachineLocation CSDst(StackPtr, stackGrowth);
1037  MachineLocation CSSrc(getRARegister());
1038  Moves.push_back(MachineMove(0, CSDst, CSSrc));
1039}
1040
1041unsigned X86RegisterInfo::getEHExceptionRegister() const {
1042  assert(0 && "What is the exception register");
1043  return 0;
1044}
1045
1046unsigned X86RegisterInfo::getEHHandlerRegister() const {
1047  assert(0 && "What is the exception handler register");
1048  return 0;
1049}
1050
1051namespace llvm {
1052unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1053  switch (VT.getSimpleVT()) {
1054  default: return Reg;
1055  case MVT::i8:
1056    if (High) {
1057      switch (Reg) {
1058      default: return 0;
1059      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1060        return X86::AH;
1061      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1062        return X86::DH;
1063      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1064        return X86::CH;
1065      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1066        return X86::BH;
1067      }
1068    } else {
1069      switch (Reg) {
1070      default: return 0;
1071      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1072        return X86::AL;
1073      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1074        return X86::DL;
1075      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1076        return X86::CL;
1077      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1078        return X86::BL;
1079      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1080        return X86::SIL;
1081      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1082        return X86::DIL;
1083      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1084        return X86::BPL;
1085      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1086        return X86::SPL;
1087      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1088        return X86::R8B;
1089      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1090        return X86::R9B;
1091      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1092        return X86::R10B;
1093      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1094        return X86::R11B;
1095      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1096        return X86::R12B;
1097      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1098        return X86::R13B;
1099      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1100        return X86::R14B;
1101      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1102        return X86::R15B;
1103      }
1104    }
1105  case MVT::i16:
1106    switch (Reg) {
1107    default: return Reg;
1108    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1109      return X86::AX;
1110    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1111      return X86::DX;
1112    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1113      return X86::CX;
1114    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1115      return X86::BX;
1116    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1117      return X86::SI;
1118    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1119      return X86::DI;
1120    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1121      return X86::BP;
1122    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1123      return X86::SP;
1124    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1125      return X86::R8W;
1126    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1127      return X86::R9W;
1128    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1129      return X86::R10W;
1130    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1131      return X86::R11W;
1132    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1133      return X86::R12W;
1134    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1135      return X86::R13W;
1136    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1137      return X86::R14W;
1138    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1139      return X86::R15W;
1140    }
1141  case MVT::i32:
1142    switch (Reg) {
1143    default: return Reg;
1144    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1145      return X86::EAX;
1146    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1147      return X86::EDX;
1148    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1149      return X86::ECX;
1150    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1151      return X86::EBX;
1152    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1153      return X86::ESI;
1154    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1155      return X86::EDI;
1156    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1157      return X86::EBP;
1158    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1159      return X86::ESP;
1160    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1161      return X86::R8D;
1162    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1163      return X86::R9D;
1164    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1165      return X86::R10D;
1166    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1167      return X86::R11D;
1168    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1169      return X86::R12D;
1170    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1171      return X86::R13D;
1172    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1173      return X86::R14D;
1174    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1175      return X86::R15D;
1176    }
1177  case MVT::i64:
1178    switch (Reg) {
1179    default: return Reg;
1180    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1181      return X86::RAX;
1182    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1183      return X86::RDX;
1184    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1185      return X86::RCX;
1186    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1187      return X86::RBX;
1188    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1189      return X86::RSI;
1190    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1191      return X86::RDI;
1192    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1193      return X86::RBP;
1194    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1195      return X86::RSP;
1196    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1197      return X86::R8;
1198    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1199      return X86::R9;
1200    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1201      return X86::R10;
1202    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1203      return X86::R11;
1204    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1205      return X86::R12;
1206    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1207      return X86::R13;
1208    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1209      return X86::R14;
1210    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1211      return X86::R15;
1212    }
1213  }
1214
1215  return Reg;
1216}
1217}
1218
1219#include "X86GenRegisterInfo.inc"
1220
1221namespace {
1222  struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1223    static char ID;
1224    MSAC() : MachineFunctionPass(&ID) {}
1225
1226    virtual bool runOnMachineFunction(MachineFunction &MF) {
1227      MachineFrameInfo *FFI = MF.getFrameInfo();
1228      MachineRegisterInfo &RI = MF.getRegInfo();
1229
1230      // Calculate max stack alignment of all already allocated stack objects.
1231      unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1232
1233      // Be over-conservative: scan over all vreg defs and find, whether vector
1234      // registers are used. If yes - there is probability, that vector register
1235      // will be spilled and thus stack needs to be aligned properly.
1236      for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1237           RegNum < RI.getLastVirtReg(); ++RegNum)
1238        MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1239
1240      FFI->setMaxAlignment(MaxAlign);
1241
1242      return false;
1243    }
1244
1245    virtual const char *getPassName() const {
1246      return "X86 Maximal Stack Alignment Calculator";
1247    }
1248  };
1249
1250  char MSAC::ID = 0;
1251}
1252
1253FunctionPass*
1254llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }
1255