X86RegisterInfo.cpp revision f463f51161fe65da93ec573f19d2d32353be4116
1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the MRegisterInfo class. This 11// file is responsible for the frame pointer elimination optimization on X86. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86RegisterInfo.h" 17#include "X86InstrBuilder.h" 18#include "llvm/Constants.h" 19#include "llvm/Type.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineLocation.h" 25#include "llvm/Target/TargetFrameInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetOptions.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/ADT/STLExtras.h" 30#include <iostream> 31 32using namespace llvm; 33 34namespace { 35 cl::opt<bool> 36 NoFusing("disable-spill-fusing", 37 cl::desc("Disable fusing of spill code into instructions")); 38 cl::opt<bool> 39 PrintFailedFusing("print-failed-fuse-candidates", 40 cl::desc("Print instructions that the allocator wants to" 41 " fuse, but the X86 backend currently can't"), 42 cl::Hidden); 43} 44 45X86RegisterInfo::X86RegisterInfo() 46 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {} 47 48void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 49 MachineBasicBlock::iterator MI, 50 unsigned SrcReg, int FrameIdx, 51 const TargetRegisterClass *RC) const { 52 unsigned Opc; 53 if (RC == &X86::R32RegClass) { 54 Opc = X86::MOV32mr; 55 } else if (RC == &X86::R8RegClass) { 56 Opc = X86::MOV8mr; 57 } else if (RC == &X86::R16RegClass) { 58 Opc = X86::MOV16mr; 59 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 60 Opc = X86::FpST64m; 61 } else if (RC == &X86::FR32RegClass) { 62 Opc = X86::MOVSSmr; 63 } else if (RC == &X86::FR64RegClass) { 64 Opc = X86::MOVSDmr; 65 } else if (RC == &X86::VR128RegClass) { 66 Opc = X86::MOVAPDmr; 67 } else { 68 assert(0 && "Unknown regclass"); 69 abort(); 70 } 71 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg); 72} 73 74void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MI, 76 unsigned DestReg, int FrameIdx, 77 const TargetRegisterClass *RC) const{ 78 unsigned Opc; 79 if (RC == &X86::R32RegClass) { 80 Opc = X86::MOV32rm; 81 } else if (RC == &X86::R8RegClass) { 82 Opc = X86::MOV8rm; 83 } else if (RC == &X86::R16RegClass) { 84 Opc = X86::MOV16rm; 85 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 86 Opc = X86::FpLD64m; 87 } else if (RC == &X86::FR32RegClass) { 88 Opc = X86::MOVSSrm; 89 } else if (RC == &X86::FR64RegClass) { 90 Opc = X86::MOVSDrm; 91 } else if (RC == &X86::VR128RegClass) { 92 Opc = X86::MOVAPDrm; 93 } else { 94 assert(0 && "Unknown regclass"); 95 abort(); 96 } 97 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx); 98} 99 100void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 101 MachineBasicBlock::iterator MI, 102 unsigned DestReg, unsigned SrcReg, 103 const TargetRegisterClass *RC) const { 104 unsigned Opc; 105 if (RC == &X86::R32RegClass) { 106 Opc = X86::MOV32rr; 107 } else if (RC == &X86::R8RegClass) { 108 Opc = X86::MOV8rr; 109 } else if (RC == &X86::R16RegClass) { 110 Opc = X86::MOV16rr; 111 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { 112 Opc = X86::FpMOV; 113 } else if (RC == &X86::FR32RegClass) { 114 Opc = X86::FsMOVAPSrr; 115 } else if (RC == &X86::FR64RegClass) { 116 Opc = X86::FsMOVAPDrr; 117 } else if (RC == &X86::VR128RegClass) { 118 Opc = X86::MOVAPSrr; 119 } else { 120 assert(0 && "Unknown regclass"); 121 abort(); 122 } 123 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg); 124} 125 126 127static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex, 128 MachineInstr *MI) { 129 return addFrameReference(BuildMI(Opcode, 4), FrameIndex); 130} 131 132static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex, 133 MachineInstr *MI) { 134 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 135 .addReg(MI->getOperand(1).getReg()); 136} 137 138static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex, 139 MachineInstr *MI) { 140 return addFrameReference(BuildMI(Opcode, 6), FrameIndex) 141 .addReg(MI->getOperand(1).getReg()) 142 .addZImm(MI->getOperand(2).getImmedValue()); 143} 144 145static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex, 146 MachineInstr *MI) { 147 if (MI->getOperand(1).isImmediate()) 148 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 149 .addZImm(MI->getOperand(1).getImmedValue()); 150 else if (MI->getOperand(1).isGlobalAddress()) 151 return addFrameReference(BuildMI(Opcode, 5), FrameIndex) 152 .addGlobalAddress(MI->getOperand(1).getGlobal(), 153 false, MI->getOperand(1).getOffset()); 154 assert(0 && "Unknown operand for MakeMI!"); 155 return 0; 156} 157 158static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex, 159 MachineInstr *MI) { 160 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0); 161} 162 163static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex, 164 MachineInstr *MI) { 165 const MachineOperand& op = MI->getOperand(0); 166 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()), 167 FrameIndex); 168} 169 170static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex, 171 MachineInstr *MI) { 172 const MachineOperand& op = MI->getOperand(0); 173 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()), 174 FrameIndex).addZImm(MI->getOperand(2).getImmedValue()); 175} 176 177 178MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI, 179 unsigned i, 180 int FrameIndex) const { 181 if (NoFusing) return NULL; 182 183 /// FIXME: This should obviously be autogenerated by tablegen when patterns 184 /// are available! 185 MachineBasicBlock& MBB = *MI->getParent(); 186 if (i == 0) { 187 switch(MI->getOpcode()) { 188 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI); 189 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI); 190 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI); 191 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI); 192 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI); 193 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI); 194 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI); 195 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI); 196 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI); 197 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI); 198 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI); 199 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI); 200 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI); 201 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI); 202 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI); 203 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI); 204 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI); 205 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI); 206 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI); 207 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI); 208 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI); 209 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI); 210 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI); 211 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI); 212 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI); 213 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI); 214 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI); 215 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI); 216 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI); 217 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI); 218 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI); 219 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI); 220 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI); 221 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI); 222 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI); 223 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI); 224 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI); 225 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI); 226 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI); 227 case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI); 228 case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI); 229 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); 230 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); 231 case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI); 232 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI); 233 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI); 234 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI); 235 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI); 236 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI); 237 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI); 238 case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI); 239 case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI); 240 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); 241 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); 242 case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI); 243 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI); 244 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI); 245 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI); 246 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI); 247 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI); 248 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI); 249 case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI); 250 case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI); 251 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI); 252 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI); 253 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI); 254 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI); 255 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI); 256 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI); 257 case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI); 258 case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI); 259 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI); 260 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI); 261 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI); 262 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI); 263 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI); 264 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI); 265 case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI); 266 case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI); 267 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI); 268 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI); 269 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI); 270 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI); 271 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI); 272 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI); 273 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI); 274 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI); 275 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI); 276 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI); 277 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI); 278 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI); 279 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI); 280 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI); 281 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI); 282 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI); 283 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI); 284 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI); 285 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI); 286 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI); 287 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI); 288 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI); 289 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI); 290 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI); 291 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI); 292 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI); 293 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI); 294 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI); 295 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI); 296 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI); 297 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI); 298 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI); 299 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI); 300 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI); 301 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI); 302 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI); 303 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI); 304 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI); 305 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI); 306 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI); 307 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI); 308 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI); 309 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI); 310 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI); 311 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI); 312 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI); 313 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI); 314 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI); 315 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI); 316 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI); 317 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI); 318 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI); 319 // Alias instructions 320 case X86::MOV8r0: return MakeM0Inst(X86::MOV8mi, FrameIndex, MI); 321 case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI); 322 case X86::MOV32r0: return MakeM0Inst(X86::MOV32mi, FrameIndex, MI); 323 // Alias scalar SSE instructions 324 case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); 325 case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); 326 // Scalar SSE instructions 327 case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); 328 case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); 329 // Packed SSE instructions 330 case X86::MOVAPSrr: return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI); 331 case X86::MOVAPDrr: return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI); 332 case X86::MOVUPSrr: return MakeMRInst(X86::MOVUPSmr, FrameIndex, MI); 333 case X86::MOVUPDrr: return MakeMRInst(X86::MOVUPDmr, FrameIndex, MI); 334 // Alias packed SSE instructions 335 case X86::MOVPS2SSrr:return MakeMRInst(X86::MOVPS2SSmr, FrameIndex, MI); 336 case X86::MOVPDI2DIrr:return MakeMRInst(X86::MOVPDI2DImr, FrameIndex, MI); 337 } 338 } else if (i == 1) { 339 switch(MI->getOpcode()) { 340 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI); 341 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI); 342 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI); 343 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI); 344 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI); 345 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI); 346 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI); 347 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI); 348 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI); 349 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI); 350 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI); 351 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI); 352 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI); 353 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI); 354 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI); 355 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI); 356 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI); 357 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI); 358 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI); 359 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI); 360 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI); 361 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI); 362 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI); 363 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI); 364 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI); 365 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI); 366 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI); 367 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI); 368 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI); 369 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI); 370 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI); 371 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI); 372 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI); 373 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI); 374 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI); 375 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI); 376 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI); 377 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI); 378 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI); 379 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI); 380 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI); 381 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI); 382 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI); 383 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI); 384 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI); 385 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI); 386 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI); 387 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI); 388 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI); 389 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI); 390 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI); 391 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI); 392 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); 393 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); 394 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI); 395 case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI); 396 case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI); 397 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI); 398 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI); 399 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI); 400 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI); 401 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI); 402 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI); 403 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI); 404 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI); 405 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI); 406 case X86::CMP8ri: return MakeRMInst(X86::CMP8mi , FrameIndex, MI); 407 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); 408 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); 409 case X86::CMP16ri8: return MakeMIInst(X86::CMP16mi8, FrameIndex, MI); 410 case X86::CMP32ri8: return MakeRMInst(X86::CMP32mi8, FrameIndex, MI); 411 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI); 412 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI); 413 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI); 414 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI); 415 case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI); 416 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI); 417 // Alias scalar SSE instructions 418 case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI); 419 case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI); 420 // Scalar SSE instructions 421 case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI); 422 case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI); 423 case X86::CVTSS2SIrr:return MakeRMInst(X86::CVTSS2SIrm, FrameIndex, MI); 424 case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI); 425 case X86::CVTSD2SIrr:return MakeRMInst(X86::CVTSD2SIrm, FrameIndex, MI); 426 case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI); 427 case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI); 428 case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI); 429 case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI); 430 case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI); 431 case X86::Int_CVTTSS2SIrr: 432 return MakeRMInst(X86::Int_CVTTSS2SIrm, FrameIndex, MI); 433 case X86::Int_CVTTSD2SIrr: 434 return MakeRMInst(X86::Int_CVTTSD2SIrm, FrameIndex, MI); 435 case X86::Int_CVTSI2SSrr: 436 return MakeRMInst(X86::Int_CVTSI2SSrm, FrameIndex, MI); 437 case X86::SQRTSSr: return MakeRMInst(X86::SQRTSSm, FrameIndex, MI); 438 case X86::SQRTSDr: return MakeRMInst(X86::SQRTSDm, FrameIndex, MI); 439 case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI); 440 case X86::ADDSDrr: return MakeRMInst(X86::ADDSDrm, FrameIndex, MI); 441 case X86::MULSSrr: return MakeRMInst(X86::MULSSrm, FrameIndex, MI); 442 case X86::MULSDrr: return MakeRMInst(X86::MULSDrm, FrameIndex, MI); 443 case X86::DIVSSrr: return MakeRMInst(X86::DIVSSrm, FrameIndex, MI); 444 case X86::DIVSDrr: return MakeRMInst(X86::DIVSDrm, FrameIndex, MI); 445 case X86::SUBSSrr: return MakeRMInst(X86::SUBSSrm, FrameIndex, MI); 446 case X86::SUBSDrr: return MakeRMInst(X86::SUBSDrm, FrameIndex, MI); 447 case X86::CMPSSrr: return MakeRMInst(X86::CMPSSrm, FrameIndex, MI); 448 case X86::CMPSDrr: return MakeRMInst(X86::CMPSDrm, FrameIndex, MI); 449 case X86::Int_CMPSSrr: return MakeRMInst(X86::Int_CMPSSrm, FrameIndex, MI); 450 case X86::Int_CMPSDrr: return MakeRMInst(X86::Int_CMPSDrm, FrameIndex, MI); 451 case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI); 452 case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI); 453 case X86::Int_UCOMISSrr: 454 return MakeRMInst(X86::Int_UCOMISSrm, FrameIndex, MI); 455 case X86::Int_UCOMISDrr: 456 return MakeRMInst(X86::Int_UCOMISDrm, FrameIndex, MI); 457 case X86::Int_COMISSrr: 458 return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI); 459 case X86::Int_COMISDrr: 460 return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI); 461 // Packed SSE instructions 462 case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI); 463 case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI); 464 case X86::MOVUPSrr: return MakeRMInst(X86::MOVUPSrm, FrameIndex, MI); 465 case X86::MOVUPDrr: return MakeRMInst(X86::MOVUPDrm, FrameIndex, MI); 466 case X86::MOVSHDUPrr:return MakeRMInst(X86::MOVSHDUPrm, FrameIndex, MI); 467 case X86::MOVSLDUPrr:return MakeRMInst(X86::MOVSLDUPrm, FrameIndex, MI); 468 case X86::MOVDDUPrr: return MakeRMInst(X86::MOVDDUPrm, FrameIndex, MI); 469 case X86::CVTDQ2PSrr:return MakeRMInst(X86::CVTDQ2PSrm, FrameIndex, MI); 470 case X86::CVTDQ2PDrr:return MakeRMInst(X86::CVTDQ2PDrm, FrameIndex, MI); 471 case X86::CVTPS2DQrr:return MakeRMInst(X86::CVTPS2DQrm, FrameIndex, MI); 472 case X86::CVTTPS2DQrr:return MakeRMInst(X86::CVTTPS2DQrm, FrameIndex, MI); 473 case X86::CVTPD2DQrr:return MakeRMInst(X86::CVTPD2DQrm, FrameIndex, MI); 474 case X86::CVTTPD2DQrr:return MakeRMInst(X86::CVTTPD2DQrm, FrameIndex, MI); 475 case X86::CVTPS2PDrr:return MakeRMInst(X86::CVTPS2PDrm, FrameIndex, MI); 476 case X86::CVTPD2PSrr:return MakeRMInst(X86::CVTPD2PSrm, FrameIndex, MI); 477 case X86::Int_CVTSI2SDrr: 478 return MakeRMInst(X86::Int_CVTSI2SDrm, FrameIndex, MI); 479 case X86::Int_CVTSD2SSrr: 480 return MakeRMInst(X86::Int_CVTSD2SSrm, FrameIndex, MI); 481 case X86::Int_CVTSS2SDrr: 482 return MakeRMInst(X86::Int_CVTSS2SDrm, FrameIndex, MI); 483 case X86::ADDPSrr: return MakeRMInst(X86::ADDPSrm, FrameIndex, MI); 484 case X86::ADDPDrr: return MakeRMInst(X86::ADDPDrm, FrameIndex, MI); 485 case X86::SUBPSrr: return MakeRMInst(X86::SUBPSrm, FrameIndex, MI); 486 case X86::SUBPDrr: return MakeRMInst(X86::SUBPDrm, FrameIndex, MI); 487 case X86::MULPSrr: return MakeRMInst(X86::MULPSrm, FrameIndex, MI); 488 case X86::MULPDrr: return MakeRMInst(X86::MULPDrm, FrameIndex, MI); 489 case X86::DIVPSrr: return MakeRMInst(X86::DIVPSrm, FrameIndex, MI); 490 case X86::DIVPDrr: return MakeRMInst(X86::DIVPDrm, FrameIndex, MI); 491 case X86::ADDSUBPSrr:return MakeRMInst(X86::ADDSUBPSrm, FrameIndex, MI); 492 case X86::ADDSUBPDrr:return MakeRMInst(X86::ADDSUBPDrm, FrameIndex, MI); 493 case X86::HADDPSrr: return MakeRMInst(X86::HADDPSrm, FrameIndex, MI); 494 case X86::HADDPDrr: return MakeRMInst(X86::HADDPDrm, FrameIndex, MI); 495 case X86::HSUBPSrr: return MakeRMInst(X86::HSUBPSrm, FrameIndex, MI); 496 case X86::HSUBPDrr: return MakeRMInst(X86::HSUBPDrm, FrameIndex, MI); 497 case X86::SQRTPSr: return MakeRMInst(X86::SQRTPSm, FrameIndex, MI); 498 case X86::SQRTPDr: return MakeRMInst(X86::SQRTPDm, FrameIndex, MI); 499 case X86::RSQRTPSr: return MakeRMInst(X86::RSQRTPSm, FrameIndex, MI); 500 case X86::RCPPSr: return MakeRMInst(X86::RCPPSm, FrameIndex, MI); 501 case X86::MAXPSrr: return MakeRMInst(X86::MAXPSrm, FrameIndex, MI); 502 case X86::MAXPDrr: return MakeRMInst(X86::MAXPDrm, FrameIndex, MI); 503 case X86::MINPSrr: return MakeRMInst(X86::MINPSrm, FrameIndex, MI); 504 case X86::MINPDrr: return MakeRMInst(X86::MINPDrm, FrameIndex, MI); 505 case X86::ANDPSrr: return MakeRMInst(X86::ANDPSrm, FrameIndex, MI); 506 case X86::ANDPDrr: return MakeRMInst(X86::ANDPDrm, FrameIndex, MI); 507 case X86::ORPSrr: return MakeRMInst(X86::ORPSrm, FrameIndex, MI); 508 case X86::ORPDrr: return MakeRMInst(X86::ORPDrm, FrameIndex, MI); 509 case X86::XORPSrr: return MakeRMInst(X86::XORPSrm, FrameIndex, MI); 510 case X86::XORPDrr: return MakeRMInst(X86::XORPDrm, FrameIndex, MI); 511 case X86::ANDNPSrr: return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI); 512 case X86::ANDNPDrr: return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI); 513 case X86::CMPPSrri: return MakeRMIInst(X86::CMPPSrmi, FrameIndex, MI); 514 case X86::CMPPDrri: return MakeRMIInst(X86::CMPPDrmi, FrameIndex, MI); 515 case X86::SHUFPSrri: return MakeRMIInst(X86::SHUFPSrmi, FrameIndex, MI); 516 case X86::SHUFPDrri: return MakeRMIInst(X86::SHUFPDrmi, FrameIndex, MI); 517 case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI); 518 case X86::UNPCKHPDrr:return MakeRMInst(X86::UNPCKHPDrm, FrameIndex, MI); 519 case X86::UNPCKLPSrr:return MakeRMInst(X86::UNPCKLPSrm, FrameIndex, MI); 520 case X86::UNPCKLPDrr:return MakeRMInst(X86::UNPCKLPDrm, FrameIndex, MI); 521 case X86::PADDBrr: return MakeRMInst(X86::PADDBrm, FrameIndex, MI); 522 case X86::PADDWrr: return MakeRMInst(X86::PADDWrm, FrameIndex, MI); 523 case X86::PADDDrr: return MakeRMInst(X86::PADDDrm, FrameIndex, MI); 524 case X86::PADDSBrr: return MakeRMInst(X86::PADDSBrm, FrameIndex, MI); 525 case X86::PADDSWrr: return MakeRMInst(X86::PADDSWrm, FrameIndex, MI); 526 case X86::PSUBBrr: return MakeRMInst(X86::PSUBBrm, FrameIndex, MI); 527 case X86::PSUBWrr: return MakeRMInst(X86::PSUBWrm, FrameIndex, MI); 528 case X86::PSUBDrr: return MakeRMInst(X86::PSUBDrm, FrameIndex, MI); 529 case X86::PSUBSBrr: return MakeRMInst(X86::PSUBSBrm, FrameIndex, MI); 530 case X86::PSUBSWrr: return MakeRMInst(X86::PSUBSWrm, FrameIndex, MI); 531 case X86::PMULHUWrr: return MakeRMInst(X86::PMULHUWrm, FrameIndex, MI); 532 case X86::PMULHWrr: return MakeRMInst(X86::PMULHWrm, FrameIndex, MI); 533 case X86::PMULLWrr: return MakeRMInst(X86::PMULLWrm, FrameIndex, MI); 534 case X86::PMULUDQrr: return MakeRMInst(X86::PMULUDQrm, FrameIndex, MI); 535 case X86::PMADDWDrr: return MakeRMInst(X86::PMADDWDrm, FrameIndex, MI); 536 case X86::PAVGBrr: return MakeRMInst(X86::PAVGBrm, FrameIndex, MI); 537 case X86::PAVGWrr: return MakeRMInst(X86::PAVGWrm, FrameIndex, MI); 538 case X86::PMAXUBrr: return MakeRMInst(X86::PMAXUBrm, FrameIndex, MI); 539 case X86::PMAXSWrr: return MakeRMInst(X86::PMAXSWrm, FrameIndex, MI); 540 case X86::PMINUBrr: return MakeRMInst(X86::PMINUBrm, FrameIndex, MI); 541 case X86::PMINSWrr: return MakeRMInst(X86::PMINSWrm, FrameIndex, MI); 542 case X86::PSADBWrr: return MakeRMInst(X86::PSADBWrm, FrameIndex, MI); 543 case X86::PSLLWrr: return MakeRMInst(X86::PSLLWrm, FrameIndex, MI); 544 case X86::PSLLDrr: return MakeRMInst(X86::PSLLDrm, FrameIndex, MI); 545 case X86::PSLLQrr: return MakeRMInst(X86::PSLLQrm, FrameIndex, MI); 546 case X86::PSRLWrr: return MakeRMInst(X86::PSRLWrm, FrameIndex, MI); 547 case X86::PSRLDrr: return MakeRMInst(X86::PSRLDrm, FrameIndex, MI); 548 case X86::PSRLQrr: return MakeRMInst(X86::PSRLQrm, FrameIndex, MI); 549 case X86::PSRAWrr: return MakeRMInst(X86::PSRAWrm, FrameIndex, MI); 550 case X86::PSRADrr: return MakeRMInst(X86::PSRADrm, FrameIndex, MI); 551 case X86::PANDrr: return MakeRMInst(X86::PANDrm, FrameIndex, MI); 552 case X86::PORrr: return MakeRMInst(X86::PORrm, FrameIndex, MI); 553 case X86::PXORrr: return MakeRMInst(X86::PXORrm, FrameIndex, MI); 554 case X86::PANDNrr: return MakeRMInst(X86::PANDNrm, FrameIndex, MI); 555 case X86::PCMPEQBrr: return MakeRMInst(X86::PCMPEQBrm, FrameIndex, MI); 556 case X86::PCMPEQWrr: return MakeRMInst(X86::PCMPEQWrm, FrameIndex, MI); 557 case X86::PCMPEQDrr: return MakeRMInst(X86::PCMPEQDrm, FrameIndex, MI); 558 case X86::PCMPGTBrr: return MakeRMInst(X86::PCMPGTBrm, FrameIndex, MI); 559 case X86::PCMPGTWrr: return MakeRMInst(X86::PCMPGTWrm, FrameIndex, MI); 560 case X86::PCMPGTDrr: return MakeRMInst(X86::PCMPGTDrm, FrameIndex, MI); 561 case X86::PACKSSWBrr:return MakeRMInst(X86::PACKSSWBrm, FrameIndex, MI); 562 case X86::PACKSSDWrr:return MakeRMInst(X86::PACKSSDWrm, FrameIndex, MI); 563 case X86::PACKUSWBrr:return MakeRMInst(X86::PACKUSWBrm, FrameIndex, MI); 564 case X86::PSHUFDri: return MakeRMIInst(X86::PSHUFDmi, FrameIndex, MI); 565 case X86::PSHUFHWri: return MakeRMIInst(X86::PSHUFHWmi, FrameIndex, MI); 566 case X86::PSHUFLWri: return MakeRMIInst(X86::PSHUFLWmi, FrameIndex, MI); 567 case X86::PUNPCKLBWrr:return MakeRMInst(X86::PUNPCKLBWrm, FrameIndex, MI); 568 case X86::PUNPCKLWDrr:return MakeRMInst(X86::PUNPCKLWDrm, FrameIndex, MI); 569 case X86::PUNPCKLDQrr:return MakeRMInst(X86::PUNPCKLDQrm, FrameIndex, MI); 570 case X86::PUNPCKLQDQrr:return MakeRMInst(X86::PUNPCKLQDQrm, FrameIndex, MI); 571 case X86::PUNPCKHBWrr:return MakeRMInst(X86::PUNPCKHBWrm, FrameIndex, MI); 572 case X86::PUNPCKHWDrr:return MakeRMInst(X86::PUNPCKHWDrm, FrameIndex, MI); 573 case X86::PUNPCKHDQrr:return MakeRMInst(X86::PUNPCKHDQrm, FrameIndex, MI); 574 case X86::PUNPCKHQDQrr:return MakeRMInst(X86::PUNPCKHQDQrm, FrameIndex, MI); 575 case X86::PEXTRWri: return MakeRMInst(X86::PEXTRWmi, FrameIndex, MI); 576 case X86::PINSRWrri: return MakeRMInst(X86::PINSRWrmi, FrameIndex, MI); 577 // Alias packed SSE instructions 578 case X86::MOVSS2PSrr:return MakeRMInst(X86::MOVSS2PSrm, FrameIndex, MI); 579 case X86::MOVSD2PDrr:return MakeRMInst(X86::MOVSD2PDrm, FrameIndex, MI); 580 case X86::MOVDI2PDIrr:return MakeRMInst(X86::MOVDI2PDIrm, FrameIndex, MI); 581 case X86::MOVQI2PQIrr:return MakeRMInst(X86::MOVQI2PQIrm, FrameIndex, MI); 582 } 583 } 584 if (PrintFailedFusing) 585 std::cerr << "We failed to fuse (" 586 << ((i == 1) ? "r" : "s") << "): " << *MI; 587 return NULL; 588} 589 590//===----------------------------------------------------------------------===// 591// Stack Frame Processing methods 592//===----------------------------------------------------------------------===// 593 594// hasFP - Return true if the specified function should have a dedicated frame 595// pointer register. This is true if the function has variable sized allocas or 596// if frame pointer elimination is disabled. 597// 598static bool hasFP(MachineFunction &MF) { 599 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 600} 601 602void X86RegisterInfo:: 603eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 604 MachineBasicBlock::iterator I) const { 605 if (hasFP(MF)) { 606 // If we have a frame pointer, turn the adjcallstackup instruction into a 607 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP, 608 // <amt>' 609 MachineInstr *Old = I; 610 unsigned Amount = Old->getOperand(0).getImmedValue(); 611 if (Amount != 0) { 612 // We need to keep the stack aligned properly. To do this, we round the 613 // amount of space needed for the outgoing arguments up to the next 614 // alignment boundary. 615 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 616 Amount = (Amount+Align-1)/Align*Align; 617 618 MachineInstr *New = 0; 619 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { 620 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) 621 .addZImm(Amount); 622 } else { 623 assert(Old->getOpcode() == X86::ADJCALLSTACKUP); 624 // factor out the amount the callee already popped. 625 unsigned CalleeAmt = Old->getOperand(1).getImmedValue(); 626 Amount -= CalleeAmt; 627 if (Amount) { 628 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri; 629 New = BuildMI(Opc, 1, X86::ESP, 630 MachineOperand::UseAndDef).addZImm(Amount); 631 } 632 } 633 634 // Replace the pseudo instruction with a new instruction... 635 if (New) MBB.insert(I, New); 636 } 637 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { 638 // If we are performing frame pointer elimination and if the callee pops 639 // something off the stack pointer, add it back. We do this until we have 640 // more advanced stack pointer tracking ability. 641 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) { 642 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri; 643 MachineInstr *New = 644 BuildMI(Opc, 1, X86::ESP, 645 MachineOperand::UseAndDef).addZImm(CalleeAmt); 646 MBB.insert(I, New); 647 } 648 } 649 650 MBB.erase(I); 651} 652 653void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 654 unsigned i = 0; 655 MachineInstr &MI = *II; 656 MachineFunction &MF = *MI.getParent()->getParent(); 657 while (!MI.getOperand(i).isFrameIndex()) { 658 ++i; 659 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 660 } 661 662 int FrameIndex = MI.getOperand(i).getFrameIndex(); 663 664 // This must be part of a four operand memory reference. Replace the 665 // FrameIndex with base register with EBP. Add add an offset to the offset. 666 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP); 667 668 // Now add the frame object offset to the offset from EBP. 669 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 670 MI.getOperand(i+3).getImmedValue()+4; 671 672 if (!hasFP(MF)) 673 Offset += MF.getFrameInfo()->getStackSize(); 674 else 675 Offset += 4; // Skip the saved EBP 676 677 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset); 678} 679 680void 681X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ 682 if (hasFP(MF)) { 683 // Create a frame entry for the EBP register that must be saved. 684 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8); 685 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 686 "Slot for EBP register must be last in order to be found!"); 687 } 688} 689 690void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { 691 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 692 MachineBasicBlock::iterator MBBI = MBB.begin(); 693 MachineFrameInfo *MFI = MF.getFrameInfo(); 694 MachineInstr *MI; 695 696 // Get the number of bytes to allocate from the FrameInfo 697 unsigned NumBytes = MFI->getStackSize(); 698 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) { 699 // When we have no frame pointer, we reserve argument space for call sites 700 // in the function immediately on entry to the current function. This 701 // eliminates the need for add/sub ESP brackets around call sites. 702 // 703 if (!hasFP(MF)) 704 NumBytes += MFI->getMaxCallFrameSize(); 705 706 // Round the size to a multiple of the alignment (don't forget the 4 byte 707 // offset though). 708 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 709 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4; 710 } 711 712 // Update frame info to pretend that this is part of the stack... 713 MFI->setStackSize(NumBytes); 714 715 if (NumBytes) { // adjust stack pointer: ESP -= numbytes 716 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; 717 MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes); 718 MBB.insert(MBBI, MI); 719 } 720 721 if (hasFP(MF)) { 722 // Get the offset of the stack slot for the EBP register... which is 723 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 724 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4; 725 726 // Save EBP into the appropriate stack slot... 727 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP 728 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); 729 MBB.insert(MBBI, MI); 730 731 // Update EBP with the new base value... 732 if (NumBytes == 4) // mov EBP, ESP 733 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP); 734 else // lea EBP, [ESP+StackSize] 735 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4); 736 737 MBB.insert(MBBI, MI); 738 } 739} 740 741void X86RegisterInfo::emitEpilogue(MachineFunction &MF, 742 MachineBasicBlock &MBB) const { 743 const MachineFrameInfo *MFI = MF.getFrameInfo(); 744 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 745 746 switch (MBBI->getOpcode()) { 747 case X86::RET: 748 case X86::RETI: 749 case X86::TAILJMPd: 750 case X86::TAILJMPr: 751 case X86::TAILJMPm: break; // These are ok 752 default: 753 assert(0 && "Can only insert epilog into returning blocks"); 754 } 755 756 if (hasFP(MF)) { 757 // Get the offset of the stack slot for the EBP register... which is 758 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 759 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4; 760 761 // mov ESP, EBP 762 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP); 763 764 // pop EBP 765 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP); 766 } else { 767 // Get the number of bytes allocated from the FrameInfo... 768 unsigned NumBytes = MFI->getStackSize(); 769 770 if (NumBytes) { // adjust stack pointer back: ESP += numbytes 771 // If there is an ADD32ri or SUB32ri of ESP immediately before this 772 // instruction, merge the two instructions. 773 if (MBBI != MBB.begin()) { 774 MachineBasicBlock::iterator PI = prior(MBBI); 775 if ((PI->getOpcode() == X86::ADD32ri || 776 PI->getOpcode() == X86::ADD32ri8) && 777 PI->getOperand(0).getReg() == X86::ESP) { 778 NumBytes += PI->getOperand(1).getImmedValue(); 779 MBB.erase(PI); 780 } else if ((PI->getOpcode() == X86::SUB32ri || 781 PI->getOpcode() == X86::SUB32ri8) && 782 PI->getOperand(0).getReg() == X86::ESP) { 783 NumBytes -= PI->getOperand(1).getImmedValue(); 784 MBB.erase(PI); 785 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) { 786 NumBytes += PI->getOperand(1).getImmedValue(); 787 MBB.erase(PI); 788 } 789 } 790 791 if (NumBytes > 0) { 792 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri; 793 BuildMI(MBB, MBBI, Opc, 2) 794 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes); 795 } else if ((int)NumBytes < 0) { 796 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; 797 BuildMI(MBB, MBBI, Opc, 2) 798 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes); 799 } 800 } 801 } 802} 803 804unsigned X86RegisterInfo::getRARegister() const { 805 return X86::ST0; // use a non-register register 806} 807 808unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { 809 return hasFP(MF) ? X86::EBP : X86::ESP; 810} 811 812#include "X86GenRegisterInfo.inc" 813 814