Lines Matching refs:BrCond
101 /// BrCond - Conditions for end of block conditional branches.
119 SmallVector<MachineOperand, 4> BrCond;
430 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
432 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
492 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
627 BBI.BrCond.clear();
629 !TII->AnalyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
632 if (BBI.BrCond.size()) {
719 if (BBI.BrCond.size()) {
725 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
755 if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
784 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
801 FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
819 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
834 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
842 FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
1023 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1096 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1154 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
1155 CvtBBI->BrCond.end());
1227 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1230 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;