Lines Matching refs:SRL
874 else if (Opc == ISD::SRL)
1115 case ISD::SRL: return visitSRL(N);
1194 case ISD::SRL:
1876 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1879 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1880 AddToWorkList(SRL.getNode());
1930 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2088 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2124 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2207 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2237 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2321 // For each of OP in SHL/SRL/SRA/AND...
2325 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2732 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2756 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2758 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2797 // Make sure everything beyond the low halfword is zero since the SRL 16
2807 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2820 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2843 if (N0.getOpcode() != ISD::SRL)
2865 } else { // Opc == ISD::SRL
2951 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3106 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3435 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3554 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3568 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3669 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3702 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3727 // If the sign bit is known to be zero, switch this to a SRL.
3729 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3750 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3766 if (N1C && N0.getOpcode() == ISD::SRL &&
3772 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3778 N0.getOperand(0).getOpcode() == ISD::SRL &&
3791 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3813 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3815 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3827 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3848 // could be set on input to the CTLZ node. If this bit is set, the SRL
3849 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3850 // to an SRL/XOR pair, which is likely to simplify more.
3855 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3915 // However when after the source operand of SRL is optimized into AND, the SRL
4697 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4904 case ISD::SRL:
4917 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4946 } else if (Opc == ISD::SRL) {
4947 // Another special-case: SRL is basically zero-extending a narrower value.
4966 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5112 if (N0.getOpcode() == ISD::SRL) {
5115 // We can turn this into an SRA iff the input to the SRL is already sign
5424 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
6130 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6133 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6156 // SRL constant is equal to the log2 of the AND constant. The back-end is
6186 // Replace the uses of SRL with SETCC
6815 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
8307 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8424 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8433 return DAG.getNode(ISD::SRL, DL, XType,
8440 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,