Lines Matching refs:VT
86 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
90 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
178 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
181 unsigned NumMaskElts = VT.getVectorNumElements();
251 EVT VT = CFP->getValueType(0);
254 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
256 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
259 EVT OrigVT = VT;
260 EVT SVT = VT;
270 VT = SVT;
282 VT, false, false, Alignment);
301 EVT VT = Val.getValueType();
306 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
384 // Get the half-size VT
393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
422 EVT VT = LD->getValueType(0);
425 if (VT.isFloatingPoint() || VT.isVector()) {
435 if (VT.isFloatingPoint() && LoadedVT != VT)
436 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
496 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
507 // Compute the new VT that is half the size of the old one. This is an
525 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
530 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
549 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
550 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
576 EVT VT = Tmp1.getValueType();
577 EVT EltVT = VT.getVectorElementType();
580 SDValue StackPtr = DAG.CreateStackTemporary(VT);
600 return DAG.getLoad(VT, dl, Ch, StackPtr,
913 EVT VT = Node->getValueType(0);
917 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
940 assert(VT.isVector() && "Cannot promote this load!");
942 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
947 Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
1191 EVT VT = Tmp3.getValueType();
1192 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1211 assert(VT.isVector() && "Unknown legal promote case!");
1213 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1413 EVT VT = Node->getValueType(0);
1414 EVT EltVT = VT.getVectorElementType();
1416 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1455 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1526 EVT VT = Node->getValueType(0);
1537 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1542 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1543 DAG.getConstant(-(uint64_t)Align, VT));
1544 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1557 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1588 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1589 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1590 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1671 EVT VT = Node->getValueType(0);
1673 EVT EltVT = VT.getVectorElementType();
1700 return DAG.getUNDEF(VT);
1703 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1733 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1748 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1751 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1753 Vec2 = DAG.getUNDEF(VT);
1756 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2292 EVT VT = Op.getValueType();
2293 EVT SHVT = TLI.getShiftAmountTy(VT);
2295 switch (VT.getSimpleVT().SimpleTy) {
2298 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2299 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2300 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2302 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2303 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2304 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2305 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2306 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2307 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2308 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2309 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2310 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2312 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2313 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2314 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2315 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2316 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2317 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2318 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2319 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2320 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2321 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2322 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2323 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2324 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2325 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2326 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2327 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2328 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2329 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2330 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2331 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2332 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2355 EVT VT = Op.getValueType();
2356 EVT ShVT = TLI.getShiftAmountTy(VT);
2357 unsigned Len = VT.getSizeInBits();
2359 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2365 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2366 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2367 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2368 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2371 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2372 DAG.getNode(ISD::AND, dl, VT,
2373 DAG.getNode(ISD::SRL, dl, VT, Op,
2377 Op = DAG.getNode(ISD::ADD, dl, VT,
2378 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2379 DAG.getNode(ISD::AND, dl, VT,
2380 DAG.getNode(ISD::SRL, dl, VT, Op,
2384 Op = DAG.getNode(ISD::AND, dl, VT,
2385 DAG.getNode(ISD::ADD, dl, VT, Op,
2386 DAG.getNode(ISD::SRL, dl, VT, Op,
2390 Op = DAG.getNode(ISD::SRL, dl, VT,
2391 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2409 EVT VT = Op.getValueType();
2410 EVT ShVT = TLI.getShiftAmountTy(VT);
2411 unsigned len = VT.getSizeInBits();
2414 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2415 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2417 Op = DAG.getNOT(dl, Op, VT);
2418 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2428 EVT VT = Op.getValueType();
2429 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2430 DAG.getNOT(dl, Op, VT),
2431 DAG.getNode(ISD::SUB, dl, VT, Op,
2432 DAG.getConstant(1, VT)));
2434 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2435 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2436 return DAG.getNode(ISD::SUB, dl, VT,
2437 DAG.getConstant(VT.getSizeInBits(), VT),
2438 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2439 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2446 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2453 switch (VT.SimpleTy) {
2462 switch (VT.SimpleTy) {
2471 switch (VT.SimpleTy) {
2480 switch (VT.SimpleTy) {
2489 switch (VT.SimpleTy) {
2498 switch (VT.SimpleTy) {
2507 switch (VT.SimpleTy) {
2516 switch (VT.SimpleTy) {
2638 EVT VT = Node->getValueType(0);
2639 if (VT.isInteger())
2640 Results.push_back(DAG.getConstant(0, VT));
2642 assert(VT.isFloatingPoint() && "Unknown value type!");
2643 Results.push_back(DAG.getConstantFP(0, VT));
2676 EVT VT = Node->getValueType(0);
2677 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2678 if (VT.isVector())
2679 ShiftAmountTy = VT;
2680 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2710 EVT VT = Node->getOperand(0).getValueType();
2712 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2715 Tmp1 = DAG.getConstantFP(apf, VT);
2716 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2721 DAG.getNode(ISD::FSUB, dl, VT,
2731 EVT VT = Node->getValueType(0);
2756 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2762 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2811 EVT VT = Node->getValueType(0);
2812 EVT EltVT = VT.getVectorElementType();
2827 // Calculate new VT, the size of the new VT should be equal to original.
2829 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2830 assert(NewVT.bitsEq(VT));
2832 // cast operands to new VT
2837 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2842 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2853 VT = NewVT;
2857 unsigned NumElems = VT.getVectorNumElements();
2875 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2931 EVT VT = Node->getValueType(0);
2933 Tmp2 = DAG.getConstantFP(0.0, VT);
2936 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2937 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3046 EVT VT = Node->getValueType(0);
3047 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3048 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3050 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3051 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3056 EVT VT = Node->getValueType(0);
3057 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3058 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3060 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3061 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3062 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3063 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3068 EVT VT = Node->getValueType(0);
3069 SDVTList VTs = DAG.getVTList(VT, VT);
3075 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3079 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3081 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3082 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3083 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3101 EVT VT = Node->getValueType(0);
3102 SDVTList VTs = DAG.getVTList(VT, VT);
3103 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3125 EVT VT = Node->getValueType(0);
3126 SDVTList VTs = DAG.getVTList(VT, VT);
3127 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3140 EVT VT = Node->getValueType(0);
3141 SDVTList VTs = DAG.getVTList(VT, VT);
3147 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3148 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3149 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3150 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3222 EVT VT = Node->getValueType(0);
3223 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3232 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3233 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3234 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3235 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3236 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3240 VT.getSizeInBits() * 2))) {
3244 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3246 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3266 unsigned LoSize = VT.getSizeInBits();
3267 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3269 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3278 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3280 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3289 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3291 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3292 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3295 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3296 DAG.getConstant(0, VT), ISD::SETNE);
3394 EVT VT = Node->getValueType(0);
3395 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3396 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3442 EVT VT = Node->getValueType(0);
3443 assert(VT.isVector() && "Unable to legalize non-vector shift");
3444 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3445 unsigned NumElem = VT.getVectorNumElements();
3450 VT.getScalarType(),
3453 VT.getScalarType(),
3456 VT.getScalarType(), Ex, Sh));
3513 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))