Cross Reference: /external/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Lines Matching refs:PredReg
95                   ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109                         unsigned PredReg,
115                       ARMCC::CondCodes Pred, unsigned PredReg,
286                           unsigned PredReg, unsigned Scratch, DebugLoc dl,
340       .addImm(Pred).addReg(PredReg).addReg(0);
351     .addImm(Pred).addReg(PredReg);
371                                      ARMCC::CondCodes Pred, unsigned PredReg,
416                 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448                           ARMCC::CondCodes Pred, unsigned PredReg,
501                      Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
502       MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
513                  Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
533                                 ARMCC::CondCodes Pred, unsigned PredReg) {
558         MyPredReg == PredReg))
566                                 ARMCC::CondCodes Pred, unsigned PredReg) {
591         MyPredReg == PredReg))
720   unsigned PredReg = 0;
721   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
741         isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
745                isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
760         isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
763                isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
782     .addImm(Pred).addReg(PredReg);
873   unsigned PredReg = 0;
874   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
887     if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
891                isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
907         isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
910     } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
935       .addImm(Pred).addReg(PredReg)
945           .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
950           .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
957         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
969         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
975         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1081                           ARMCC::CondCodes Pred, unsigned PredReg,
1088     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1094     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1131     unsigned PredReg = 0;
1132     ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1143           .addImm(Pred).addReg(PredReg)
1150           .addImm(Pred).addReg(PredReg)
1178                       Pred, PredReg, TII, isT2);
1185                       Pred, PredReg, TII, isT2);
1201                       Pred, PredReg, TII, isT2);
1206                       Pred, PredReg, TII, isT2);
1253       unsigned PredReg = 0;
1254       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
1272         CurrPredReg = PredReg;
1283           // No need to match PredReg.
1473                           unsigned &PredReg, ARMCC::CondCodes &Pred,
1568                                           int &Offset, unsigned &PredReg,
1630   Pred = getInstrPredicate(Op0, PredReg);
1729         unsigned BaseReg = 0, PredReg = 0;
1737                                              Offset, PredReg, Pred, isT2)) {
1757             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1771             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1826       unsigned PredReg = 0;
1827       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)