Lines Matching refs:Inst
184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
204 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
206 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
208 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
210 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
212 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
214 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
216 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
218 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
220 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
222 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
224 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
227 bool validateInstruction(MCInst &Inst,
229 bool processInstruction(MCInst &Inst,
262 unsigned checkTargetMatchPredicate(MCInst &Inst);
1382 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1385 Inst.addOperand(MCOperand::CreateImm(0));
1387 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1389 Inst.addOperand(MCOperand::CreateExpr(Expr));
1392 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1394 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1396 Inst.addOperand(MCOperand::CreateReg(RegNum));
1399 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1401 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1404 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1406 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1409 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1411 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1414 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1416 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1419 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1421 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1424 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1426 Inst.addOperand(MCOperand::CreateReg(getReg()));
1429 void addRegOperands(MCInst &Inst, unsigned N) const {
1431 Inst.addOperand(MCOperand::CreateReg(getReg()));
1434 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1438 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1439 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1440 Inst.addOperand(MCOperand::CreateImm(
1444 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1448 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1449 Inst.addOperand(MCOperand::CreateImm(
1453 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1455 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1459 void addRegListOperands(MCInst &Inst, unsigned N) const {
1464 Inst.addOperand(MCOperand::CreateReg(*I));
1467 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1468 addRegListOperands(Inst, N);
1471 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1472 addRegListOperands(Inst, N);
1475 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1478 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1481 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1489 Inst.addOperand(MCOperand::CreateImm(Mask));
1492 void addImmOperands(MCInst &Inst, unsigned N) const {
1494 addExpr(Inst, getImm());
1497 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1500 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1503 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1506 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1509 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1513 Inst.addOperand(MCOperand::CreateImm(Val));
1516 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1521 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1524 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1529 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1532 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1537 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1540 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1545 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1548 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1553 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1556 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1561 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1564 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1570 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1573 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1579 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1582 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1587 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1590 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1595 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1598 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1603 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1606 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1611 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1614 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1619 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1622 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1624 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1627 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1629 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1632 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1637 Inst.addOperand(MCOperand::CreateImm(Imm));
1640 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1642 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1643 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1646 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1661 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1662 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1663 Inst.addOperand(MCOperand::CreateImm(Val));
1666 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1676 Inst.addOperand(MCOperand::CreateReg(0));
1677 Inst.addOperand(MCOperand::CreateImm(Val));
1680 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1686 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1687 Inst.addOperand(MCOperand::CreateReg(0));
1688 Inst.addOperand(MCOperand::CreateImm(0));
1704 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1705 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1706 Inst.addOperand(MCOperand::CreateImm(Val));
1709 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1714 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1715 Inst.addOperand(MCOperand::CreateImm(Val));
1727 Inst.addOperand(MCOperand::CreateReg(0));
1728 Inst.addOperand(MCOperand::CreateImm(Val));
1731 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1737 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1738 Inst.addOperand(MCOperand::CreateImm(0));
1749 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1750 Inst.addOperand(MCOperand::CreateImm(Val));
1753 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1759 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1760 Inst.addOperand(MCOperand::CreateImm(0));
1765 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1766 Inst.addOperand(MCOperand::CreateImm(Val));
1769 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1773 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1774 Inst.addOperand(MCOperand::CreateImm(Val));
1777 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1780 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1781 Inst.addOperand(MCOperand::CreateImm(Val));
1784 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1785 addMemImm8OffsetOperands(Inst, N);
1788 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1789 addMemImm8OffsetOperands(Inst, N);
1792 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1796 addExpr(Inst, getImm());
1797 Inst.addOperand(MCOperand::CreateImm(0));
1803 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1804 Inst.addOperand(MCOperand::CreateImm(Val));
1807 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1811 addExpr(Inst, getImm());
1812 Inst.addOperand(MCOperand::CreateImm(0));
1818 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1819 Inst.addOperand(MCOperand::CreateImm(Val));
1822 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1824 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1825 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1828 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1830 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1831 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1834 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1839 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1840 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1841 Inst.addOperand(MCOperand::CreateImm(Val));
1844 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1846 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1847 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1848 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1851 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1853 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1854 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1857 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1860 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1861 Inst.addOperand(MCOperand::CreateImm(Val));
1864 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1867 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1868 Inst.addOperand(MCOperand::CreateImm(Val));
1871 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1874 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1875 Inst.addOperand(MCOperand::CreateImm(Val));
1878 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1881 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1882 Inst.addOperand(MCOperand::CreateImm(Val));
1885 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1893 Inst.addOperand(MCOperand::CreateImm(Imm));
1896 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1905 Inst.addOperand(MCOperand::CreateImm(Imm));
1908 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1910 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1911 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1914 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1916 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1922 Inst.addOperand(MCOperand::CreateImm(Imm));
1925 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1927 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1930 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1932 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1935 void addVecListOperands(MCInst &Inst, unsigned N) const {
1937 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1940 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1942 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1943 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1946 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1948 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1951 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1953 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1956 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1958 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1961 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1966 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1969 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1978 Inst.addOperand(MCOperand::CreateImm(Value));
1981 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1992 Inst.addOperand(MCOperand::CreateImm(Value));
1995 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2006 Inst.addOperand(MCOperand::CreateImm(Value));
2009 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2020 Inst.addOperand(MCOperand::CreateImm(Value));
2023 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2032 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
3796 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3799 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3800 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3802 Inst.addOperand(MCOperand::CreateReg(0));
3804 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3806 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3814 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3817 Inst.addOperand(MCOperand::CreateReg(0));
3819 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3820 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3822 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3824 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3832 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3834 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3837 Inst.addOperand(MCOperand::CreateImm(0));
3839 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3840 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3848 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3851 Inst.addOperand(MCOperand::CreateImm(0));
3852 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3853 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3854 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3862 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3864 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3867 Inst.addOperand(MCOperand::CreateImm(0));
3869 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3870 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3878 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3880 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3883 Inst.addOperand(MCOperand::CreateImm(0));
3885 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3886 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3895 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3898 Inst.addOperand(MCOperand::CreateImm(0));
3899 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3900 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3901 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3909 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3912 Inst.addOperand(MCOperand::CreateImm(0));
3913 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3914 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3915 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3923 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3926 Inst.addOperand(MCOperand::CreateImm(0));
3927 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3928 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3929 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3937 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3940 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3942 Inst.addOperand(MCOperand::CreateImm(0));
3944 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3946 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3948 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3956 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3959 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3961 Inst.addOperand(MCOperand::CreateImm(0));
3963 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3965 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3967 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3975 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3978 Inst.addOperand(MCOperand::CreateImm(0));
3980 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3982 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3984 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3986 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3994 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3997 Inst.addOperand(MCOperand::CreateImm(0));
3999 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4001 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4003 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4005 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4013 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4016 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4017 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4019 Inst.addOperand(MCOperand::CreateImm(0));
4021 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4023 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4031 cvtStrdPre(MCInst &Inst, unsigned Opcode,
4034 Inst.addOperand(MCOperand::CreateImm(0));
4036 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4039 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4041 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4049 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4051 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4053 Inst.addOperand(MCOperand::CreateImm(0));
4054 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4055 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4063 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4076 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4077 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4085 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4086 Inst.addOperand(Inst.getOperand(0));
4087 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4093 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4096 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4098 Inst.addOperand(MCOperand::CreateImm(0));
4100 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4102 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4107 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4110 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4112 Inst.addOperand(MCOperand::CreateImm(0));
4114 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4116 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4118 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4123 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4126 Inst.addOperand(MCOperand::CreateImm(0));
4128 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4130 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4132 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4137 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4140 Inst.addOperand(MCOperand::CreateImm(0));
4142 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4144 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4146 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4148 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
5137 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5140 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5141 unsigned OpReg = Inst.getOperand(i).getReg();
5153 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5154 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5155 unsigned OpReg = Inst.getOperand(i).getReg();
5174 validateInstruction(MCInst &Inst,
5176 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5182 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5183 Inst.getOpcode() != ARM::BKPT) {
5192 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5208 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5209 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5210 Inst.getOpcode() != ARM::t2B)
5213 switch (Inst.getOpcode()) {
5219 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5220 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5228 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5229 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5239 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5240 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5249 unsigned lsb = Inst.getOperand(2).getImm();
5250 unsigned widthm1 = Inst.getOperand(3).getImm();
5264 unsigned Rn = Inst.getOperand(0).getReg();
5269 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5286 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5297 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5305 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5313 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5580 processInstruction(MCInst &Inst,
5582 switch (Inst.getOpcode()) {
5585 Inst.setOpcode(ARM::t2LDRpci);
5588 Inst.setOpcode(ARM::t2LDRBpci);
5591 Inst.setOpcode(ARM::t2LDRHpci);
5594 Inst.setOpcode(ARM::t2LDRSBpci);
5597 Inst.setOpcode(ARM::t2LDRSHpci);
5607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5608 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5609 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5610 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5611 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5612 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5613 TmpInst.addOperand(Inst.getOperand(1)); // lane
5614 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5615 TmpInst.addOperand(Inst.getOperand(6));
5616 Inst = TmpInst;
5629 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5630 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5631 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5632 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5633 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5634 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5637 TmpInst.addOperand(Inst.getOperand(1)); // lane
5638 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5639 TmpInst.addOperand(Inst.getOperand(6));
5640 Inst = TmpInst;
5653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5654 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5655 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5656 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5657 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5658 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5661 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5663 TmpInst.addOperand(Inst.getOperand(1)); // lane
5664 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5665 TmpInst.addOperand(Inst.getOperand(6));
5666 Inst = TmpInst;
5679 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5680 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5681 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5682 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5683 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5684 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5685 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5691 TmpInst.addOperand(Inst.getOperand(1)); // lane
5692 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5693 TmpInst.addOperand(Inst.getOperand(6));
5694 Inst = TmpInst;
5705 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5706 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5707 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5708 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5710 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5711 TmpInst.addOperand(Inst.getOperand(1)); // lane
5712 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5713 TmpInst.addOperand(Inst.getOperand(5));
5714 Inst = TmpInst;
5727 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5728 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5729 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5730 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5732 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5735 TmpInst.addOperand(Inst.getOperand(1)); // lane
5736 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5737 TmpInst.addOperand(Inst.getOperand(5));
5738 Inst = TmpInst;
5751 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5752 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5753 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5754 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5756 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5761 TmpInst.addOperand(Inst.getOperand(1)); // lane
5762 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5763 TmpInst.addOperand(Inst.getOperand(5));
5764 Inst = TmpInst;
5777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5779 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5780 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5789 TmpInst.addOperand(Inst.getOperand(1)); // lane
5790 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5791 TmpInst.addOperand(Inst.getOperand(5));
5792 Inst = TmpInst;
5803 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5804 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5805 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5807 TmpInst.addOperand(Inst.getOperand(1)); // lane
5808 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5809 TmpInst.addOperand(Inst.getOperand(5));
5810 Inst = TmpInst;
5823 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5824 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5825 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5826 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5827 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5829 TmpInst.addOperand(Inst.getOperand(1)); // lane
5830 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5831 TmpInst.addOperand(Inst.getOperand(5));
5832 Inst = TmpInst;
5845 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5846 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5847 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5848 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5849 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5851 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5853 TmpInst.addOperand(Inst.getOperand(1)); // lane
5854 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5855 TmpInst.addOperand(Inst.getOperand(5));
5856 Inst = TmpInst;
5869 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5870 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5871 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5872 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5873 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5875 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5879 TmpInst.addOperand(Inst.getOperand(1)); // lane
5880 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5881 TmpInst.addOperand(Inst.getOperand(5));
5882 Inst = TmpInst;
5894 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5895 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5896 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5897 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5898 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5899 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5900 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5901 TmpInst.addOperand(Inst.getOperand(1)); // lane
5902 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5903 TmpInst.addOperand(Inst.getOperand(6));
5904 Inst = TmpInst;
5917 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5921 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5922 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5923 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5924 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5925 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5926 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5928 TmpInst.addOperand(Inst.getOperand(1)); // lane
5929 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5930 TmpInst.addOperand(Inst.getOperand(6));
5931 Inst = TmpInst;
5944 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5945 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5946 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5948 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5951 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5952 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5953 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5954 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5955 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5957 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5959 TmpInst.addOperand(Inst.getOperand(1)); // lane
5960 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5961 TmpInst.addOperand(Inst.getOperand(6));
5962 Inst = TmpInst;
5975 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5976 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5983 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5984 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5985 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5986 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5987 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5988 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5990 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5994 TmpInst.addOperand(Inst.getOperand(1)); // lane
5995 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5996 TmpInst.addOperand(Inst.getOperand(6));
5997 Inst = TmpInst;
6008 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6009 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6010 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6011 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6012 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6014 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6015 TmpInst.addOperand(Inst.getOperand(1)); // lane
6016 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6017 TmpInst.addOperand(Inst.getOperand(5));
6018 Inst = TmpInst;
6031 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6032 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6035 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6036 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6037 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6039 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6040 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6042 TmpInst.addOperand(Inst.getOperand(1)); // lane
6043 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6044 TmpInst.addOperand(Inst.getOperand(5));
6045 Inst = TmpInst;
6058 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6059 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6064 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6065 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6066 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6068 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6069 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6073 TmpInst.addOperand(Inst.getOperand(1)); // lane
6074 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6075 TmpInst.addOperand(Inst.getOperand(5));
6076 Inst = TmpInst;
6089 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6090 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6091 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6093 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6095 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6097 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6098 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6099 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6101 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6102 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6104 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6106 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6108 TmpInst.addOperand(Inst.getOperand(1)); // lane
6109 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6110 TmpInst.addOperand(Inst.getOperand(5));
6111 Inst = TmpInst;
6122 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6123 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6124 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6125 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6126 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6127 TmpInst.addOperand(Inst.getOperand(1)); // lane
6128 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6129 TmpInst.addOperand(Inst.getOperand(5));
6130 Inst = TmpInst;
6143 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6144 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6148 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6149 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6152 TmpInst.addOperand(Inst.getOperand(1)); // lane
6153 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6154 TmpInst.addOperand(Inst.getOperand(5));
6155 Inst = TmpInst;
6168 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6169 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6172 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6174 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6175 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6176 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6177 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6179 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6181 TmpInst.addOperand(Inst.getOperand(1)); // lane
6182 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6183 TmpInst.addOperand(Inst.getOperand(5));
6184 Inst = TmpInst;
6197 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6198 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6201 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6206 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6207 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6212 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6214 TmpInst.addOperand(Inst.getOperand(1)); // lane
6215 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6216 TmpInst.addOperand(Inst.getOperand(5));
6217 Inst = TmpInst;
6230 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6231 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6232 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6237 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6238 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6239 TmpInst.addOperand(Inst.getOperand(4));
6240 Inst = TmpInst;
6252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6253 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6254 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6258 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6259 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6260 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6262 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6263 TmpInst.addOperand(Inst.getOperand(4));
6264 Inst = TmpInst;
6276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6277 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6283 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6284 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6285 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6286 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6287 TmpInst.addOperand(Inst.getOperand(5));
6288 Inst = TmpInst;
6301 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6302 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6303 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6308 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6309 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6310 TmpInst.addOperand(Inst.getOperand(4));
6311 Inst = TmpInst;
6323 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6324 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6329 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6330 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6331 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6333 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6334 TmpInst.addOperand(Inst.getOperand(4));
6335 Inst = TmpInst;
6347 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6348 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6351 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6353 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6354 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6355 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6356 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6357 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6358 TmpInst.addOperand(Inst.getOperand(5));
6359 Inst = TmpInst;
6372 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6373 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6380 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6381 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6382 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6383 TmpInst.addOperand(Inst.getOperand(4));
6384 Inst = TmpInst;
6396 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6397 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6405 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6406 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6408 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6409 TmpInst.addOperand(Inst.getOperand(4));
6410 Inst = TmpInst;
6422 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6423 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6424 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6431 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6432 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6433 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6434 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6435 TmpInst.addOperand(Inst.getOperand(5));
6436 Inst = TmpInst;
6449 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6450 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6451 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6453 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6458 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6459 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6460 TmpInst.addOperand(Inst.getOperand(4));
6461 Inst = TmpInst;
6473 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6474 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6477 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6481 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6482 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6483 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6485 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6486 TmpInst.addOperand(Inst.getOperand(4));
6487 Inst = TmpInst;
6499 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6500 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6501 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6503 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6505 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6507 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6508 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6509 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6510 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6511 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6512 TmpInst.addOperand(Inst.getOperand(5));
6513 Inst = TmpInst;
6526 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6527 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6528 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6529 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6535 TmpInst.addOperand(Inst.getOperand(4));
6536 Inst = TmpInst;
6548 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6549 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6550 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6551 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6553 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6554 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6558 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6559 TmpInst.addOperand(Inst.getOperand(4));
6560 Inst = TmpInst;
6572 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6573 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6574 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6575 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6576 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6577 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6578 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6583 TmpInst.addOperand(Inst.getOperand(5));
6584 Inst = TmpInst;
6597 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6598 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6599 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6600 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6605 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6608 TmpInst.addOperand(Inst.getOperand(4));
6609 Inst = TmpInst;
6621 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6622 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6623 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6624 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6626 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6627 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6629 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6634 TmpInst.addOperand(Inst.getOperand(4));
6635 Inst = TmpInst;
6647 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6648 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6649 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6650 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6651 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6652 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6653 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6660 TmpInst.addOperand(Inst.getOperand(5));
6661 Inst = TmpInst;
6669 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6670 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6671 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6675 switch (Inst.getOpcode()) {
6684 TmpInst.addOperand(Inst.getOperand(0));
6685 TmpInst.addOperand(Inst.getOperand(5));
6686 TmpInst.addOperand(Inst.getOperand(1));
6687 TmpInst.addOperand(Inst.getOperand(2));
6688 TmpInst.addOperand(Inst.getOperand(3));
6689 TmpInst.addOperand(Inst.getOperand(4));
6690 Inst = TmpInst;
6703 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6704 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6705 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6706 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6707 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6711 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6719 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6722 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6723 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6724 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6725 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6726 TmpInst.addOperand(Inst.getOperand(5));
6729 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6730 Inst = TmpInst;
6739 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6740 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6741 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6745 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6753 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6756 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6759 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6760 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6763 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6764 TmpInst.addOperand(Inst.getOperand(4));
6767 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6768 Inst = TmpInst;
6777 switch(Inst.getOpcode()) {
6787 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6788 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6789 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6791 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6792 TmpInst.addOperand(Inst.getOperand(4));
6793 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6794 Inst = TmpInst;
6802 switch(Inst.getOpcode()) {
6810 unsigned Amt = Inst.getOperand(2).getImm();
6815 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6816 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6819 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6820 TmpInst.addOperand(Inst.getOperand(4));
6821 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6822 Inst = TmpInst;
6829 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6830 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6832 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6833 TmpInst.addOperand(Inst.getOperand(3));
6834 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6835 Inst = TmpInst;
6841 if (Inst.getNumOperands() != 5)
6845 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6846 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6847 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6849 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6850 TmpInst.addOperand(Inst.getOperand(3));
6851 Inst = TmpInst;
6857 if (Inst.getNumOperands() != 5)
6861 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6862 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6863 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6865 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6866 TmpInst.addOperand(Inst.getOperand(3));
6867 Inst = TmpInst;
6874 Inst.getNumOperands() == 5) {
6877 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6878 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6879 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6882 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6883 TmpInst.addOperand(Inst.getOperand(3));
6884 Inst = TmpInst;
6892 Inst.getNumOperands() == 5) {
6895 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6896 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6897 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6899 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6900 TmpInst.addOperand(Inst.getOperand(3));
6901 Inst = TmpInst;
6908 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6910 Inst.setOpcode(ARM::t2ADDri);
6911 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6917 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6919 Inst.setOpcode(ARM::t2SUBri);
6920 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6927 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6928 Inst.setOpcode(ARM::tADDi3);
6937 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6938 Inst.setOpcode(ARM::tSUBi3);
6948 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6949 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
6950 (unsigned)Inst.getOperand(2).getImm() > 255 ||
6951 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
6952 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
6957 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
6959 TmpInst.addOperand(Inst.getOperand(0));
6960 TmpInst.addOperand(Inst.getOperand(5));
6961 TmpInst.addOperand(Inst.getOperand(0));
6962 TmpInst.addOperand(Inst.getOperand(2));
6963 TmpInst.addOperand(Inst.getOperand(3));
6964 TmpInst.addOperand(Inst.getOperand(4));
6965 Inst = TmpInst;
6973 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6974 Inst.getOperand(5).getReg() != 0 ||
6980 TmpInst.addOperand(Inst.getOperand(0));
6981 TmpInst.addOperand(Inst.getOperand(0));
6982 TmpInst.addOperand(Inst.getOperand(2));
6983 TmpInst.addOperand(Inst.getOperand(3));
6984 TmpInst.addOperand(Inst.getOperand(4));
6985 Inst = TmpInst;
6990 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
6991 Inst.setOpcode(ARM::tBcc);
6997 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
6998 Inst.setOpcode(ARM::t2Bcc);
7004 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7005 Inst.setOpcode(ARM::t2B);
7011 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7012 Inst.setOpcode(ARM::tB);
7021 unsigned Rn = Inst.getOperand(0).getReg();
7026 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7031 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7035 Inst.insert(Inst.begin(),
7036 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7045 unsigned Rn = Inst.getOperand(0).getReg();
7047 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7050 Inst.setOpcode(ARM::t2STMIA_UPD);
7060 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7063 Inst.setOpcode(ARM::t2LDMIA_UPD);
7065 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7066 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7071 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7074 Inst.setOpcode(ARM::t2STMDB_UPD);
7076 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7077 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7083 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7084 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7085 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7086 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7087 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7093 TmpInst.addOperand(Inst.getOperand(0));
7094 TmpInst.addOperand(Inst.getOperand(4));
7095 TmpInst.addOperand(Inst.getOperand(1));
7096 TmpInst.addOperand(Inst.getOperand(2));
7097 TmpInst.addOperand(Inst.getOperand(3));
7098 Inst = TmpInst;
7106 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7107 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7108 Inst.getOperand(2).getImm() == ARMCC::AL &&
7109 Inst.getOperand(4).getReg() == ARM::CPSR &&
7114 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7115 TmpInst.addOperand(Inst.getOperand(0));
7116 TmpInst.addOperand(Inst.getOperand(1));
7117 TmpInst.addOperand(Inst.getOperand(2));
7118 TmpInst.addOperand(Inst.getOperand(3));
7119 Inst = TmpInst;
7130 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7131 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7132 Inst.getOperand(2).getImm() == 0 &&
7136 switch (Inst.getOpcode()) {
7146 TmpInst.addOperand(Inst.getOperand(0));
7147 TmpInst.addOperand(Inst.getOperand(1));
7148 TmpInst.addOperand(Inst.getOperand(3));
7149 TmpInst.addOperand(Inst.getOperand(4));
7150 Inst = TmpInst;
7156 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7158 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7162 TmpInst.addOperand(Inst.getOperand(0));
7163 TmpInst.addOperand(Inst.getOperand(1));
7164 TmpInst.addOperand(Inst.getOperand(3));
7165 TmpInst.addOperand(Inst.getOperand(4));
7166 TmpInst.addOperand(Inst.getOperand(5));
7167 Inst = TmpInst;
7179 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7181 switch (Inst.getOpcode()) {
7191 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
7194 TmpInst.addOperand(Inst.getOperand(0));
7195 TmpInst.addOperand(Inst.getOperand(1));
7196 TmpInst.addOperand(Inst.getOperand(2));
7197 TmpInst.addOperand(Inst.getOperand(4));
7198 TmpInst.addOperand(Inst.getOperand(5));
7199 TmpInst.addOperand(Inst.getOperand(6));
7200 Inst = TmpInst;
7213 MCOperand &MO = Inst.getOperand(1);
7217 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7228 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7238 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7241 unsigned Opc = Inst.getOpcode();
7246 assert(MCID.NumOperands == Inst.getNumOperands() &&
7255 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7259 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7262 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7269 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7270 isARMLowRegister(Inst.getOperand(2).getReg()))
7274 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7275 isARMLowRegister(Inst.getOperand(1).getReg()))
7284 MCInst Inst;
7287 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7293 if (validateInstruction(Inst, Operands)) {
7304 while (processInstruction(Inst, Operands))
7314 if (Inst.getOpcode() == ARM::ITasm)
7317 Inst.setLoc(IDLoc);
7318 Out.EmitInstruction(Inst);