Lines Matching refs:PredReg
60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
180 ARMCC::CondCodes Pred, unsigned PredReg,
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
403 unsigned PredReg;
404 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
575 unsigned PredReg = 0;
576 ARMCC::CondCodes CC = getInstrPredicate(UseMI, PredReg);
577 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
592 ARMCC::CondCodes NCC = getInstrPredicate(NMI, PredReg);
609 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
613 return getInstrPredicate(MI, PredReg);