Lines Matching refs:op
193 static IRExpr* unop ( IROp op, IRExpr* a )
195 return IRExpr_Unop(op, a);
1191 /* Is it an addition or logical style op? */
1192 switch (e->Iex.Binop.op) {
1230 switch (e->Iex.Binop.op) {
1286 if (e->Iex.Binop.op == Iop_DivS32 ||
1287 e->Iex.Binop.op == Iop_DivU32 ||
1288 e->Iex.Binop.op == Iop_DivS32E ||
1289 e->Iex.Binop.op == Iop_DivU32E) {
1290 Bool syned = toBool((e->Iex.Binop.op == Iop_DivS32) || (e->Iex.Binop.op == Iop_DivS32E));
1295 PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivU32E )
1296 || ( e->Iex.Binop.op == Iop_DivS32E ) ) ? True
1305 if (e->Iex.Binop.op == Iop_DivS64 ||
1306 e->Iex.Binop.op == Iop_DivU64 || e->Iex.Binop.op == Iop_DivS64E
1307 || e->Iex.Binop.op == Iop_DivU64E ) {
1308 Bool syned = toBool((e->Iex.Binop.op == Iop_DivS64) ||(e->Iex.Binop.op == Iop_DivS64E));
1314 PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivS64E )
1315 || ( e->Iex.Binop.op
1327 if (e->Iex.Binop.op == Iop_Mul32
1328 || e->Iex.Binop.op == Iop_Mul64) {
1330 Bool sz32 = (e->Iex.Binop.op != Iop_Mul64);
1341 && (e->Iex.Binop.op == Iop_MullU32
1342 || e->Iex.Binop.op == Iop_MullS32)) {
1346 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS32);
1363 if (e->Iex.Binop.op == Iop_CmpORD32S
1364 || e->Iex.Binop.op == Iop_CmpORD32U) {
1365 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD32S);
1377 if (e->Iex.Binop.op == Iop_CmpORD64S
1378 || e->Iex.Binop.op == Iop_CmpORD64U) {
1379 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD64S);
1392 if (e->Iex.Binop.op == Iop_Max32U) {
1404 if (e->Iex.Binop.op == Iop_32HLto64) {
1421 if (e->Iex.Binop.op == Iop_CmpF64) {
1480 if ( e->Iex.Binop.op == Iop_F64toI32S ||
1481 e->Iex.Binop.op == Iop_F64toI32U ) {
1494 e->Iex.Binop.op == Iop_F64toI32S ? True/*syned*/
1512 if (e->Iex.Binop.op == Iop_F64toI64S || e->Iex.Binop.op == Iop_F64toI64U ) {
1525 ( e->Iex.Binop.op == Iop_F64toI64S ) ? True
1543 IROp op_unop = e->Iex.Unop.op;
1667 /* This is a no-op. */
1672 if (mode64) { /* This is a no-op. */
2077 && e->Iex.Binop.op == Iop_Add64
2091 && e->Iex.Binop.op == Iop_Add64) {
2103 && e->Iex.Binop.op == Iop_Add32
2114 && e->Iex.Binop.op == Iop_Add32) {
2362 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) {
2373 (e->Iex.Unop.op == Iop_32to1 || e->Iex.Unop.op == Iop_64to1)) {
2389 && e->Iex.Unop.op == Iop_CmpNEZ8) {
2403 && e->Iex.Unop.op == Iop_CmpNEZ32) {
2414 && (e->Iex.Binop.op == Iop_CmpEQ32
2415 || e->Iex.Binop.op == Iop_CmpNE32
2416 || e->Iex.Binop.op == Iop_CmpLT32S
2417 || e->Iex.Binop.op == Iop_CmpLT32U
2418 || e->Iex.Binop.op == Iop_CmpLE32S
2419 || e->Iex.Binop.op == Iop_CmpLE32U)) {
2420 Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S ||
2421 e->Iex.Binop.op == Iop_CmpLE32S);
2427 switch (e->Iex.Binop.op) {
2442 && e->Iex.Unop.op == Iop_CmpNEZ64) {
2463 && (e->Iex.Binop.op == Iop_CmpEQ64
2464 || e->Iex.Binop.op == Iop_CmpNE64
2465 || e->Iex.Binop.op == Iop_CmpLT64S
2466 || e->Iex.Binop.op == Iop_CmpLT64U
2467 || e->Iex.Binop.op == Iop_CmpLE64S
2468 || e->Iex.Binop.op == Iop_CmpLE64U)) {
2469 Bool syned = (e->Iex.Binop.op == Iop_CmpLT64S ||
2470 e->Iex.Binop.op == Iop_CmpLE64S);
2477 switch (e->Iex.Binop.op) {
2544 switch (e->Iex.Binop.op) {
2550 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
2578 switch (e->Iex.Unop.op) {
2702 IROp op_binop = e->Iex.Binop.op;
2730 PPCAluOp op = (op_binop == Iop_Or64) ? Palu_OR :
2734 addInstr(env, PPCInstr_Alu(op, tHi, xHi, PPCRH_Reg(yHi)));
2735 addInstr(env, PPCInstr_Alu(op, tLo, xLo, PPCRH_Reg(yLo)));
2801 switch (e->Iex.Unop.op) {
2868 Int off = e->Iex.Unop.op==Iop_V128HIto64 ? 0 : 8;
3012 if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_TruncF64asF32) {
3056 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64UtoF32) {
3218 switch (e->Iex.Qop.op) {
3239 switch (e->Iex.Triop.op) {
3262 switch (e->Iex.Binop.op) {
3277 if (e->Iex.Binop.op == Iop_RoundF64toF32) {
3286 if (e->Iex.Binop.op == Iop_I64StoF64 || e->Iex.Binop.op == Iop_I64UtoF64) {
3301 e->Iex.Binop.op == Iop_I64StoF64,
3329 e->Iex.Binop.op == Iop_I64StoF64,
3345 switch (e->Iex.Unop.op) {
3364 switch (e->Iex.Unop.op) {
3380 e->Iex.Unop.arg->Iex.Unop.op == Iop_ReinterpI32asF32 ) {
3402 /* this is a no-op */
3456 PPCAvOp op = Pav_INVALID;
3487 switch (e->Iex.Unop.op) {
3582 } /* switch (e->Iex.Unop.op) */
3586 switch (e->Iex.Binop.op) {
3682 case Iop_AndV128: op = Pav_AND; goto do_AvBin;
3683 case Iop_OrV128: op = Pav_OR; goto do_AvBin;
3684 case Iop_XorV128: op = Pav_XOR; goto do_AvBin;
3689 addInstr(env, PPCInstr_AvBinary(op, dst, arg1, arg2));
3693 case Iop_Shl8x16: op = Pav_SHL; goto do_AvBin8x16;
3694 case Iop_Shr8x16: op = Pav_SHR; goto do_AvBin8x16;
3695 case Iop_Sar8x16: op = Pav_SAR; goto do_AvBin8x16;
3696 case Iop_Rol8x16: op = Pav_ROTL; goto do_AvBin8x16;
3697 case Iop_InterleaveHI8x16: op = Pav_MRGHI; goto do_AvBin8x16;
3698 case Iop_InterleaveLO8x16: op = Pav_MRGLO; goto do_AvBin8x16;
3699 case Iop_Add8x16: op = Pav_ADDU; goto do_AvBin8x16;
3700 case Iop_QAdd8Ux16: op = Pav_QADDU; goto do_AvBin8x16;
3701 case Iop_QAdd8Sx16: op = Pav_QADDS; goto do_AvBin8x16;
3702 case Iop_Sub8x16: op = Pav_SUBU; goto do_AvBin8x16;
3703 case Iop_QSub8Ux16: op = Pav_QSUBU; goto do_AvBin8x16;
3704 case Iop_QSub8Sx16: op = Pav_QSUBS; goto do_AvBin8x16;
3705 case Iop_Avg8Ux16: op = Pav_AVGU; goto do_AvBin8x16;
3706 case Iop_Avg8Sx16: op = Pav_AVGS; goto do_AvBin8x16;
3707 case Iop_Max8Ux16: op = Pav_MAXU; goto do_AvBin8x16;
3708 case Iop_Max8Sx16: op = Pav_MAXS; goto do_AvBin8x16;
3709 case Iop_Min8Ux16: op = Pav_MINU; goto do_AvBin8x16;
3710 case Iop_Min8Sx16: op = Pav_MINS; goto do_AvBin8x16;
3711 case Iop_MullEven8Ux16: op = Pav_OMULU; goto do_AvBin8x16;
3712 case Iop_MullEven8Sx16: op = Pav_OMULS; goto do_AvBin8x16;
3713 case Iop_CmpEQ8x16: op = Pav_CMPEQU; goto do_AvBin8x16;
3714 case Iop_CmpGT8Ux16: op = Pav_CMPGTU; goto do_AvBin8x16;
3715 case Iop_CmpGT8Sx16: op = Pav_CMPGTS; goto do_AvBin8x16;
3720 addInstr(env, PPCInstr_AvBin8x16(op, dst, arg1, arg2));
3724 case Iop_Shl16x8: op = Pav_SHL; goto do_AvBin16x8;
3725 case Iop_Shr16x8: op = Pav_SHR; goto do_AvBin16x8;
3726 case Iop_Sar16x8: op = Pav_SAR; goto do_AvBin16x8;
3727 case Iop_Rol16x8: op = Pav_ROTL; goto do_AvBin16x8;
3728 case Iop_NarrowBin16to8x16: op = Pav_PACKUU; goto do_AvBin16x8;
3729 case Iop_QNarrowBin16Uto8Ux16: op = Pav_QPACKUU; goto do_AvBin16x8;
3730 case Iop_QNarrowBin16Sto8Sx16: op = Pav_QPACKSS; goto do_AvBin16x8;
3731 case Iop_InterleaveHI16x8: op = Pav_MRGHI; goto do_AvBin16x8;
3732 case Iop_InterleaveLO16x8: op = Pav_MRGLO; goto do_AvBin16x8;
3733 case Iop_Add16x8: op = Pav_ADDU; goto do_AvBin16x8;
3734 case Iop_QAdd16Ux8: op = Pav_QADDU; goto do_AvBin16x8;
3735 case Iop_QAdd16Sx8: op = Pav_QADDS; goto do_AvBin16x8;
3736 case Iop_Sub16x8: op = Pav_SUBU; goto do_AvBin16x8;
3737 case Iop_QSub16Ux8: op = Pav_QSUBU; goto do_AvBin16x8;
3738 case Iop_QSub16Sx8: op = Pav_QSUBS; goto do_AvBin16x8;
3739 case Iop_Avg16Ux8: op = Pav_AVGU; goto do_AvBin16x8;
3740 case Iop_Avg16Sx8: op = Pav_AVGS; goto do_AvBin16x8;
3741 case Iop_Max16Ux8: op = Pav_MAXU; goto do_AvBin16x8;
3742 case Iop_Max16Sx8: op = Pav_MAXS; goto do_AvBin16x8;
3743 case Iop_Min16Ux8: op = Pav_MINU; goto do_AvBin16x8;
3744 case Iop_Min16Sx8: op = Pav_MINS; goto do_AvBin16x8;
3745 case Iop_MullEven16Ux8: op = Pav_OMULU; goto do_AvBin16x8;
3746 case Iop_MullEven16Sx8: op = Pav_OMULS; goto do_AvBin16x8;
3747 case Iop_CmpEQ16x8: op = Pav_CMPEQU; goto do_AvBin16x8;
3748 case Iop_CmpGT16Ux8: op = Pav_CMPGTU; goto do_AvBin16x8;
3749 case Iop_CmpGT16Sx8: op = Pav_CMPGTS; goto do_AvBin16x8;
3754 addInstr(env, PPCInstr_AvBin16x8(op, dst, arg1, arg2));
3758 case Iop_Shl32x4: op = Pav_SHL; goto do_AvBin32x4;
3759 case Iop_Shr32x4: op = Pav_SHR; goto do_AvBin32x4;
3760 case Iop_Sar32x4: op = Pav_SAR; goto do_AvBin32x4;
3761 case Iop_Rol32x4: op = Pav_ROTL; goto do_AvBin32x4;
3762 case Iop_NarrowBin32to16x8: op = Pav_PACKUU; goto do_AvBin32x4;
3763 case Iop_QNarrowBin32Uto16Ux8: op = Pav_QPACKUU; goto do_AvBin32x4;
3764 case Iop_QNarrowBin32Sto16Sx8: op = Pav_QPACKSS; goto do_AvBin32x4;
3765 case Iop_InterleaveHI32x4: op = Pav_MRGHI; goto do_AvBin32x4;
3766 case Iop_InterleaveLO32x4: op = Pav_MRGLO; goto do_AvBin32x4;
3767 case Iop_Add32x4: op = Pav_ADDU; goto do_AvBin32x4;
3768 case Iop_QAdd32Ux4: op = Pav_QADDU; goto do_AvBin32x4;
3769 case Iop_QAdd32Sx4: op = Pav_QADDS; goto do_AvBin32x4;
3770 case Iop_Sub32x4: op = Pav_SUBU; goto do_AvBin32x4;
3771 case Iop_QSub32Ux4: op = Pav_QSUBU; goto do_AvBin32x4;
3772 case Iop_QSub32Sx4: op = Pav_QSUBS; goto do_AvBin32x4;
3773 case Iop_Avg32Ux4: op = Pav_AVGU; goto do_AvBin32x4;
3774 case Iop_Avg32Sx4: op = Pav_AVGS; goto do_AvBin32x4;
3775 case Iop_Max32Ux4: op = Pav_MAXU; goto do_AvBin32x4;
3776 case Iop_Max32Sx4: op = Pav_MAXS; goto do_AvBin32x4;
3777 case Iop_Min32Ux4: op = Pav_MINU; goto do_AvBin32x4;
3778 case Iop_Min32Sx4: op = Pav_MINS; goto do_AvBin32x4;
3779 case Iop_CmpEQ32x4: op = Pav_CMPEQU; goto do_AvBin32x4;
3780 case Iop_CmpGT32Ux4: op = Pav_CMPGTU; goto do_AvBin32x4;
3781 case Iop_CmpGT32Sx4: op = Pav_CMPGTS; goto do_AvBin32x4;
3786 addInstr(env, PPCInstr_AvBin32x4(op, dst, arg1, arg2));
3790 case Iop_ShlN8x16: op = Pav_SHL; goto do_AvShift8x16;
3791 case Iop_SarN8x16: op = Pav_SAR; goto do_AvShift8x16;
3796 addInstr(env, PPCInstr_AvBin8x16(op, dst, r_src, v_shft));
3800 case Iop_ShlN16x8: op = Pav_SHL; goto do_AvShift16x8;
3801 case Iop_ShrN16x8: op = Pav_SHR; goto do_AvShift16x8;
3802 case Iop_SarN16x8: op = Pav_SAR; goto do_AvShift16x8;
3807 addInstr(env, PPCInstr_AvBin16x8(op, dst, r_src, v_shft));
3811 case Iop_ShlN32x4: op = Pav_SHL; goto do_AvShift32x4;
3812 case Iop_ShrN32x4: op = Pav_SHR; goto do_AvShift32x4;
3813 case Iop_SarN32x4: op = Pav_SAR; goto do_AvShift32x4;
3818 addInstr(env, PPCInstr_AvBin32x4(op, dst, r_src, v_shft));
3822 case Iop_ShrV128: op = Pav_SHR; goto do_AvShiftV128;
3823 case Iop_ShlV128: op = Pav_SHL; goto do_AvShiftV128;
3829 addInstr(env, PPCInstr_AvBinary(op, dst, r_src, v_shft));
3843 } /* switch (e->Iex.Binop.op) */