/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::SPISD::__anon7656
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H A D | SparcISelLowering.cpp | 474 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, local 482 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 489 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 505 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 821 case SPISD::Lo: return "SPISD::Lo"; 887 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); local 890 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 894 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, H 909 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); local [all...] |
/external/llvm/include/llvm/Support/ |
H A D | MDBuilder.h | 57 /// \brief Return metadata describing the range [Lo, Hi). 58 MDNode *createRange(const APInt &Lo, const APInt &Hi) { argument 59 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!"); 61 if (Hi == Lo) 64 // Return the range [Lo, Hi). 65 Type *Ty = IntegerType::get(Context, Lo.getBitWidth()); 66 Value *Range[2] = { ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi) };
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H A D | GCOV.h | 136 uint64_t Lo = readInt(); local 138 uint64_t Result = Lo | (Hi << 32);
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H A D | MathExtras.h | 227 uint32_t Lo = Lo_32(Value); local 229 Count = CountLeadingZeros_32(Lo)+32;
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 32 Lo, ///< Low address component (lower 16) enumerator in enum:llvm::SPUISD::NodeType
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 41 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::HexagonISD::__anon7584
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 37 // No relation with Mips Lo register 38 Lo, enumerator in enum:llvm::MipsISD::NodeType
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H A D | MipsJITInfo.cpp | 134 int Lo = (int)(NewVal & 0xffff); local 137 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo; 174 int Lo = (int)(EmittedAddr & 0xffff); local 181 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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H A D | MipsISelDAGToDAG.cpp | 318 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) { 343 SDNode *Lo = 0, *Hi = 0; local 349 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, 351 InFlag = SDValue(Lo, 1); 357 return std::make_pair(Lo, Hi);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.h | 158 SDValue JoinIntegers(SDValue Lo, SDValue Hi); 170 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 172 SDValue &Lo, SDValue &Hi); 296 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi. 298 /// method returns the two i32's, with Lo being equal to the lower 32 bits of 300 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 301 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi); 306 SDValue &Lo, SDValue &Hi); 307 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); 308 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValu 686 GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument 719 GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part 30 // These routines assume that the Lo/Hi part is stored first in memory on 31 // little/big-endian machines, followed by the Hi/Lo part. This means that 32 // they cannot be used as is on vectors, for which Lo is always stored first. 34 SDValue &Lo, SDValue &Hi) { 36 GetExpandedOp(Op, Lo, Hi); 39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { argument 53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); local 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 33 ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 148 ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 155 ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 167 ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 201 ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, SDValue &Hi) argument 243 ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 314 SDValue Lo, Hi; local 332 SDValue Lo, Hi; local 356 SDValue Lo, Hi; local 403 SDValue Lo, Hi; local 433 SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 439 SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 463 SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 476 SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeTypes.cpp | 764 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo, argument 770 Lo = Entry.first; 774 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo, argument 776 assert(Lo.getValueType() == 778 Hi.getValueType() == Lo.getValueType() && 780 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant. 781 AnalyzeNewValue(Lo); 787 Entry.first = Lo; 791 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo, argument 797 Lo 801 SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi) argument 818 GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi) argument 828 SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi) argument 972 GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi) argument 1000 JoinIntegers(SDValue Lo, SDValue Hi) argument 1110 SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) argument 1124 SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeDAG.cpp | 392 SDValue Lo = Val; local 397 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 403 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 523 SDValue Lo, Hi; local 525 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 540 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 550 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 552 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 672 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); local 674 if (TLI.isBigEndian()) std::swap(Lo, H [all...] |
H A D | LegalizeFloatTypes.cpp | 822 SDValue Lo, Hi; local 823 Lo = Hi = SDValue(); 837 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 838 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 839 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 841 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 842 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 843 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 844 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 845 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, H 880 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); local 883 ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 895 ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 909 ExpandFloatRes_FADD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 918 ExpandFloatRes_FCEIL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 927 ExpandFloatRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 938 ExpandFloatRes_FCOS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 947 ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 960 ExpandFloatRes_FEXP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 969 ExpandFloatRes_FEXP2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 978 ExpandFloatRes_FFLOOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 987 ExpandFloatRes_FLOG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 996 ExpandFloatRes_FLOG2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1005 ExpandFloatRes_FLOG10(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1014 ExpandFloatRes_FMA(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1027 ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1040 ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1051 ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1059 ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1066 ExpandFloatRes_FPOW(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1075 ExpandFloatRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1084 ExpandFloatRes_FRINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1093 ExpandFloatRes_FSIN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1102 ExpandFloatRes_FSQRT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1111 ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1124 ExpandFloatRes_FTRUNC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1133 ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1165 ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1344 SDValue Lo, Hi; local 1456 SDValue Lo, Hi; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global 60 Hi, Lo, enumerator in enum:llvm::PPCISD::NodeType
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H A D | PPCISelDAGToDAG.cpp | 772 unsigned Lo = Imm & 0xFFFF; local 777 // Just the Lo bits. 778 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 779 } else if (Lo) { 783 // And Lo bits. 785 SDValue(Result, 0), getI32Imm(Lo)); 807 if ((Lo = Remainder & 0xFFFF)) { 809 SDValue(Result, 0), getI32Imm(Lo));
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DIE.h | 304 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) argument 305 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
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H A D | AsmPrinter.cpp | 1360 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size 1361 /// in bytes of the directive is specified by Size and Hi/Lo specify the 1363 void AsmPrinter::EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, argument 1365 // Get the Hi-Lo expression. 1368 MCSymbolRefExpr::Create(Lo, OutContext), 1382 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo" 1383 /// where the size in bytes of the directive is specified by Size and Hi/Lo 1386 const MCSymbol *Lo, unsigned Size) 1389 // Emit Hi+Offset - Lo 1396 // Get the Hi+Offset-Lo expressio 1385 EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset, const MCSymbol *Lo, unsigned Size) const argument [all...] |
H A D | DwarfCompileUnit.cpp | 99 const MCSymbol *Hi, const MCSymbol *Lo) { 100 DIEValue *Value = new (DIEValueAllocator) DIEDelta(Hi, Lo); 98 addDelta(DIE *Die, unsigned Attribute, unsigned Form, const MCSymbol *Hi, const MCSymbol *Lo) argument
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/external/skia/src/core/ |
H A D | SkMath.cpp | 182 uint32_t Lo = C + (B << 16); local 183 uint32_t Hi = A + (B >>16) + (Lo < C); 187 int32_t R = (Hi << 2) + (Lo >> 30);
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/external/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 876 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 882 /// \param Lo - The classification for the parts of the type 888 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 893 /// \param Lo - The classification for the parts of the type 904 /// be passed in Memory then at least the classification of \arg Lo 907 /// The \arg Lo class will be NoClass iff the argument is ignored. 909 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 911 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const; 1066 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, argument 1090 Lo 1139 classify(QualType Ty, uint64_t OffsetBase, Class &Lo, Class &Hi) const argument [all...] |
/external/llvm/lib/Analysis/ |
H A D | DIBuilder.cpp | 714 DISubrange DIBuilder::getOrCreateSubrange(int64_t Lo, int64_t Hi) { argument 717 ConstantInt::get(Type::getInt64Ty(VMContext), Lo),
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 572 SDValue Lo(Hi.getNode(), 1); 573 SDValue Ops[] = { Lo, Hi }; 589 SDValue Lo(Hi.getNode(), 1); 590 SDValue Ops[] = { Lo, Hi }; 686 SDValue Lo(Hi.getNode(), 1); 687 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 694 SDValue Lo(Hi.getNode(), 1); 695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 705 SDValue Lo(Hi.getNode(), 1); 710 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, H 1434 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); local [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAndOrXor.cpp | 270 /// InsertRangeTest - Emit a computation of: (V >= Lo && V < Hi) if Inside is 271 /// true, otherwise (V < Lo || V >= Hi). In practice, we emit the more efficient 272 /// (V-Lo) <u Hi-Lo. This method expects that Lo <= Hi. isSigned indicates 273 /// whether to treat the V, Lo and HI as signed or not. IB is the location to 275 Value *InstCombiner::InsertRangeTest(Value *V, Constant *Lo, Constant *Hi, argument 278 ICmpInst::ICMP_SLE:ICmpInst::ICMP_ULE), Lo, Hi))->getZExtValue() && 279 "Lo is not <= Hi in range emission code!"); 282 if (Lo [all...] |