Searched defs:RegVT (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp350 EVT RegVT = Value.getValueType(); local
351 EVT RegSclVT = RegVT.getScalarType();
H A DLegalizeDAG.cpp320 EVT RegVT = local
325 unsigned RegBytes = RegVT.getSizeInBits() / 8;
329 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
342 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
445 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); local
447 unsigned RegBytes = RegVT.getSizeInBits() / 8;
451 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
461 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
479 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chai
[all...]
H A DSelectionDAGBuilder.h275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
281 EVT RegVT; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
H A DLegalizeIntegerTypes.cpp702 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); local
704 // The argument is passed as NumRegs registers of type RegVT.
708 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
724 DAG.getConstant(i * RegVT.getSizeInBits(),
H A DSelectionDAGBuilder.cpp1732 B.RegVT = VT;
1766 EVT VT = BB.RegVT;
5779 EVT RegVT = *PhysReg.second->vt_begin(); local
5780 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5782 RegVT, OpInfo.CallOperand);
5783 OpInfo.ConstraintVT = RegVT;
5784 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5789 RegVT = EVT::getIntegerVT(Context,
5792 RegVT, OpInfo.CallOperand);
5793 OpInfo.ConstraintVT = RegVT;
5800 EVT RegVT; local
6156 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); local
6693 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); local
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/external/llvm/lib/Target/PTX/
H A DPTXISelLowering.cpp253 EVT RegVT = Ins[i].VT; local
254 const TargetRegisterClass* TRC = getRegClassFor(RegVT);
258 if (RegVT == MVT::i1)
260 else if (RegVT == MVT::i16)
262 else if (RegVT == MVT::i32)
264 else if (RegVT == MVT::i64)
266 else if (RegVT == MVT::f32)
268 else if (RegVT == MVT::f64)
277 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain,
331 EVT RegVT local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp839 EVT RegVT = VA.getLocVT(); local
840 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
844 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
845 } else if (RegVT == MVT::i64) {
849 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp722 MVT RegVT = VA.getLocVT(); local
730 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
733 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
736 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
897 MVT RegVT = VA.getLocVT(); local
901 if (RegVT == MVT::i32)
903 else if (RegVT == MVT::f32)
906 llvm_unreachable("RegVT not supported by LowerFormalArguments");
911 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
924 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValu
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp322 EVT RegVT = VA.getLocVT(); local
323 switch (RegVT.getSimpleVT().SimpleTy) {
328 << RegVT.getSimpleVT().SimpleTy << "\n";
336 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
342 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1113 EVT RegVT = VA.getLocVT(); local
1114 switch (RegVT.getSimpleVT().SimpleTy) {
1119 << RegVT.getSimpleVT().SimpleTy << "\n";
1127 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2777 EVT RegVT = VA.getLocVT(); local
2781 if (RegVT == MVT::i32)
2783 else if (RegVT == MVT::i64)
2785 else if (RegVT == MVT::f32)
2787 else if (RegVT == MVT::f64)
2790 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2795 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2807 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
2813 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2814 (RegVT
[all...]
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1816 EVT RegVT = VA.getLocVT(); local
1830 if (RegVT == MVT::v2f64) {
2598 EVT RegVT = VA.getLocVT(); local
2629 if (RegVT == MVT::f32)
2631 else if (RegVT == MVT::f64)
2633 else if (RegVT == MVT::v2f64)
2635 else if (RegVT == MVT::i32)
2639 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2643 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2656 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValu
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/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1851 EVT RegVT = VA.getLocVT(); local
1853 if (RegVT == MVT::i32)
1855 else if (Is64Bit && RegVT == MVT::i64)
1857 else if (RegVT == MVT::f32)
1859 else if (RegVT == MVT::f64)
1861 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1863 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1865 else if (RegVT
2219 EVT RegVT = VA.getLocVT(); local
14298 EVT RegVT = Ld->getValueType(0); local
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