Searched refs:CP0C1_PC (Results 1 - 2 of 2) sorted by relevance

/external/qemu/target-mips/
H A Dtranslate_init.c32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
355 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
376 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
402 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
429 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
H A Dcpu.h347 #define CP0C1_PC 4 macro

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