Searched refs:DestReg (Results 1 - 25 of 48) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg,
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
81 unsigned DestReg, int FI,
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
86 isARMLowRegister(DestReg))) && "Unknown regclass!");
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
90 isARMLowRegister(DestReg))) {
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2RegisterInfo.h35 unsigned DestReg, unsigned SubIdx, int Val,
H A DThumb2InstrInfo.cpp114 unsigned DestReg, unsigned SrcReg,
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
153 unsigned DestReg, int FI,
169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
179 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 if (DestReg != ARM::SP && DestReg !
112 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
152 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DThumb1RegisterInfo.cpp67 unsigned DestReg, unsigned SubIdx,
78 .addReg(DestReg, getDefRegState(true), SubIdx)
92 unsigned DestReg, unsigned BaseReg,
98 bool isHigh = !isARMLowRegister(DestReg) ||
109 unsigned LdReg = DestReg;
110 if (DestReg == ARM::SP) {
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
133 if (DestReg == ARM::SP || isSub)
169 unsigned DestReg, unsigned BaseReg,
185 if (DestReg
64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
89 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
166 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
341 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
[all...]
H A DThumb2InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
56 unsigned DestReg, int FrameIndex,
H A DARMBaseInstrInfo.h111 unsigned DestReg, unsigned SrcReg,
122 unsigned DestReg, int FrameIndex,
136 unsigned DestReg, unsigned SubIdx,
361 unsigned DestReg, unsigned BaseReg, int NumBytes,
367 unsigned DestReg, unsigned BaseReg, int NumBytes,
372 unsigned DestReg, unsigned BaseReg,
H A DThumb1RegisterInfo.h40 unsigned DestReg, unsigned SubIdx, int Val,
/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitTFRCondSets.cpp87 int DestReg = MI->getOperand(0).getReg(); local
93 if (DestReg != SrcReg1) {
95 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
97 if (DestReg != SrcReg2) {
99 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
104 int DestReg = MI->getOperand(0).getReg(); local
109 DestReg).addReg(SrcReg1).addImm(Immed1);
111 DestReg).addReg(SrcReg1).addImm(Immed2);
H A DHexagonInstrInfo.h71 unsigned DestReg, unsigned SrcReg,
87 unsigned DestReg, int FrameIndex,
91 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp323 unsigned DestReg, unsigned SrcReg,
326 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
328 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
330 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
332 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
334 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
336 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
343 BuildMI(MBB, I, DL, MCID, DestReg)
346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
522 unsigned DestReg, in
321 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
521 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
630 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
H A DPPCInstrInfo.h76 unsigned DestReg, int FrameIdx,
120 unsigned DestReg, unsigned SrcReg,
131 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp104 unsigned DestReg, unsigned SrcReg,
108 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
121 if (Mips::CCRRegClass.contains(DestReg))
123 else if (Mips::FGR32RegClass.contains(DestReg))
125 else if (DestReg == Mips::HI)
126 Opc = Mips::MTHI, DestReg = 0;
127 else if (DestReg == Mips::LO)
128 Opc = Mips::MTLO, DestReg = 0;
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcRe
102 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
209 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
H A DMipsInstrInfo.h81 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h199 unsigned DestReg) {
201 .addReg(DestReg, RegState::Define);
212 unsigned DestReg) {
215 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
222 unsigned DestReg) {
225 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
232 unsigned DestReg) {
235 return BuildMI(BB, MII, DL, MCID, DestReg);
239 return BuildMI(BB, MII, DL, MCID, DestReg);
294 unsigned DestReg) {
196 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
208 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
218 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
228 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
291 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
[all...]
/external/llvm/lib/Target/CellSPU/
H A DSPUInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
62 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
H A DMSP430InstrInfo.cpp64 unsigned DestReg, int FrameIdx,
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
62 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
88 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h87 unsigned DestReg, unsigned SrcReg,
98 unsigned DestReg, int FrameIndex,
H A DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg,
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
321 unsigned DestReg, int FI,
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg)
280 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
320 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.h66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
H A DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg,
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
353 if (DestReg == XCore::SP && GRSrc) {
378 unsigned DestReg, int FrameIndex,
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
334 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
376 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/CodeGen/
H A DStrongPHIElimination.cpp243 unsigned DestReg = BBI->getOperand(0).getReg(); local
244 addReg(DestReg);
251 unionRegs(DestReg, SrcReg);
287 unsigned DestReg = BBI->getOperand(0).getReg(); local
288 addReg(DestReg);
293 unionRegs(DestReg, SrcReg);
317 unsigned DestReg = PHI->getOperand(0).getReg(); local
318 if (!InsertedDestCopies.count(DestReg))
319 MergeLIsAndRename(DestReg, NewReg);
340 unsigned DestReg local
460 unsigned DestReg = PHI->getOperand(0).getReg(); local
541 unsigned DestReg = MO.getReg(); local
737 unsigned DestReg = PHI->getOperand(0).getReg(); local
[all...]
H A DPHIElimination.cpp202 unsigned DestReg = MPhi->getOperand(0).getReg(); local
219 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
231 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
235 TII->get(TargetOpcode::COPY), DestReg)
274 LV->addVirtualRegisterDead(DestReg, PHICopy);
275 LV->removeVirtualRegisterDead(DestReg, MPhi);

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